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| author | J. Bruce Fields <bfields@citi.umich.edu> | 2009-10-27 18:45:17 -0400 |
|---|---|---|
| committer | J. Bruce Fields <bfields@citi.umich.edu> | 2009-10-27 18:45:17 -0400 |
| commit | e343eb0d60f74547e0aeb5bd151105c2e6cfe588 (patch) | |
| tree | 92586df0daf3298262a957640e5c86679c963f41 /drivers/gpu/drm/radeon/r420.c | |
| parent | ddc04fd4d5163aee9ebdb38a56c365b602e2b7b7 (diff) | |
| parent | 012abeea669ea49636cf952d13298bb68654146a (diff) | |
Merge commit 'v2.6.32-rc5' into for-2.6.33
Diffstat (limited to 'drivers/gpu/drm/radeon/r420.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r420.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 49a2fdc57d27..5c7fe52de30e 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c @@ -155,6 +155,9 @@ static void r420_debugfs(struct radeon_device *rdev) static void r420_clock_resume(struct radeon_device *rdev) { u32 sclk_cntl; + + if (radeon_dynclks != -1 && radeon_dynclks) + radeon_atom_set_clock_gating(rdev, 1); sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); if (rdev->family == CHIP_R420) @@ -167,6 +170,8 @@ static int r420_startup(struct radeon_device *rdev) int r; r300_mc_program(rdev); + /* Resume clock */ + r420_clock_resume(rdev); /* Initialize GART (initialize after TTM so we can allocate * memory through TTM but finalize after TTM) */ if (rdev->flags & RADEON_IS_PCIE) { @@ -267,7 +272,6 @@ int r420_init(struct radeon_device *rdev) { int r; - rdev->new_init_path = true; /* Initialize scratch registers */ radeon_scratch_init(rdev); /* Initialize surface registers */ |