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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-05 10:05:49 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-07-05 18:09:11 -0400 |
| commit | 67d5ced503db5b44cb82f378c9cb3f0e77a94e7f (patch) | |
| tree | 99f8b0b84ca5f72e334437eb97422015f4d1ab74 /drivers/gpu/drm/radeon/radeon_asic.h | |
| parent | edcaa5b12525f0de79e027ea1ae8a96ee7d785b3 (diff) | |
drm/radeon: fix surface setup on r1xx
r1xx asics have a slightly different surface register
setup compared to newer asics. There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.
With this fixed, the special rn50 handling can go.
Noticed-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
0 files changed, 0 insertions, 0 deletions