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authorAlex Deucher <alexander.deucher@amd.com>2013-02-13 16:38:25 -0500
committerAlex Deucher <alexander.deucher@amd.com>2013-06-27 19:16:23 -0400
commiteaa778aff0f19c35e9380c2bc5513b5b60ce01a6 (patch)
tree153c9da3bd059419edabbef11a1e0e508efe939b /drivers/gpu/drm/radeon/radeon_mode.h
parente37e6a0e4fc68cfa9c54410170577de385231de0 (diff)
drm/radeon/atom: add helper to calcuate mpll params
There's a new table for calculating the memory pll parameters on SI. Required for SI DPM support. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_mode.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 02bf4a755f34..e5ea915993d9 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -519,6 +519,30 @@ struct atom_clock_dividers {
u32 flags;
};
+struct atom_mpll_param {
+ union {
+ struct {
+#ifdef __BIG_ENDIAN
+ u32 reserved : 8;
+ u32 clkfrac : 12;
+ u32 clkf : 12;
+#else
+ u32 clkf : 12;
+ u32 clkfrac : 12;
+ u32 reserved : 8;
+#endif
+ };
+ u32 fb_div;
+ };
+ u32 post_div;
+ u32 bwcntl;
+ u32 dll_speed;
+ u32 vco_mode;
+ u32 yclk_sel;
+ u32 qdr;
+ u32 half_rate;
+};
+
#define MEM_TYPE_GDDR5 0x50
#define MEM_TYPE_GDDR4 0x40
#define MEM_TYPE_GDDR3 0x30