diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-11-15 16:35:55 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-01-08 18:42:24 -0500 |
| commit | 4a5c8ea59f8360f354158fca039ee7fbef0fa4dd (patch) | |
| tree | a3f90a21e8fc301d7e03d0145c853c0abd06c5ea /drivers/gpu/drm/radeon/sid.h | |
| parent | b5470b036e14d063655cc01d22ea5d727042860a (diff) | |
drm/radeon: implement pci config reset for SI (v2)
pci config reset is a low level reset that resets
the entire chip from the bus interface. It can
be more reliable if soft reset fails.
v2: hide behind module parameter
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index b322acc48097..caa3e61a38c2 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -94,6 +94,8 @@ #define CG_SPLL_FUNC_CNTL_2 0x604 #define SCLK_MUX_SEL(x) ((x) << 0) #define SCLK_MUX_SEL_MASK (0x1ff << 0) +#define SPLL_CTLREQ_CHG (1 << 23) +#define SCLK_MUX_UPDATE (1 << 26) #define CG_SPLL_FUNC_CNTL_3 0x608 #define SPLL_FB_DIV(x) ((x) << 0) #define SPLL_FB_DIV_MASK (0x3ffffff << 0) @@ -101,7 +103,10 @@ #define SPLL_DITHEN (1 << 28) #define CG_SPLL_FUNC_CNTL_4 0x60c +#define SPLL_STATUS 0x614 +#define SPLL_CHG_STATUS (1 << 1) #define SPLL_CNTL_MODE 0x618 +#define SPLL_SW_DIR_CONTROL (1 << 0) # define SPLL_REFCLK_SEL(x) ((x) << 8) # define SPLL_REFCLK_SEL_MASK 0xFF00 @@ -559,6 +564,8 @@ # define MRDCK0_BYPASS (1 << 24) # define MRDCK1_BYPASS (1 << 25) +#define MPLL_CNTL_MODE 0x2bb0 +# define MPLL_MCLK_SEL (1 << 11) #define MPLL_FUNC_CNTL 0x2bb4 #define BWCTRL(x) ((x) << 20) #define BWCTRL_MASK (0xff << 20) |