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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-03 15:14:25 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-07-03 17:37:31 -0400 |
| commit | 338a95a95508537e23c82d59a2d87be6fde4b6ff (patch) | |
| tree | a07986ff4466ca2acccc83cd450a86da53945d89 /drivers/gpu/drm/radeon/sumo_dpm.c | |
| parent | 62fa44bf7b75e3e482655baa15309bf3ea122bd3 (diff) | |
drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag
Some asic revisions need to disable PG when UVD is active.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sumo_dpm.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/sumo_dpm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index b13448f13ee8..dc599060a9a4 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -824,7 +824,9 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev, radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); if (pi->enable_gfx_power_gating) { - sumo_gfx_powergating_enable(rdev, true); + if (!pi->disable_gfx_power_gating_in_uvd || + !r600_is_uvd_state(new_rps->class, new_rps->class2)) + sumo_gfx_powergating_enable(rdev, true); } } |