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| author | Iago Toral Quiroga <itoral@igalia.com> | 2021-09-15 12:05:07 +0200 |
|---|---|---|
| committer | Melissa Wen <melissa.srw@gmail.com> | 2021-09-15 18:43:37 +0100 |
| commit | e4f868191138975f2fdf2f37c11318b47db4acc9 (patch) | |
| tree | 507fc03fd7c9209bbef044cf553c2318ce271f72 /drivers/gpu/drm/radeon | |
| parent | bcf26654a38f8e55ecac4635dac2e72c161d0063 (diff) | |
drm/v3d: fix wait for TMU write combiner flush
The hardware sets the TMUWCF bit back to 0 when the TMU write
combiner flush completes so we should be checking for that instead
of the L2TFLS bit.
v2 (Melissa Wen):
- Add Signed-off-by and Fixes tags.
- Change the error message for the timeout to be more clear.
Fixes spurious Vulkan CTS failures in:
dEQP-VK.binding_model.descriptorset_random.*
Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch.")
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Melissa Wen <melissa.srw@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210915100507.3945-1-itoral@igalia.com
Diffstat (limited to 'drivers/gpu/drm/radeon')
0 files changed, 0 insertions, 0 deletions