diff options
| author | Thierry Reding <treding@nvidia.com> | 2018-02-05 15:16:18 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:45 +0100 |
| commit | 4ff9ba5674d16857372b936a8d08920a9851d1cd (patch) | |
| tree | ec7d59a5f9f9055b3a0dc132ddd3705a0f6fbf24 /drivers/gpu/drm/tegra/dp.c | |
| parent | 6c651b13e436030f996bcfb2f76833af94e44531 (diff) | |
drm/tegra: dp: Read alternate scrambler reset capability from sink
Parse from the sink capabilities whether or not the eDP alternate
scrambler reset value of 0xfffe is supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dp.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/dp.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 0bd87cff4575..1f48c2190e3b 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -14,6 +14,7 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps) caps->tps3_supported = false; caps->fast_training = false; caps->channel_coding = false; + caps->alternate_scrambler_reset = false; } void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, @@ -23,6 +24,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, dest->tps3_supported = src->tps3_supported; dest->fast_training = src->fast_training; dest->channel_coding = src->channel_coding; + dest->alternate_scrambler_reset = src->alternate_scrambler_reset; } static void drm_dp_link_reset(struct drm_dp_link *link) @@ -71,6 +73,9 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) link->caps.fast_training = drm_dp_fast_training_cap(dpcd); link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); + if (drm_dp_alternate_scrambler_reset_cap(dpcd)) + link->caps.alternate_scrambler_reset = true; + link->rate = link->max_rate; link->lanes = link->max_lanes; |