diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-08-30 17:41:00 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-10-20 14:19:54 +0200 |
| commit | a2f2f7403e1ea192ce79584d7050c46e455409dd (patch) | |
| tree | b303ec55ecd6a5cae2f5b1fa11fa2e8a8cd9fedb /drivers/gpu/drm/tegra | |
| parent | 39e08affecf0998be1b01f4752016e33fa98eb9a (diff) | |
drm/tegra: dc: Perform a complete reset sequence
In order for the reset to be applied properly, the module clock must be
enabled during the assertion.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
| -rw-r--r-- | drivers/gpu/drm/tegra/dc.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index d5a63230e509..24a5ef4f5bb8 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1997,8 +1997,22 @@ static int tegra_dc_probe(struct platform_device *pdev) return PTR_ERR(dc->rst); } - if (!dc->soc->broken_reset) - reset_control_assert(dc->rst); + /* assert reset and disable clock */ + if (!dc->soc->broken_reset) { + err = clk_prepare_enable(dc->clk); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + err = reset_control_assert(dc->rst); + if (err < 0) + return err; + + usleep_range(2000, 4000); + + clk_disable_unprepare(dc->clk); + } if (dc->soc->has_powergate) { if (dc->pipe == 0) |