diff options
| author | Maxime Ripard <maxime@cerno.tech> | 2020-06-11 15:36:50 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-07-07 10:51:21 +0200 |
| commit | 811a850cbddef47623c5f6197154a05bb4efc7c9 (patch) | |
| tree | c730e0f3955fb26dd8fd47146188fbf788396db9 /drivers/gpu/drm/vc4/vc4_crtc.c | |
| parent | 5a20ff8bf3d455855d445594152cc6a7760a3793 (diff) | |
drm/vc4: crtc: Only access the PixelValve registers if we have to
The CRTC hooks are called both for the TXP and the pixelvalve, yet some
will read / write the registers as if the device was a pixelvalve, which
won't really work.
Let's make sure we only access those registers if we are running on a
PixelValve.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/b55e31869304c748920c261eba87b3275dbeb297.1591882579.git-series.maxime@cerno.tech
Diffstat (limited to 'drivers/gpu/drm/vc4/vc4_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_crtc.c | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index efc21fa9e6a8..f715736f668c 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -357,6 +357,7 @@ static void require_hvs_enabled(struct drm_device *dev) static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); struct drm_device *dev = crtc->dev; struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); int ret; @@ -366,10 +367,12 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, /* Disable vblank irq handling before crtc is disabled. */ drm_crtc_vblank_off(crtc); - CRTC_WRITE(PV_V_CONTROL, - CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); - ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); - WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + if (!vc4_state->feed_txp) { + CRTC_WRITE(PV_V_CONTROL, + CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); + ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); + WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + } vc4_hvs_atomic_disable(crtc, old_state); @@ -502,6 +505,10 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc, static int vc4_enable_vblank(struct drm_crtc *crtc) { struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); + + if (vc4_state->feed_txp) + return 0; CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); @@ -511,6 +518,10 @@ static int vc4_enable_vblank(struct drm_crtc *crtc) static void vc4_disable_vblank(struct drm_crtc *crtc) { struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); + + if (vc4_state->feed_txp) + return; CRTC_WRITE(PV_INTEN, 0); } |