diff options
| author | Vitaly Lubart <vitaly.lubart@intel.com> | 2023-08-28 19:24:03 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:43:00 -0500 |
| commit | 87a4c85d3a3ed579c86fd2612715ccb94c4001ff (patch) | |
| tree | 38d2e2f9dbbe385a96624a7dd0ef906198263106 /drivers/gpu/drm/xe/xe_irq.c | |
| parent | 437d7a84ada7a4cfeab2d9555c446936c3fb09f4 (diff) | |
drm/xe/gsc: add gsc device support
Create mei-gscfi auxiliary device and configure interrupts
to be consumed by mei-gsc device driver.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_irq.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_irq.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c index 4cc5f7086b4c..5631e5e1ea20 100644 --- a/drivers/gpu/drm/xe/xe_irq.c +++ b/drivers/gpu/drm/xe/xe_irq.c @@ -141,6 +141,7 @@ void xe_irq_enable_hwe(struct xe_gt *gt) struct xe_device *xe = gt_to_xe(gt); u32 ccs_mask, bcs_mask; u32 irqs, dmask, smask; + u32 gsc_mask = 0; if (xe_device_uc_enabled(xe)) { irqs = GT_RENDER_USER_INTERRUPT | @@ -190,9 +191,13 @@ void xe_irq_enable_hwe(struct xe_gt *gt) xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask); xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask); - if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) { - xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, irqs); - xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~irqs); + if (xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER)) + gsc_mask = irqs; + else if (HAS_HECI_GSCFI(xe)) + gsc_mask = GSC_IRQ_INTF(1); + if (gsc_mask) { + xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, gsc_mask); + xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~gsc_mask); } } } @@ -306,7 +311,11 @@ static void gt_irq_handler(struct xe_tile *tile, } if (class == XE_ENGINE_CLASS_OTHER) { - gt_other_irq_handler(engine_gt, instance, intr_vec); + /* HECI GSCFI interrupts come from outside of GT */ + if (HAS_HECI_GSCFI(xe) && instance == OTHER_GSC_INSTANCE) + xe_heci_gsc_irq_handler(xe, intr_vec); + else + gt_other_irq_handler(engine_gt, instance, intr_vec); continue; } } @@ -480,8 +489,9 @@ static void gt_irq_reset(struct xe_tile *tile) if (ccs_mask & (BIT(2)|BIT(3))) xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~0); - if (tile->media_gt && - xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) { + if ((tile->media_gt && + xe_hw_engine_mask_per_class(tile->media_gt, XE_ENGINE_CLASS_OTHER)) || + HAS_HECI_GSCFI(tile_to_xe(tile))) { xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, 0); xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~0); } |