diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-02-24 16:15:42 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:29:21 -0500 |
| commit | 63955b3bfa0b69fd86b9e827e0f14f3fa4508826 (patch) | |
| tree | 0fe09f93495aeb45c345dd2967e39a940a078d5b /drivers/gpu/drm/xe/xe_ring_ops.c | |
| parent | 0992884d09cc1c91e9c3310a9204eb080db37714 (diff) | |
drm/xe: Remove dependency on intel_gpu_commands.h
Copy the macros used by xe in intel_gpu_commands.h to
regs/xe_gpu_commands.h. PIPE_CONTROL_3D_ENGINE_FLAGS and
PIPE_CONTROL_3D_ARCH_FLAGS were already defined in
drivers/gpu/drm/xe/xe_ring_ops.c and only used there. So let that define
to be used instead of also adding to the new header.
v2: Let PIPE_CONTROL_3D_ENGINE_FLAGS/PIPE_CONTROL_3D_ARCH_FLAGS in the
only .c that uses it instead of redefining (Matt Roper)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_ring_ops.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_ring_ops.c | 49 |
1 files changed, 25 insertions, 24 deletions
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index 6275f8c34878..ef8cef20acd6 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -5,6 +5,7 @@ #include "xe_ring_ops.h" +#include "regs/xe_gpu_commands.h" #include "regs/xe_gt_regs.h" #include "regs/xe_lrc_layout.h" #include "xe_engine_types.h" @@ -14,9 +15,32 @@ #include "xe_sched_job.h" #include "xe_vm_types.h" -#include "gt/intel_gpu_commands.h" #include "i915_reg.h" +/* + * 3D-related flags that can't be set on _engines_ that lack access to the 3D + * pipeline (i.e., CCS engines). + */ +#define PIPE_CONTROL_3D_ENGINE_FLAGS (\ + PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \ + PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ + PIPE_CONTROL_TILE_CACHE_FLUSH | \ + PIPE_CONTROL_DEPTH_STALL | \ + PIPE_CONTROL_STALL_AT_SCOREBOARD | \ + PIPE_CONTROL_PSD_SYNC | \ + PIPE_CONTROL_AMFS_FLUSH | \ + PIPE_CONTROL_VF_CACHE_INVALIDATE | \ + PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET) + +/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */ +#define PIPE_CONTROL_3D_ARCH_FLAGS ( \ + PIPE_CONTROL_3D_ENGINE_FLAGS | \ + PIPE_CONTROL_INDIRECT_STATE_DISABLE | \ + PIPE_CONTROL_FLUSH_ENABLE | \ + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ + PIPE_CONTROL_DC_FLUSH_ENABLE) + + static u32 preparser_disable(bool state) { return MI_ARB_CHECK | BIT(8) | state; @@ -181,29 +205,6 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc, xe_lrc_write_ring(lrc, dw, i * sizeof(*dw)); } -/* - * 3D-related flags that can't be set on _engines_ that lack access to the 3D - * pipeline (i.e., CCS engines). - */ -#define PIPE_CONTROL_3D_ENGINE_FLAGS (\ - PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \ - PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ - PIPE_CONTROL_TILE_CACHE_FLUSH | \ - PIPE_CONTROL_DEPTH_STALL | \ - PIPE_CONTROL_STALL_AT_SCOREBOARD | \ - PIPE_CONTROL_PSD_SYNC | \ - PIPE_CONTROL_AMFS_FLUSH | \ - PIPE_CONTROL_VF_CACHE_INVALIDATE | \ - PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET) - -/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */ -#define PIPE_CONTROL_3D_ARCH_FLAGS ( \ - PIPE_CONTROL_3D_ENGINE_FLAGS | \ - PIPE_CONTROL_INDIRECT_STATE_DISABLE | \ - PIPE_CONTROL_FLUSH_ENABLE | \ - PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ - PIPE_CONTROL_DC_FLUSH_ENABLE) - static void __emit_job_gen12_render_compute(struct xe_sched_job *job, struct xe_lrc *lrc, u64 batch_addr, u32 seqno) |