diff options
| author | Imre Deak <imre.deak@intel.com> | 2016-04-01 16:02:34 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2016-04-15 14:19:52 +0300 |
| commit | 28ca6931f07f83a397e10493a798c1f00c415c40 (patch) | |
| tree | ef6922d7768a2cee78b4ee438b7ff60ef8462cc5 /drivers/gpu/drm | |
| parent | d1e082ffb898bd9cf7cb58358917a415d2dd0a13 (diff) | |
drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only
This register is read-only, so we have never actually set
OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
comment about this. I filed a specification update request to clarify
this there.
CC: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: David Weinehall <david.weinehall@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-4-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 921edf183d22..2b9e79d59c13 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, * enabled. * TODO: port C is only connected on BXT-P, so on BXT0/1 we should * power down the second channel on PHY0 as well. + * + * FIXME: Clarify programming of the following, the register is + * read-only with bit 6 fixed at 0 at least in stepping A. */ if (phy == DPIO_PHY1) val |= OCL2_LDOFUSE_PWR_DIS; |