diff options
| author | Dave Airlie <airlied@redhat.com> | 2017-12-07 06:28:22 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2017-12-07 06:28:22 +1000 |
| commit | 9c606cd4117a3c45e04a6616b1a0dbeb18eeee62 (patch) | |
| tree | aa6c1db29e1a3f687c81fa03aecd24992a76e993 /drivers/gpu/drm | |
| parent | c5dd52f653fa74f8f4771425c6db33609ad21258 (diff) | |
| parent | 3997eea57caf542e9327df9b6bb2882a57c4c421 (diff) | |
Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next
First feature request for 4.16. Highlights:
- RV and Vega header cleanups
- TTM operation context support
- 48 bit GPUVM fixes for Vega/RV
- More smatch fixes
- ECC support for vega10
- Resizeable BAR support
- Multi-display sync support in DC
- SR-IOV fixes
- Various scheduler improvements
- GPU reset fixes and vram lost tracking
- Clean up DC/powerplay interfaces
- DCN display fixes
- Various DC fixes
* 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux: (291 commits)
drm/radeon: Use drm_fb_helper_lastclose() and _poll_changed()
drm/amdgpu: Use drm_fb_helper_lastclose() and _poll_changed()
drm/amd/display: Use drm_fb_helper_poll_changed()
drm/ttm: swap consecutive allocated pooled pages v4
drm/amdgpu: fix amdgpu_sync_resv v2
drm/ttm: swap consecutive allocated cached pages v3
drm/amd/amdgpu: set gtt size according to system memory size only
drm/amdgpu: Get rid of dep_sync as a seperate object.
drm/amdgpu: allow specifying vm_block_size for multi level PDs v2
drm/amdgpu: move validation of the VM size into the VM code
drm/amdgpu: allow non pot VM size values
drm/amdgpu: choose number of VM levels based on VM size
drm/amdgpu: unify VM size handling of Vega10 with older generation
drm/amdgpu: fix amdgpu_vm_num_entries
drm/amdgpu: fix VM PD addr shift
drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)
drm/amd/display: Don't call dm_log_to_buffer directly in dc_conn_log
drm/amd/display: Add dm_logger_append_va API
drm/ttm: Use a static string instead of an array of char *
drm/amd/display: remove usage of legacy_cursor_update
...
Diffstat (limited to 'drivers/gpu/drm')
309 files changed, 17733 insertions, 74416 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0b14b5373783..5e2958a79928 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -47,6 +47,8 @@ #include <drm/amdgpu_drm.h> #include <kgd_kfd_interface.h> +#include "dm_pp_interface.h" +#include "kgd_pp_interface.h" #include "amd_shared.h" #include "amdgpu_mode.h" @@ -59,7 +61,6 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" -#include "amd_powerplay.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "amdgpu_uvd.h" @@ -67,11 +68,11 @@ #include "amdgpu_vcn.h" #include "amdgpu_mn.h" #include "amdgpu_dm.h" - #include "gpu_scheduler.h" #include "amdgpu_virt.h" #include "amdgpu_gart.h" + /* * Modules parameters. */ @@ -177,6 +178,10 @@ extern int amdgpu_cik_support; #define CIK_CURSOR_WIDTH 128 #define CIK_CURSOR_HEIGHT 128 +/* GPU RESET flags */ +#define AMDGPU_RESET_INFO_VRAM_LOST (1 << 0) +#define AMDGPU_RESET_INFO_FULLRESET (1 << 1) + struct amdgpu_device; struct amdgpu_ib; struct amdgpu_cs_parser; @@ -735,6 +740,7 @@ struct amdgpu_ctx { struct amdgpu_device *adev; struct amdgpu_queue_mgr queue_mgr; unsigned reset_counter; + unsigned reset_counter_query; uint32_t vram_lost_counter; spinlock_t ring_lock; struct dma_fence **fences; @@ -743,6 +749,7 @@ struct amdgpu_ctx { enum amd_sched_priority init_priority; enum amd_sched_priority override_priority; struct mutex lock; + atomic_t guilty; }; struct amdgpu_ctx_mgr { @@ -1114,7 +1121,6 @@ struct amdgpu_job { struct amdgpu_vm *vm; struct amdgpu_ring *ring; struct amdgpu_sync sync; - struct amdgpu_sync dep_sync; struct amdgpu_sync sched_sync; struct amdgpu_ib *ibs; struct dma_fence *fence; /* the hw fence */ @@ -1405,6 +1411,7 @@ struct amdgpu_fw_vram_usage { }; int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev); +void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev); /* * CGS @@ -1421,6 +1428,13 @@ typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); +struct amd_powerplay { + struct cgs_device *cgs_device; + void *pp_handle; + const struct amd_ip_funcs *ip_funcs; + const struct amd_pm_funcs *pp_funcs; +}; + #define AMDGPU_RESET_MAGIC_NUM 64 struct amdgpu_device { struct device *dev; @@ -1616,9 +1630,6 @@ struct amdgpu_device { /* link all shadow bo */ struct list_head shadow_list; struct mutex shadow_list_lock; - /* link all gtt */ - spinlock_t gtt_list_lock; - struct list_head gtt_list; /* keep an lru list of rings by HW IP */ struct list_head ring_lru_list; spinlock_t ring_lru_list_lock; @@ -1629,7 +1640,8 @@ struct amdgpu_device { /* record last mm index being written through WREG32*/ unsigned long last_mm_index; - bool in_sriov_reset; + bool in_gpu_reset; + struct mutex lock_reset; }; static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) @@ -1823,7 +1835,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) /* Common functions */ -int amdgpu_gpu_reset(struct amdgpu_device *adev); +int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job); bool amdgpu_need_backup(struct amdgpu_device *adev); void amdgpu_pci_config_reset(struct amdgpu_device *adev); bool amdgpu_need_post(struct amdgpu_device *adev); @@ -1835,6 +1847,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); +int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 5432af39a674..c70cda04dbfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -85,7 +85,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); break; default: - dev_info(adev->dev, "kfd not supported on this ASIC\n"); + dev_dbg(adev->dev, "kfd not supported on this ASIC\n"); return; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index f450b69323fa..39f4d0df1ada 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -690,12 +690,12 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); /* set a reasonable default for DP */ if (adev->clock.default_dispclk < 53900) { - DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", - adev->clock.default_dispclk / 100); + DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n", + adev->clock.default_dispclk / 100); adev->clock.default_dispclk = 60000; } else if (adev->clock.default_dispclk <= 60000) { - DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n", - adev->clock.default_dispclk / 100); + DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n", + adev->clock.default_dispclk / 100); adev->clock.default_dispclk = 62500; } adev->clock.dp_extclk = diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index f2b72c7c6857..85d2149b9dbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -948,7 +948,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, (amdgpu_crtc->v_border * 2); mode_info->vblank_time_us = vblank_lines * line_time_us; mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); - mode_info->ref_clock = adev->clock.spll.reference_freq; mode_info = NULL; } } @@ -958,7 +957,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, if (mode_info != NULL) { mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time; mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh; - mode_info->ref_clock = adev->clock.spll.reference_freq; } } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 57abf7abd7a9..4cea9ab237ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -90,6 +90,12 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) goto free_chunk; } + /* skip guilty context job */ + if (atomic_read(&p->ctx->guilty) == 1) { + ret = -ECANCELED; + goto free_chunk; + } + mutex_lock(&p->ctx->lock); /* get chunks */ @@ -337,7 +343,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - u64 initial_bytes_moved, bytes_moved; + struct ttm_operation_ctx ctx = { true, false }; uint32_t domain; int r; @@ -367,15 +373,13 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, retry: amdgpu_ttm_placement_from_domain(bo, domain); - initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); - bytes_moved = atomic64_read(&adev->num_bytes_moved) - - initial_bytes_moved; - p->bytes_moved += bytes_moved; + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + + p->bytes_moved += ctx.bytes_moved; if (adev->mc.visible_vram_size < adev->mc.real_vram_size && bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) - p->bytes_moved_vis += bytes_moved; + p->bytes_moved_vis += ctx.bytes_moved; if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { domain = bo->allowed_domains; @@ -390,6 +394,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, struct amdgpu_bo *validated) { uint32_t domain = validated->allowed_domains; + struct ttm_operation_ctx ctx = { true, false }; int r; if (!p->evictable) @@ -431,7 +436,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT; initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); bytes_moved = atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved; p->bytes_moved += bytes_moved; @@ -470,6 +475,7 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo) static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, struct list_head *validated) { + struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_bo_list_entry *lobj; int r; @@ -487,8 +493,7 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, lobj->user_pages) { amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, - false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) return r; amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, @@ -678,7 +683,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, if (!r && p->uf_entry.robj) { struct amdgpu_bo *uf = p->uf_entry.robj; - r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem); + r = amdgpu_ttm_alloc_gart(&uf->tbo); p->job->uf_addr += amdgpu_bo_gpu_offset(uf); } @@ -781,7 +786,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) return r; r = amdgpu_sync_fence(adev, &p->job->sync, - fpriv->prt_va->last_pt_update); + fpriv->prt_va->last_pt_update, false); if (r) return r; @@ -795,7 +800,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) return r; f = bo_va->last_pt_update; - r = amdgpu_sync_fence(adev, &p->job->sync, f); + r = amdgpu_sync_fence(adev, &p->job->sync, f, false); if (r) return r; } @@ -818,7 +823,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) return r; f = bo_va->last_pt_update; - r = amdgpu_sync_fence(adev, &p->job->sync, f); + r = amdgpu_sync_fence(adev, &p->job->sync, f, false); if (r) return r; } @@ -829,7 +834,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p) if (r) return r; - r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update); + r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false); if (r) return r; @@ -865,8 +870,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *m; struct amdgpu_bo *aobj = NULL; struct amdgpu_cs_chunk *chunk; + uint64_t offset, va_start; struct amdgpu_ib *ib; - uint64_t offset; uint8_t *kptr; chunk = &p->chunks[i]; @@ -876,14 +881,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB) continue; - r = amdgpu_cs_find_mapping(p, chunk_ib->va_start, - &aobj, &m); + va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK; + r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m); if (r) { DRM_ERROR("IB va_start is invalid\n"); return r; } - if ((chunk_ib->va_start + chunk_ib->ib_bytes) > + if ((va_start + chunk_ib->ib_bytes) > (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) { DRM_ERROR("IB va_start+ib_bytes is invalid\n"); return -EINVAL; @@ -896,7 +901,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, } offset = m->start * AMDGPU_GPU_PAGE_SIZE; - kptr += chunk_ib->va_start - offset; + kptr += va_start - offset; memcpy(ib->ptr, kptr, chunk_ib->ib_bytes); amdgpu_bo_kunmap(aobj); @@ -1033,8 +1038,8 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, amdgpu_ctx_put(ctx); return r; } else if (fence) { - r = amdgpu_sync_fence(p->adev, &p->job->sync, - fence); + r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, + true); dma_fence_put(fence); amdgpu_ctx_put(ctx); if (r) @@ -1053,7 +1058,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p, if (r) return r; - r = amdgpu_sync_fence(p->adev, &p->job->sync, fence); + r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true); dma_fence_put(fence); return r; @@ -1194,11 +1199,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, job->uf_sequence = seq; amdgpu_job_free_resources(job); - amdgpu_ring_priority_get(job->ring, - amd_sched_get_job_priority(&job->base)); + amdgpu_ring_priority_get(job->ring, job->base.s_priority); trace_amdgpu_cs_ioctl(job); - amd_sched_entity_push_job(&job->base); + amd_sched_entity_push_job(&job->base, entity); ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); amdgpu_mn_unlock(p->mn); @@ -1570,6 +1574,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, struct amdgpu_bo_va_mapping **map) { struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; + struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va_mapping *mapping; int r; @@ -1590,11 +1595,10 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) { (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains); - r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false, - false); + r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx); if (r) return r; } - return amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem); + return amdgpu_ttm_alloc_gart(&(*bo)->tbo); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index c184468e2b2b..d71dc164b469 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -75,6 +75,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, } ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); + ctx->reset_counter_query = ctx->reset_counter; ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter); ctx->init_priority = priority; ctx->override_priority = AMD_SCHED_PRIORITY_UNSET; @@ -90,7 +91,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, continue; r = amd_sched_entity_init(&ring->sched, &ctx->rings[i].entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, &ctx->guilty); if (r) goto failed; } @@ -216,11 +217,45 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev, /* determine if a GPU reset has occured since the last call */ reset_counter = atomic_read(&adev->gpu_reset_counter); /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ - if (ctx->reset_counter == reset_counter) + if (ctx->reset_counter_query == reset_counter) out->state.reset_status = AMDGPU_CTX_NO_RESET; else out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; - ctx->reset_counter = reset_counter; + ctx->reset_counter_query = reset_counter; + + mutex_unlock(&mgr->lock); + return 0; +} + +static int amdgpu_ctx_query2(struct amdgpu_device *adev, + struct amdgpu_fpriv *fpriv, uint32_t id, + union drm_amdgpu_ctx_out *out) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr; + + if (!fpriv) + return -EINVAL; + + mgr = &fpriv->ctx_mgr; + mutex_lock(&mgr->lock); + ctx = idr_find(&mgr->ctx_handles, id); + if (!ctx) { + mutex_unlock(&mgr->lock); + return -EINVAL; + } + + out->state.flags = 0x0; + out->state.hangs = 0x0; + + if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; + + if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; + + if (atomic_read(&ctx->guilty)) + out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; mutex_unlock(&mgr->lock); return 0; @@ -257,6 +292,9 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, case AMDGPU_CTX_OP_QUERY_STATE: r = amdgpu_ctx_query(adev, fpriv, id, &args->out); break; + case AMDGPU_CTX_OP_QUERY_STATE2: + r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3573ecdb06ee..70c9e5756b02 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -410,6 +410,9 @@ static int amdgpu_doorbell_init(struct amdgpu_device *adev) return 0; } + if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET) + return -EINVAL; + /* doorbell bar mapping */ adev->doorbell.base = pci_resource_start(adev->pdev, 2); adev->doorbell.size = pci_resource_len(adev->pdev, 2); @@ -575,41 +578,13 @@ void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) * @base: base address at which to put VRAM * * Function will try to place VRAM at base address provided - * as parameter (which is so far either PCI aperture address or - * for IGP TOM base address). - * - * If there is not enough space to fit the unvisible VRAM in the 32bits - * address space then we limit the VRAM size to the aperture. - * - * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, - * this shouldn't be a problem as we are using the PCI aperture as a reference. - * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but - * not IGP. - * - * Note: we use mc_vram_size as on some board we need to program the mc to - * cover the whole aperture even if VRAM size is inferior to aperture size - * Novell bug 204882 + along with lots of ubuntu ones - * - * Note: when limiting vram it's safe to overwritte real_vram_size because - * we are not in case where real_vram_size is inferior to mc_vram_size (ie - * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu - * ones) - * - * Note: IGP TOM addr should be the same as the aperture addr, we don't - * explicitly check for that though. - * - * FIXME: when reducing VRAM size align new size on power of 2. + * as parameter. */ void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base) { uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; mc->vram_start = base; - if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) { - dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n"); - mc->real_vram_size = mc->aper_size; - mc->mc_vram_size = mc->aper_size; - } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; if (limit && limit < mc->real_vram_size) mc->real_vram_size = limit; @@ -647,7 +622,10 @@ void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc) dev_warn(adev->dev, "limiting GTT\n"); mc->gart_size = size_af; } - mc->gart_start = mc->vram_end + 1; + /* VCE doesn't like it when BOs cross a 4GB segment, so align + * the GART base on a 4GB boundary as well. + */ + mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL); } mc->gart_end = mc->gart_start + mc->gart_size - 1; dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", @@ -679,9 +657,13 @@ void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev) */ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) { + struct ttm_operation_ctx ctx = { false, false }; int r = 0; - u64 gpu_addr; + int i; u64 vram_size = adev->mc.visible_vram_size; + u64 offset = adev->fw_vram_usage.start_offset; + u64 size = adev->fw_vram_usage.size; + struct amdgpu_bo *bo; adev->fw_vram_usage.va = NULL; adev->fw_vram_usage.reserved_bo = NULL; @@ -690,7 +672,7 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) adev->fw_vram_usage.size <= vram_size) { r = amdgpu_bo_create(adev, adev->fw_vram_usage.size, - PAGE_SIZE, true, 0, + PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0, &adev->fw_vram_usage.reserved_bo); @@ -700,11 +682,28 @@ int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev) r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false); if (r) goto error_reserve; + + /* remove the original mem node and create a new one at the + * request position + */ + bo = adev->fw_vram_usage.reserved_bo; + offset = ALIGN(offset, PAGE_SIZE); + for (i = 0; i < bo->placement.num_placement; ++i) { + bo->placements[i].fpfn = offset >> PAGE_SHIFT; + bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; + } + + ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem); + r = ttm_bo_mem_space(&bo->tbo, &bo->placement, + &bo->tbo.mem, &ctx); + if (r) + goto error_pin; + r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo, AMDGPU_GEM_DOMAIN_VRAM, adev->fw_vram_usage.start_offset, (adev->fw_vram_usage.start_offset + - adev->fw_vram_usage.size), &gpu_addr); + adev->fw_vram_usage.size), NULL); if (r) goto error_pin; r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, @@ -728,6 +727,75 @@ error_create: return r; } +/** + * amdgpu_device_resize_fb_bar - try to resize FB BAR + * + * @adev: amdgpu_device pointer + * + * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not + * to fail, but if any of the BARs is not accessible after the size we abort + * driver loading by returning -ENODEV. + */ +int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) +{ + u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size); + u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; + struct pci_bus *root; + struct resource *res; + unsigned i; + u16 cmd; + int r; + + /* Bypass for VF */ + if (amdgpu_sriov_vf(adev)) + return 0; + + /* Check if the root BUS has 64bit memory resources */ + root = adev->pdev->bus; + while (root->parent) + root = root->parent; + + pci_bus_for_each_resource(root, res, i) { + if (res && res->flags & IORESOURCE_MEM_64 && + res->start > 0x100000000ull) + break; + } + + /* Trying to resize is pointless without a root hub window above 4GB */ + if (!res) + return 0; + + /* Disable memory decoding while we change the BAR addresses and size */ + pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd); + pci_write_config_word(adev->pdev, PCI_COMMAND, + cmd & ~PCI_COMMAND_MEMORY); + + /* Free the VRAM and doorbell BAR, we most likely need to move both. */ + amdgpu_doorbell_fini(adev); + if (adev->asic_type >= CHIP_BONAIRE) + pci_release_resource(adev->pdev, 2); + + pci_release_resource(adev->pdev, 0); + + r = pci_resize_resource(adev->pdev, 0, rbar_size); + if (r == -ENOSPC) + DRM_INFO("Not enough PCI address space for a large BAR."); + else if (r && r != -ENOTSUPP) + DRM_ERROR("Problem resizing BAR0 (%d).", r); + + pci_assign_unassigned_bus_resources(adev->pdev->bus); + + /* When the doorbell or fb BAR isn't available we have no chance of + * using the device. + */ + r = amdgpu_doorbell_init(adev); + if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET)) + return -ENODEV; + + pci_write_config_word(adev->pdev, PCI_COMMAND, cmd); + + return 0; +} /* * GPU helpers function. @@ -1029,7 +1097,7 @@ static int amdgpu_atombios_init(struct amdgpu_device *adev) atom_card_info->ioreg_read = cail_ioreg_read; atom_card_info->ioreg_write = cail_ioreg_write; } else { - DRM_INFO("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); + DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); atom_card_info->ioreg_read = cail_reg_read; atom_card_info->ioreg_write = cail_reg_write; } @@ -1094,20 +1162,8 @@ static void amdgpu_check_block_size(struct amdgpu_device *adev) if (amdgpu_vm_block_size < 9) { dev_warn(adev->dev, "VM page table size (%d) too small\n", amdgpu_vm_block_size); - goto def_value; + amdgpu_vm_block_size = -1; } - - if (amdgpu_vm_block_size > 24 || - (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { - dev_warn(adev->dev, "VM page table size (%d) too large\n", - amdgpu_vm_block_size); - goto def_value; - } - - return; - -def_value: - amdgpu_vm_block_size = -1; } static void amdgpu_check_vm_size(struct amdgpu_device *adev) @@ -1116,31 +1172,11 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) if (amdgpu_vm_size == -1) return; - if (!is_power_of_2(amdgpu_vm_size)) { - dev_warn(adev->dev, "VM size (%d) must be a power of 2\n", - amdgpu_vm_size); - goto def_value; - } - if (amdgpu_vm_size < 1) { dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", amdgpu_vm_size); - goto def_value; + amdgpu_vm_size = -1; } - - /* - * Max GPUVM size for Cayman, SI, CI VI are 40 bits. - */ - if (amdgpu_vm_size > 1024) { - dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n", - amdgpu_vm_size); - goto def_value; - } - - return; - -def_value: - amdgpu_vm_size = -1; } /** @@ -1622,10 +1658,12 @@ static int amdgpu_early_init(struct amdgpu_device *adev) if (r) return r; + amdgpu_amdkfd_device_probe(adev); + if (amdgpu_sriov_vf(adev)) { r = amdgpu_virt_request_full_gpu(adev, true); if (r) - return r; + return -EAGAIN; } for (i = 0; i < adev->num_ip_blocks; i++) { @@ -1716,6 +1754,11 @@ static int amdgpu_init(struct amdgpu_device *adev) adev->ip_blocks[i].status.hw = true; } + amdgpu_amdkfd_device_init(adev); + + if (amdgpu_sriov_vf(adev)) + amdgpu_virt_release_full_gpu(adev, true); + return 0; } @@ -1783,6 +1826,7 @@ static int amdgpu_fini(struct amdgpu_device *adev) { int i, r; + amdgpu_amdkfd_device_fini(adev); /* need to disable SMC first */ for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.hw) @@ -1811,6 +1855,7 @@ static int amdgpu_fini(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { + amdgpu_free_static_csa(adev); amdgpu_wb_fini(adev); amdgpu_vram_scratch_fini(adev); } @@ -1859,7 +1904,8 @@ static int amdgpu_fini(struct amdgpu_device *adev) } if (amdgpu_sriov_vf(adev)) - amdgpu_virt_release_full_gpu(adev, false); + if (amdgpu_virt_release_full_gpu(adev, false)) + DRM_ERROR("failed to release exclusive mode on fini\n"); return 0; } @@ -2163,6 +2209,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->mn_lock); mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); + mutex_init(&adev->lock_reset); amdgpu_check_arguments(adev); @@ -2179,9 +2226,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_LIST_HEAD(&adev->shadow_list); mutex_init(&adev->shadow_list_lock); - INIT_LIST_HEAD(&adev->gtt_list); - spin_lock_init(&adev->gtt_list_lock); - INIT_LIST_HEAD(&adev->ring_lru_list); spin_lock_init(&adev->ring_lru_list_lock); @@ -2267,8 +2311,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, dev_err(adev->dev, "gpu post error!\n"); goto failed; } - } else { - DRM_INFO("GPU post is not needed\n"); } if (adev->is_atom_fw) { @@ -2305,6 +2347,18 @@ int amdgpu_device_init(struct amdgpu_device *adev, r = amdgpu_init(adev); if (r) { + /* failed in exclusive mode due to timeout */ + if (amdgpu_sriov_vf(adev) && + !amdgpu_sriov_runtime(adev) && + amdgpu_virt_mmio_blocked(adev) && + !amdgpu_virt_wait_reset(adev)) { + dev_err(adev->dev, "VF exclusive mode timeout\n"); + /* Don't send request since VF is inactive. */ + adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; + adev->virt.ops = NULL; + r = -EAGAIN; + goto failed; + } dev_err(adev->dev, "amdgpu_init failed\n"); amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0); amdgpu_fini(adev); @@ -2392,6 +2446,7 @@ failed: amdgpu_vf_error_trans_all(adev); if (runtime) vga_switcheroo_fini_domain_pm_ops(adev->dev); + return r; } @@ -2414,7 +2469,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev) /* evict vram memory */ amdgpu_bo_evict_vram(adev); amdgpu_ib_pool_fini(adev); - amdgpu_fw_reserve_vram_fini(adev); amdgpu_fence_driver_fini(adev); amdgpu_fbdev_fini(adev); r = amdgpu_fini(adev); @@ -2819,163 +2873,172 @@ err: return r; } -/** - * amdgpu_sriov_gpu_reset - reset the asic +/* + * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough * * @adev: amdgpu device pointer - * @job: which job trigger hang + * @reset_flags: output param tells caller the reset result * - * Attempt the reset the GPU if it has hung (all asics). - * for SRIOV case. - * Returns 0 for success or an error on failure. - */ -int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job) + * attempt to do soft-reset or full-reset and reinitialize Asic + * return 0 means successed otherwise failed +*/ +static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags) { - int i, j, r = 0; - int resched; - struct amdgpu_bo *bo, *tmp; - struct amdgpu_ring *ring; - struct dma_fence *fence = NULL, *next = NULL; + bool need_full_reset, vram_lost = 0; + int r; - mutex_lock(&adev->virt.lock_reset); - atomic_inc(&adev->gpu_reset_counter); - adev->in_sriov_reset = true; + need_full_reset = amdgpu_need_full_reset(adev); - /* block TTM */ - resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); + if (!need_full_reset) { + amdgpu_pre_soft_reset(adev); + r = amdgpu_soft_reset(adev); + amdgpu_post_soft_reset(adev); + if (r || amdgpu_check_soft_reset(adev)) { + DRM_INFO("soft reset failed, will fallback to full reset!\n"); + need_full_reset = true; + } - /* we start from the ring trigger GPU hang */ - j = job ? job->ring->idx : 0; + } - /* block scheduler */ - for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { - ring = adev->rings[i % AMDGPU_MAX_RINGS]; - if (!ring || !ring->sched.thread) - continue; + if (need_full_reset) { + r = amdgpu_suspend(adev); - kthread_park(ring->sched.thread); +retry: + amdgpu_atombios_scratch_regs_save(adev); + r = amdgpu_asic_reset(adev); + amdgpu_atombios_scratch_regs_restore(adev); + /* post card */ + amdgpu_atom_asic_init(adev->mode_info.atom_context); - if (job && j != i) - continue; + if (!r) { + dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); + r = amdgpu_resume_phase1(adev); + if (r) + goto out; - /* here give the last chance to check if job removed from mirror-list - * since we already pay some time on kthread_park */ - if (job && list_empty(&job->base.node)) { - kthread_unpark(ring->sched.thread); - goto give_up_reset; + vram_lost = amdgpu_check_vram_lost(adev); + if (vram_lost) { + DRM_ERROR("VRAM is lost!\n"); + atomic_inc(&adev->vram_lost_counter); + } + + r = amdgpu_gtt_mgr_recover( + &adev->mman.bdev.man[TTM_PL_TT]); + if (r) + goto out; + + r = amdgpu_resume_phase2(adev); + if (r) + goto out; + + if (vram_lost) + amdgpu_fill_reset_magic(adev); } + } - if (amd_sched_invalidate_job(&job->base, amdgpu_job_hang_limit)) - amd_sched_job_kickout(&job->base); +out: + if (!r) { + amdgpu_irq_gpu_reset_resume_helper(adev); + r = amdgpu_ib_ring_tests(adev); + if (r) { + dev_err(adev->dev, "ib ring test failed (%d).\n", r); + r = amdgpu_suspend(adev); + need_full_reset = true; + goto retry; + } + } - /* only do job_reset on the hang ring if @job not NULL */ - amd_sched_hw_job_reset(&ring->sched); + if (reset_flags) { + if (vram_lost) + (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST; - /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion_ring(ring); + if (need_full_reset) + (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; } - /* request to take full control of GPU before re-initialization */ - if (job) - amdgpu_virt_reset_gpu(adev); - else - amdgpu_virt_request_full_gpu(adev, true); + return r; +} +/* + * amdgpu_reset_sriov - reset ASIC for SR-IOV vf + * + * @adev: amdgpu device pointer + * @reset_flags: output param tells caller the reset result + * + * do VF FLR and reinitialize Asic + * return 0 means successed otherwise failed +*/ +static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor) +{ + int r; + + if (from_hypervisor) + r = amdgpu_virt_request_full_gpu(adev, true); + else + r = amdgpu_virt_reset_gpu(adev); + if (r) + return r; /* Resume IP prior to SMC */ - amdgpu_sriov_reinit_early(adev); + r = amdgpu_sriov_reinit_early(adev); + if (r) + goto error; /* we need recover gart prior to run SMC/CP/SDMA resume */ - amdgpu_ttm_recover_gart(adev); + amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]); /* now we are okay to resume SMC/CP/SDMA */ - amdgpu_sriov_reinit_late(adev); + r = amdgpu_sriov_reinit_late(adev); + if (r) + goto error; amdgpu_irq_gpu_reset_resume_helper(adev); - - if (amdgpu_ib_ring_tests(adev)) + r = amdgpu_ib_ring_tests(adev); + if (r) dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r); +error: /* release full control of GPU after ib test */ amdgpu_virt_release_full_gpu(adev, true); - DRM_INFO("recover vram bo from shadow\n"); - - ring = adev->mman.buffer_funcs_ring; - mutex_lock(&adev->shadow_list_lock); - list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) { - next = NULL; - amdgpu_recover_vram_from_shadow(adev, ring, bo, &next); - if (fence) { - r = dma_fence_wait(fence, false); - if (r) { - WARN(r, "recovery from shadow isn't completed\n"); - break; - } - } - - dma_fence_put(fence); - fence = next; - } - mutex_unlock(&adev->shadow_list_lock); - - if (fence) { - r = dma_fence_wait(fence, false); - if (r) - WARN(r, "recovery from shadow isn't completed\n"); - } - dma_fence_put(fence); - - for (i = j; i < j + AMDGPU_MAX_RINGS; ++i) { - ring = adev->rings[i % AMDGPU_MAX_RINGS]; - if (!ring || !ring->sched.thread) - continue; - - if (job && j != i) { - kthread_unpark(ring->sched.thread); - continue; + if (reset_flags) { + if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { + (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST; + atomic_inc(&adev->vram_lost_counter); } - amd_sched_job_recovery(&ring->sched); - kthread_unpark(ring->sched.thread); - } - - drm_helper_resume_force_mode(adev->ddev); -give_up_reset: - ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); - if (r) { - /* bad news, how to tell it to userspace ? */ - dev_info(adev->dev, "GPU reset failed\n"); - } else { - dev_info(adev->dev, "GPU reset successed!\n"); + /* VF FLR or hotlink reset is always full-reset */ + (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET; } - adev->in_sriov_reset = false; - mutex_unlock(&adev->virt.lock_reset); return r; } /** - * amdgpu_gpu_reset - reset the asic + * amdgpu_gpu_recover - reset the asic and recover scheduler * * @adev: amdgpu device pointer + * @job: which job trigger hang * - * Attempt the reset the GPU if it has hung (all asics). + * Attempt to reset the GPU if it has hung (all asics). * Returns 0 for success or an error on failure. */ -int amdgpu_gpu_reset(struct amdgpu_device *adev) +int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job) { struct drm_atomic_state *state = NULL; - int i, r; - int resched; - bool need_full_reset, vram_lost = false; + uint64_t reset_flags = 0; + int i, r, resched; if (!amdgpu_check_soft_reset(adev)) { DRM_INFO("No hardware hang detected. Did some blocks stall?\n"); return 0; } + dev_info(adev->dev, "GPU reset begin!\n"); + + mutex_lock(&adev->lock_reset); atomic_inc(&adev->gpu_reset_counter); + adev->in_gpu_reset = 1; /* block TTM */ resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); @@ -2989,69 +3052,26 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) if (!ring || !ring->sched.thread) continue; - kthread_park(ring->sched.thread); - amd_sched_hw_job_reset(&ring->sched); - } - /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion(adev); - need_full_reset = amdgpu_need_full_reset(adev); + /* only focus on the ring hit timeout if &job not NULL */ + if (job && job->ring->idx != i) + continue; - if (!need_full_reset) { - amdgpu_pre_soft_reset(adev); - r = amdgpu_soft_reset(adev); - amdgpu_post_soft_reset(adev); - if (r || amdgpu_check_soft_reset(adev)) { - DRM_INFO("soft reset failed, will fallback to full reset!\n"); - need_full_reset = true; - } - } + kthread_park(ring->sched.thread); + amd_sched_hw_job_reset(&ring->sched, &job->base); - if (need_full_reset) { - r = amdgpu_suspend(adev); + /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ + amdgpu_fence_driver_force_completion(ring); + } -retry: - amdgpu_atombios_scratch_regs_save(adev); - r = amdgpu_asic_reset(adev); - amdgpu_atombios_scratch_regs_restore(adev); - /* post card */ - amdgpu_atom_asic_init(adev->mode_info.atom_context); + if (amdgpu_sriov_vf(adev)) + r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true); + else + r = amdgpu_reset(adev, &reset_flags); - if (!r) { - dev_info(adev->dev, "GPU reset succeeded, trying to resume\n"); - r = amdgpu_resume_phase1(adev); - if (r) - goto out; - vram_lost = amdgpu_check_vram_lost(adev); - if (vram_lost) { - DRM_ERROR("VRAM is lost!\n"); - atomic_inc(&adev->vram_lost_counter); - } - r = amdgpu_ttm_recover_gart(adev); - if (r) - goto out; - r = amdgpu_resume_phase2(adev); - if (r) - goto out; - if (vram_lost) - amdgpu_fill_reset_magic(adev); - } - } -out: if (!r) { - amdgpu_irq_gpu_reset_resume_helper(adev); - r = amdgpu_ib_ring_tests(adev); - if (r) { - dev_err(adev->dev, "ib ring test failed (%d).\n", r); - r = amdgpu_suspend(adev); - need_full_reset = true; - goto retry; - } - /** - * recovery vm page tables, since we cannot depend on VRAM is - * consistent after gpu full reset. - */ - if (need_full_reset && amdgpu_need_backup(adev)) { + if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) || + (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) { struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct amdgpu_bo *bo, *tmp; struct dma_fence *fence = NULL, *next = NULL; @@ -3080,40 +3100,56 @@ out: } dma_fence_put(fence); } + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; if (!ring || !ring->sched.thread) continue; + /* only focus on the ring hit timeout if &job not NULL */ + if (job && job->ring->idx != i) + continue; + amd_sched_job_recovery(&ring->sched); kthread_unpark(ring->sched.thread); } } else { - dev_err(adev->dev, "asic resume failed (%d).\n", r); for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - if (adev->rings[i] && adev->rings[i]->sched.thread) { - kthread_unpark(adev->rings[i]->sched.thread); - } + struct amdgpu_ring *ring = adev->rings[i]; + + if (!ring || !ring->sched.thread) + continue; + + /* only focus on the ring hit timeout if &job not NULL */ + if (job && job->ring->idx != i) + continue; + + kthread_unpark(adev->rings[i]->sched.thread); } } if (amdgpu_device_has_dc_support(adev)) { - r = drm_atomic_helper_resume(adev->ddev, state); + if (drm_atomic_helper_resume(adev->ddev, state)) + dev_info(adev->dev, "drm resume failed:%d\n", r); amdgpu_dm_display_resume(adev); - } else + } else { drm_helper_resume_force_mode(adev->ddev); + } ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); + if (r) { /* bad news, how to tell it to userspace ? */ - dev_info(adev->dev, "GPU reset failed\n"); - } - else { - dev_info(adev->dev, "GPU reset successed!\n"); + dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter)); + amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r); + } else { + dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter)); } amdgpu_vf_error_trans_all(adev); + adev->in_gpu_reset = 0; + mutex_unlock(&adev->lock_reset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 138beb550a58..38d47559f098 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -34,6 +34,7 @@ #include <linux/pm_runtime.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_edid.h> +#include <drm/drm_fb_helper.h> static void amdgpu_flip_callback(struct dma_fence *f, struct dma_fence_cb *cb) { @@ -556,15 +557,9 @@ amdgpu_user_framebuffer_create(struct drm_device *dev, return &amdgpu_fb->base; } -void amdgpu_output_poll_changed(struct drm_device *dev) -{ - struct amdgpu_device *adev = dev->dev_private; - amdgpu_fb_output_poll_changed(adev); -} - const struct drm_mode_config_funcs amdgpu_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, - .output_poll_changed = amdgpu_output_poll_changed + .output_poll_changed = drm_fb_helper_output_poll_changed, }; static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 3cc0ef0c055e..0bcb6c6e0ca9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -25,9 +25,7 @@ struct drm_framebuffer * amdgpu_user_framebuffer_create(struct drm_device *dev, - struct drm_file *file_priv, - const struct drm_mode_fb_cmd2 *mode_cmd); - -void amdgpu_output_poll_changed(struct drm_device *dev); + struct drm_file *file_priv, + const struct drm_mode_fb_cmd2 *mode_cmd); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index 56caaeee6fea..a8437a3296a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -360,6 +360,12 @@ enum amdgpu_pcie_gen { ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ (adev)->powerplay.pp_handle, msg_id)) +#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \ + virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \ + ((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \ + (adev)->powerplay.pp_handle, virtual_addr_low, \ + virtual_addr_hi, mc_addr_low, mc_addr_hi, size) + struct amdgpu_dpm { struct amdgpu_ps *ps; /* number of valid power states */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c2f414ffb2cc..31383e004947 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -216,7 +216,7 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); module_param_named(dc, amdgpu_dc, int, 0444); -MODULE_PARM_DESC(dc, "Display Core Log Level (0 = minimal (default), 1 = chatty"); +MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty"); module_param_named(dc_log, amdgpu_dc_log, int, 0444); MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); @@ -306,7 +306,6 @@ MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled) module_param_named(cik_support, amdgpu_cik_support, int, 0444); #endif - static const struct pci_device_id pciidlist[] = { #ifdef CONFIG_DRM_AMDGPU_SI {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, @@ -566,12 +565,13 @@ static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) return 0; } + static int amdgpu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct drm_device *dev; unsigned long flags = ent->driver_data; - int ret; + int ret, retry = 0; if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { DRM_INFO("This hardware requires experimental hardware support.\n" @@ -604,8 +604,14 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, pci_set_drvdata(pdev, dev); +retry_init: ret = drm_dev_register(dev, ent->driver_data); - if (ret) + if (ret == -EAGAIN && ++retry <= 3) { + DRM_INFO("retry init %d\n", retry); + /* Don't request EX mode too frequently which is attacking */ + msleep(5000); + goto retry_init; + } else if (ret) goto err_pci; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 90fa8e8bc6fb..ff3e9beb7d19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -283,12 +283,6 @@ out: return ret; } -void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev) -{ - if (adev->mode_info.rfbdev) - drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper); -} - static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) { struct amdgpu_framebuffer *rfb = &rfbdev->rfb; @@ -393,24 +387,3 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; return false; } - -void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev) -{ - struct amdgpu_fbdev *afbdev; - struct drm_fb_helper *fb_helper; - int ret; - - if (!adev) - return; - - afbdev = adev->mode_info.rfbdev; - - if (!afbdev) - return; - - fb_helper = &afbdev->helper; - - ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); - if (ret) - DRM_DEBUG("failed to restore crtc mode\n"); -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 2fa95aef74d5..604ac03a42e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -391,9 +391,9 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, ring->fence_drv.irq_type = irq_type; ring->fence_drv.initialized = true; - dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " - "cpu addr 0x%p\n", ring->idx, - ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); + dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, " + "cpu addr 0x%p\n", ring->idx, + ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); return 0; } @@ -446,7 +446,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, timeout = MAX_SCHEDULE_TIMEOUT; } r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, - num_hw_submission, + num_hw_submission, amdgpu_job_hang_limit, timeout, ring->name); if (r) { DRM_ERROR("Failed to create scheduler on ring %s.\n", @@ -499,7 +499,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) r = amdgpu_fence_wait_empty(ring); if (r) { /* no need to trigger GPU reset as we are unloading */ - amdgpu_fence_driver_force_completion(adev); + amdgpu_fence_driver_force_completion(ring); } amdgpu_irq_put(adev, ring->fence_drv.irq_src, ring->fence_drv.irq_type); @@ -534,7 +534,7 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev) r = amdgpu_fence_wait_empty(ring); if (r) { /* delay GPU reset to resume */ - amdgpu_fence_driver_force_completion(adev); + amdgpu_fence_driver_force_completion(ring); } /* disable the interrupt */ @@ -571,30 +571,15 @@ void amdgpu_fence_driver_resume(struct amdgpu_device *adev) } /** - * amdgpu_fence_driver_force_completion - force all fence waiter to complete + * amdgpu_fence_driver_force_completion - force signal latest fence of ring * - * @adev: amdgpu device pointer + * @ring: fence of the ring to signal * - * In case of GPU reset failure make sure no process keep waiting on fence - * that will never complete. */ -void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) { - int i; - - for (i = 0; i < AMDGPU_MAX_RINGS; i++) { - struct amdgpu_ring *ring = adev->rings[i]; - if (!ring || !ring->fence_drv.initialized) - continue; - - amdgpu_fence_write(ring, ring->fence_drv.sync_seq); - } -} - -void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring) -{ - if (ring) - amdgpu_fence_write(ring, ring->fence_drv.sync_seq); + amdgpu_fence_write(ring, ring->fence_drv.sync_seq); + amdgpu_fence_process(ring); } /* @@ -709,25 +694,25 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) } /** - * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset + * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover * * Manually trigger a gpu reset at the next fence wait. */ -static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data) +static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; - seq_printf(m, "gpu reset\n"); - amdgpu_gpu_reset(adev); + seq_printf(m, "gpu recover\n"); + amdgpu_gpu_recover(adev, NULL); return 0; } static const struct drm_info_list amdgpu_debugfs_fence_list[] = { {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL}, - {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL} + {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL} }; static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index fe818501c520..1f51897acc5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -57,63 +57,6 @@ */ /** - * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table - * - * @adev: amdgpu_device pointer - * - * Allocate system memory for GART page table - * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the - * gart table to be in system memory. - * Returns 0 for success, -ENOMEM for failure. - */ -int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev) -{ - void *ptr; - - ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size, - &adev->gart.table_addr); - if (ptr == NULL) { - return -ENOMEM; - } -#ifdef CONFIG_X86 - if (0) { - set_memory_uc((unsigned long)ptr, - adev->gart.table_size >> PAGE_SHIFT); - } -#endif - adev->gart.ptr = ptr; - memset((void *)adev->gart.ptr, 0, adev->gart.table_size); - return 0; -} - -/** - * amdgpu_gart_table_ram_free - free system ram for gart page table - * - * @adev: amdgpu_device pointer - * - * Free system memory for GART page table - * (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the - * gart table to be in system memory. - */ -void amdgpu_gart_table_ram_free(struct amdgpu_device *adev) -{ - if (adev->gart.ptr == NULL) { - return; - } -#ifdef CONFIG_X86 - if (0) { - set_memory_wb((unsigned long)adev->gart.ptr, - adev->gart.table_size >> PAGE_SHIFT); - } -#endif - pci_free_consistent(adev->pdev, adev->gart.table_size, - (void *)adev->gart.ptr, - adev->gart.table_addr); - adev->gart.ptr = NULL; - adev->gart.table_addr = 0; -} - -/** * amdgpu_gart_table_vram_alloc - allocate vram for gart page table * * @adev: amdgpu_device pointer @@ -377,10 +320,8 @@ int amdgpu_gart_init(struct amdgpu_device *adev) #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS /* Allocate pages table */ adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages); - if (adev->gart.pages == NULL) { - amdgpu_gart_fini(adev); + if (adev->gart.pages == NULL) return -ENOMEM; - } #endif return 0; @@ -395,11 +336,6 @@ int amdgpu_gart_init(struct amdgpu_device *adev) */ void amdgpu_gart_fini(struct amdgpu_device *adev) { - if (adev->gart.ready) { - /* unbind pages */ - amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages); - } - adev->gart.ready = false; #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS vfree(adev->gart.pages); adev->gart.pages = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index afbe803b1a13..d4a43302c2be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -39,7 +39,7 @@ struct amdgpu_gart_funcs; #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) struct amdgpu_gart { - dma_addr_t table_addr; + u64 table_addr; struct amdgpu_bo *robj; void *ptr; unsigned num_gpu_pages; @@ -56,8 +56,6 @@ struct amdgpu_gart { const struct amdgpu_gart_funcs *gart_funcs; }; -int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); -void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index e87eedcc0da9..eb75eb44efc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -72,7 +72,7 @@ retry: initial_domain |= AMDGPU_GEM_DOMAIN_GTT; goto retry; } - DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", + DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", size, initial_domain, alignment, r); } return r; @@ -282,6 +282,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct ttm_operation_ctx ctx = { true, false }; struct amdgpu_device *adev = dev->dev_private; struct drm_amdgpu_gem_userptr *args = data; struct drm_gem_object *gobj; @@ -335,7 +336,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto free_pages; amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); amdgpu_bo_unreserve(bo); if (r) goto free_pages; @@ -557,14 +558,25 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, int r = 0; if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { - dev_err(&dev->pdev->dev, + dev_dbg(&dev->pdev->dev, "va_address 0x%LX is in reserved area 0x%LX\n", args->va_address, AMDGPU_VA_RESERVED_SIZE); return -EINVAL; } + if (args->va_address >= AMDGPU_VA_HOLE_START && + args->va_address < AMDGPU_VA_HOLE_END) { + dev_dbg(&dev->pdev->dev, + "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", + args->va_address, AMDGPU_VA_HOLE_START, + AMDGPU_VA_HOLE_END); + return -EINVAL; + } + + args->va_address &= AMDGPU_VA_HOLE_MASK; + if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { - dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n", + dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", args->flags); return -EINVAL; } @@ -576,7 +588,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, case AMDGPU_VA_OP_REPLACE: break; default: - dev_err(&dev->pdev->dev, "unsupported operation %d\n", + dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", args->operation); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 00e0ce10862f..e14ab34d8262 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -31,6 +31,11 @@ struct amdgpu_gtt_mgr { atomic64_t available; }; +struct amdgpu_gtt_node { + struct drm_mm_node node; + struct ttm_buffer_object *tbo; +}; + /** * amdgpu_gtt_mgr_init - init GTT manager and DRM MM * @@ -79,17 +84,17 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) } /** - * amdgpu_gtt_mgr_is_allocated - Check if mem has address space + * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space * * @mem: the mem object to check * * Check if a mem object has already address space allocated. */ -bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem) +bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem) { - struct drm_mm_node *node = mem->mm_node; + struct amdgpu_gtt_node *node = mem->mm_node; - return (node->start != AMDGPU_BO_INVALID_OFFSET); + return (node->node.start != AMDGPU_BO_INVALID_OFFSET); } /** @@ -109,12 +114,12 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, { struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev); struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_mm_node *node = mem->mm_node; + struct amdgpu_gtt_node *node = mem->mm_node; enum drm_mm_insert_mode mode; unsigned long fpfn, lpfn; int r; - if (amdgpu_gtt_mgr_is_allocated(mem)) + if (amdgpu_gtt_mgr_has_gart_addr(mem)) return 0; if (place) @@ -132,13 +137,13 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man, mode = DRM_MM_INSERT_HIGH; spin_lock(&mgr->lock); - r = drm_mm_insert_node_in_range(&mgr->mm, node, - mem->num_pages, mem->page_alignment, 0, - fpfn, lpfn, mode); + r = drm_mm_insert_node_in_range(&mgr->mm, &node->node, mem->num_pages, + mem->page_alignment, 0, fpfn, lpfn, + mode); spin_unlock(&mgr->lock); if (!r) - mem->start = node->start; + mem->start = node->node.start; return r; } @@ -159,7 +164,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_mm_node *node; + struct amdgpu_gtt_node *node; int r; spin_lock(&mgr->lock); @@ -177,8 +182,9 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, goto err_out; } - node->start = AMDGPU_BO_INVALID_OFFSET; - node->size = mem->num_pages; + node->node.start = AMDGPU_BO_INVALID_OFFSET; + node->node.size = mem->num_pages; + node->tbo = tbo; mem->mm_node = node; if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) { @@ -190,7 +196,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man, goto err_out; } } else { - mem->start = node->start; + mem->start = node->node.start; } return 0; @@ -214,14 +220,14 @@ static void amdgpu_gtt_mgr_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct amdgpu_gtt_mgr *mgr = man->priv; - struct drm_mm_node *node = mem->mm_node; + struct amdgpu_gtt_node *node = mem->mm_node; if (!node) return; spin_lock(&mgr->lock); - if (node->start != AMDGPU_BO_INVALID_OFFSET) - drm_mm_remove_node(node); + if (node->node.start != AMDGPU_BO_INVALID_OFFSET) + drm_mm_remove_node(&node->node); spin_unlock(&mgr->lock); atomic64_add(mem->num_pages, &mgr->available); @@ -244,6 +250,25 @@ uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man) return (result > 0 ? result : 0) * PAGE_SIZE; } +int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man) +{ + struct amdgpu_gtt_mgr *mgr = man->priv; + struct amdgpu_gtt_node *node; + struct drm_mm_node *mm_node; + int r = 0; + + spin_lock(&mgr->lock); + drm_mm_for_each_node(mm_node, &mgr->mm) { + node = container_of(mm_node, struct amdgpu_gtt_node, node); + r = amdgpu_ttm_recover_gart(node->tbo); + if (r) + break; + } + spin_unlock(&mgr->lock); + + return r; +} + /** * amdgpu_gtt_mgr_debug - dump VRAM table * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 659997bfff30..0cf86eb357d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -164,7 +164,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, } if (ring->funcs->emit_pipeline_sync && job && - ((tmp = amdgpu_sync_get_fence(&job->sched_sync)) || + ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || amdgpu_vm_need_pipeline_sync(ring, job))) { need_pipe_sync = true; dma_fence_put(tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 47c5ce9807db..c340774082ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -88,7 +88,7 @@ static void amdgpu_irq_reset_work_func(struct work_struct *work) reset_work); if (!amdgpu_sriov_vf(adev)) - amdgpu_gpu_reset(adev); + amdgpu_gpu_recover(adev, NULL); } /* Disable *all* interrupts */ @@ -232,7 +232,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) int ret = pci_enable_msi(adev->pdev); if (!ret) { adev->irq.msi_enabled = true; - dev_info(adev->dev, "amdgpu: using MSI.\n"); + dev_dbg(adev->dev, "amdgpu: using MSI.\n"); } } @@ -262,7 +262,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) return r; } - DRM_INFO("amdgpu: irq initialized.\n"); + DRM_DEBUG("amdgpu: irq initialized.\n"); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 0cfc68db575b..bdc210ac74f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -37,10 +37,7 @@ static void amdgpu_job_timedout(struct amd_sched_job *s_job) atomic_read(&job->ring->fence_drv.last_seq), job->ring->fence_drv.sync_seq); - if (amdgpu_sriov_vf(job->adev)) - amdgpu_sriov_gpu_reset(job->adev, job); - else - amdgpu_gpu_reset(job->adev); + amdgpu_gpu_recover(job->adev, job); } int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, @@ -63,7 +60,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, (*job)->num_ibs = num_ibs; amdgpu_sync_create(&(*job)->sync); - amdgpu_sync_create(&(*job)->dep_sync); amdgpu_sync_create(&(*job)->sched_sync); (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter); @@ -104,10 +100,9 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job) { struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base); - amdgpu_ring_priority_put(job->ring, amd_sched_get_job_priority(s_job)); + amdgpu_ring_priority_put(job->ring, s_job->s_priority); dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); - amdgpu_sync_free(&job->dep_sync); amdgpu_sync_free(&job->sched_sync); kfree(job); } @@ -118,7 +113,6 @@ void amdgpu_job_free(struct amdgpu_job *job) dma_fence_put(job->fence); amdgpu_sync_free(&job->sync); - amdgpu_sync_free(&job->dep_sync); amdgpu_sync_free(&job->sched_sync); kfree(job); } @@ -141,28 +135,29 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, job->fence_ctx = entity->fence_context; *f = dma_fence_get(&job->base.s_fence->finished); amdgpu_job_free_resources(job); - amdgpu_ring_priority_get(job->ring, - amd_sched_get_job_priority(&job->base)); - amd_sched_entity_push_job(&job->base); + amdgpu_ring_priority_get(job->ring, job->base.s_priority); + amd_sched_entity_push_job(&job->base, entity); return 0; } -static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) +static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job, + struct amd_sched_entity *s_entity) { struct amdgpu_job *job = to_amdgpu_job(sched_job); struct amdgpu_vm *vm = job->vm; - - struct dma_fence *fence = amdgpu_sync_get_fence(&job->dep_sync); + bool explicit = false; int r; - - if (amd_sched_dependency_optimized(fence, sched_job->s_entity)) { - r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence); - if (r) - DRM_ERROR("Error adding fence to sync (%d)\n", r); + struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit); + + if (fence && explicit) { + if (amd_sched_dependency_optimized(fence, s_entity)) { + r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false); + if (r) + DRM_ERROR("Error adding fence to sync (%d)\n", r); + } } - if (!fence) - fence = amdgpu_sync_get_fence(&job->sync); + while (fence == NULL && vm && !job->vm_id) { struct amdgpu_ring *ring = job->ring; @@ -172,7 +167,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) if (r) DRM_ERROR("Error getting VM ID (%d)\n", r); - fence = amdgpu_sync_get_fence(&job->sync); + fence = amdgpu_sync_get_fence(&job->sync, NULL); } return fence; @@ -180,7 +175,7 @@ static struct dma_fence *amdgpu_job_dependency(struct amd_sched_job *sched_job) static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) { - struct dma_fence *fence = NULL; + struct dma_fence *fence = NULL, *finished; struct amdgpu_device *adev; struct amdgpu_job *job; int r; @@ -190,15 +185,18 @@ static struct dma_fence *amdgpu_job_run(struct amd_sched_job *sched_job) return NULL; } job = to_amdgpu_job(sched_job); + finished = &job->base.s_fence->finished; adev = job->adev; BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL)); trace_amdgpu_sched_run_job(job); - /* skip ib schedule when vram is lost */ - if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) { - dma_fence_set_error(&job->base.s_fence->finished, -ECANCELED); - DRM_ERROR("Skip scheduling IBs!\n"); + + if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) + dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ + + if (finished->error < 0) { + DRM_INFO("Skip scheduling IBs!\n"); } else { r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job, &fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 720139e182a3..bd6e9a40f421 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -63,8 +63,6 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) pm_runtime_forbid(dev->dev); } - amdgpu_amdkfd_device_fini(adev); - amdgpu_acpi_fini(adev); amdgpu_device_fini(adev); @@ -159,9 +157,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) "Error during ACPI methods call\n"); } - amdgpu_amdkfd_device_probe(adev); - amdgpu_amdkfd_device_init(adev); - if (amdgpu_device_is_px(dev)) { pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); @@ -171,9 +166,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) pm_runtime_put_autosuspend(dev->dev); } - if (amdgpu_sriov_vf(adev)) - amdgpu_virt_release_full_gpu(adev, true); - out: if (r) { /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ @@ -558,6 +550,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file } case AMDGPU_INFO_DEV_INFO: { struct drm_amdgpu_info_device dev_info = {}; + uint64_t vm_size; dev_info.device_id = dev->pdev->device; dev_info.chip_rev = adev->rev_id; @@ -585,8 +578,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; if (amdgpu_sriov_vf(adev)) dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; + + vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; - dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; + dev_info.virtual_address_max = + min(vm_size, AMDGPU_VA_HOLE_START); + + vm_size -= AMDGPU_VA_RESERVED_SIZE; + if (vm_size > AMDGPU_VA_HOLE_START) { + dev_info.high_va_offset = AMDGPU_VA_HOLE_END; + dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size; + } dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; @@ -786,9 +788,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file */ void amdgpu_driver_lastclose_kms(struct drm_device *dev) { - struct amdgpu_device *adev = dev->dev_private; - - amdgpu_fbdev_restore_mode(adev); + drm_fb_helper_lastclose(dev); vga_switcheroo_process_delayed_switch(); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index ffde1e9666e8..54f06c959340 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -89,7 +89,6 @@ enum amdgpu_hpd_id { AMDGPU_HPD_4, AMDGPU_HPD_5, AMDGPU_HPD_6, - AMDGPU_HPD_LAST, AMDGPU_HPD_NONE = 0xff, }; @@ -106,7 +105,6 @@ enum amdgpu_crtc_irq { AMDGPU_CRTC_IRQ_VLINE4, AMDGPU_CRTC_IRQ_VLINE5, AMDGPU_CRTC_IRQ_VLINE6, - AMDGPU_CRTC_IRQ_LAST, AMDGPU_CRTC_IRQ_NONE = 0xff }; @@ -117,7 +115,6 @@ enum amdgpu_pageflip_irq { AMDGPU_PAGEFLIP_IRQ_D4, AMDGPU_PAGEFLIP_IRQ_D5, AMDGPU_PAGEFLIP_IRQ_D6, - AMDGPU_PAGEFLIP_IRQ_LAST, AMDGPU_PAGEFLIP_IRQ_NONE = 0xff }; @@ -661,10 +658,6 @@ void amdgpu_fbdev_fini(struct amdgpu_device *adev); void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); int amdgpu_fbdev_total_size(struct amdgpu_device *adev); bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); -void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); - -void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); - int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index ea25164e7f4b..dc0a8be98043 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -281,6 +281,44 @@ void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, *cpu_addr = NULL; } +/* Validate bo size is bit bigger then the request domain */ +static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, + unsigned long size, u32 domain) +{ + struct ttm_mem_type_manager *man = NULL; + + /* + * If GTT is part of requested domains the check must succeed to + * allow fall back to GTT + */ + if (domain & AMDGPU_GEM_DOMAIN_GTT) { + man = &adev->mman.bdev.man[TTM_PL_TT]; + + if (size < (man->size << PAGE_SHIFT)) + return true; + else + goto fail; + } + + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { + man = &adev->mman.bdev.man[TTM_PL_VRAM]; + + if (size < (man->size << PAGE_SHIFT)) + return true; + else + goto fail; + } + + + /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ + return true; + +fail: + DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, + man->size << PAGE_SHIFT); + return false; +} + static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size, int byte_align, bool kernel, u32 domain, u64 flags, @@ -289,16 +327,19 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, uint64_t init_value, struct amdgpu_bo **bo_ptr) { + struct ttm_operation_ctx ctx = { !kernel, false }; struct amdgpu_bo *bo; enum ttm_bo_type type; unsigned long page_align; - u64 initial_bytes_moved, bytes_moved; size_t acc_size; int r; page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; size = ALIGN(size, PAGE_SIZE); + if (!amdgpu_bo_validate_size(adev, size, domain)) + return -ENOMEM; + if (kernel) { type = ttm_bo_type_kernel; } else if (sg) { @@ -364,22 +405,19 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, bo->tbo.bdev = &adev->mman.bdev; amdgpu_ttm_placement_from_domain(bo, domain); - initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); - /* Kernel allocation are uninterruptible */ r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type, - &bo->placement, page_align, !kernel, NULL, + &bo->placement, page_align, &ctx, NULL, acc_size, sg, resv, &amdgpu_ttm_bo_destroy); if (unlikely(r != 0)) return r; - bytes_moved = atomic64_read(&adev->num_bytes_moved) - - initial_bytes_moved; if (adev->mc.visible_vram_size < adev->mc.real_vram_size && bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) - amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved); + amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, + ctx.bytes_moved); else - amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0); + amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); if (kernel) bo->tbo.priority = 1; @@ -511,6 +549,7 @@ err: int amdgpu_bo_validate(struct amdgpu_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; uint32_t domain; int r; @@ -521,7 +560,7 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo) retry: amdgpu_ttm_placement_from_domain(bo, domain); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { domain = bo->allowed_domains; goto retry; @@ -632,6 +671,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) @@ -647,7 +687,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, if (bo->pin_count) { uint32_t mem_type = bo->tbo.mem.mem_type; - if (domain != amdgpu_mem_type_to_domain(mem_type)) + if (!(domain & amdgpu_mem_type_to_domain(mem_type))) return -EINVAL; bo->pin_count++; @@ -682,21 +722,23 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r)) { dev_err(adev->dev, "%p pin failed\n", bo); goto error; } + r = amdgpu_ttm_alloc_gart(&bo->tbo); + if (unlikely(r)) { + dev_err(adev->dev, "%p bind failed\n", bo); + goto error; + } + bo->pin_count = 1; - if (gpu_addr != NULL) { - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); - if (unlikely(r)) { - dev_err(adev->dev, "%p bind failed\n", bo); - goto error; - } + if (gpu_addr != NULL) *gpu_addr = amdgpu_bo_gpu_offset(bo); - } + + domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); if (domain == AMDGPU_GEM_DOMAIN_VRAM) { adev->vram_pin_size += amdgpu_bo_size(bo); if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) @@ -717,6 +759,7 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) int amdgpu_bo_unpin(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (!bo->pin_count) { @@ -730,7 +773,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) bo->placements[i].lpfn = 0; bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r)) { dev_err(adev->dev, "%p validate failed for unpin\n", bo); goto error; @@ -779,8 +822,8 @@ int amdgpu_bo_init(struct amdgpu_device *adev) adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, adev->mc.aper_size); DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", - adev->mc.mc_vram_size >> 20, - (unsigned long long)adev->mc.aper_size >> 20); + adev->mc.mc_vram_size >> 20, + (unsigned long long)adev->mc.aper_size >> 20); DRM_INFO("RAM width %dbits %s\n", adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); return amdgpu_ttm_init(adev); @@ -902,6 +945,7 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); + struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_bo *abo; unsigned long offset, size; int r; @@ -935,7 +979,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) abo->placement.num_busy_placement = 1; abo->placement.busy_placement = &abo->placements[1]; - r = ttm_bo_validate(bo, &abo->placement, false, false); + r = ttm_bo_validate(bo, &abo->placement, &ctx); if (unlikely(r != 0)) return r; @@ -980,7 +1024,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT && - !amdgpu_ttm_is_bound(bo->tbo.ttm)); + !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem)); WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) && !bo->pin_count); WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 428aae048f4b..33615e2ea2e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -187,7 +187,7 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo) { switch (bo->tbo.mem.mem_type) { - case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm); + case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem); case TTM_PL_VRAM: return true; default: return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6c570d4e4516..6f56ff606e43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -30,7 +30,6 @@ #include <linux/hwmon.h> #include <linux/hwmon-sysfs.h> -#include "amd_powerplay.h" static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 447d446b5015..2157d4509e84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -264,7 +264,7 @@ static int psp_hw_start(struct psp_context *psp) struct amdgpu_device *adev = psp->adev; int ret; - if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { + if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) { ret = psp_bootloader_load_sysdrv(psp); if (ret) return ret; @@ -334,23 +334,26 @@ static int psp_load_fw(struct amdgpu_device *adev) int ret; struct psp_context *psp = &adev->psp; + if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0) + goto skip_memalloc; + psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); if (!psp->cmd) return -ENOMEM; ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, - AMDGPU_GEM_DOMAIN_GTT, - &psp->fw_pri_bo, - &psp->fw_pri_mc_addr, - &psp->fw_pri_buf); + AMDGPU_GEM_DOMAIN_GTT, + &psp->fw_pri_bo, + &psp->fw_pri_mc_addr, + &psp->fw_pri_buf); if (ret) goto failed; ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, - AMDGPU_GEM_DOMAIN_VRAM, - &psp->fence_buf_bo, - &psp->fence_buf_mc_addr, - &psp->fence_buf); + AMDGPU_GEM_DOMAIN_VRAM, + &psp->fence_buf_bo, + &psp->fence_buf_mc_addr, + &psp->fence_buf); if (ret) goto failed_mem2; @@ -375,6 +378,7 @@ static int psp_load_fw(struct amdgpu_device *adev) if (ret) goto failed_mem; +skip_memalloc: ret = psp_hw_start(psp); if (ret) goto failed_mem; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c index 93d86619e802..262c1267249e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c @@ -225,7 +225,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, /* Right now all IPs have only one instance - multiple rings. */ if (instance != 0) { - DRM_ERROR("invalid ip instance: %d\n", instance); + DRM_DEBUG("invalid ip instance: %d\n", instance); return -EINVAL; } @@ -255,13 +255,13 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, ip_num_rings = adev->vcn.num_enc_rings; break; default: - DRM_ERROR("unknown ip type: %d\n", hw_ip); + DRM_DEBUG("unknown ip type: %d\n", hw_ip); return -EINVAL; } if (ring >= ip_num_rings) { - DRM_ERROR("Ring index:%d exceeds maximum:%d for ip:%d\n", - ring, ip_num_rings, hw_ip); + DRM_DEBUG("Ring index:%d exceeds maximum:%d for ip:%d\n", + ring, ip_num_rings, hw_ip); return -EINVAL; } @@ -292,7 +292,7 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev, default: *out_ring = NULL; r = -EINVAL; - DRM_ERROR("unknown HW IP type: %d\n", mapper->hw_ip); + DRM_DEBUG("unknown HW IP type: %d\n", mapper->hw_ip); } out_unlock: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index b18c2b96691f..a6b89e3932a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -79,8 +79,7 @@ struct amdgpu_fence_driver { int amdgpu_fence_driver_init(struct amdgpu_device *adev); void amdgpu_fence_driver_fini(struct amdgpu_device *adev); -void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); -void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring); +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, unsigned num_hw_submission); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index a4bf21f8f1c1..ebe1ffbab0c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -35,6 +35,7 @@ struct amdgpu_sync_entry { struct hlist_node node; struct dma_fence *fence; + bool explicit; }; static struct kmem_cache *amdgpu_sync_slab; @@ -141,7 +142,7 @@ static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f) * */ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct dma_fence *f) + struct dma_fence *f, bool explicit) { struct amdgpu_sync_entry *e; @@ -159,6 +160,8 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, if (!e) return -ENOMEM; + e->explicit = explicit; + hash_add(sync->fences, &e->node, f->context); e->fence = dma_fence_get(f); return 0; @@ -189,10 +192,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, /* always sync to the exclusive fence */ f = reservation_object_get_excl(resv); - r = amdgpu_sync_fence(adev, sync, f); - - if (explicit_sync) - return r; + r = amdgpu_sync_fence(adev, sync, f, false); flist = reservation_object_get_list(resv); if (!flist || r) @@ -212,15 +212,15 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, (fence_owner == AMDGPU_FENCE_OWNER_VM))) continue; - /* Ignore fence from the same owner as + /* Ignore fence from the same owner and explicit one as * long as it isn't undefined. */ if (owner != AMDGPU_FENCE_OWNER_UNDEFINED && - fence_owner == owner) + (fence_owner == owner || explicit_sync)) continue; } - r = amdgpu_sync_fence(adev, sync, f); + r = amdgpu_sync_fence(adev, sync, f, false); if (r) break; } @@ -275,19 +275,21 @@ struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, * amdgpu_sync_get_fence - get the next fence from the sync object * * @sync: sync object to use + * @explicit: true if the next fence is explicit * * Get and removes the next fence from the sync object not signaled yet. */ -struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync) +struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit) { struct amdgpu_sync_entry *e; struct hlist_node *tmp; struct dma_fence *f; int i; - hash_for_each_safe(sync->fences, i, tmp, e, node) { f = e->fence; + if (explicit) + *explicit = e->explicit; hash_del(&e->node); kmem_cache_free(amdgpu_sync_slab, e); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h index 70d7e3a279a0..7aba38d5c9df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h @@ -41,7 +41,7 @@ struct amdgpu_sync { void amdgpu_sync_create(struct amdgpu_sync *sync); int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct dma_fence *f); + struct dma_fence *f, bool explicit); int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, struct reservation_object *resv, @@ -49,7 +49,7 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, bool explicit_sync); struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct amdgpu_ring *ring); -struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); +struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit); int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr); void amdgpu_sync_free(struct amdgpu_sync *sync); int amdgpu_sync_init(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index ad5bf86ee8a3..952e0bf3bc84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -110,7 +110,7 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev) ring = adev->mman.buffer_funcs_ring; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; r = amd_sched_entity_init(&ring->sched, &adev->mman.entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up TTM BO move run queue.\n"); goto error_entity; @@ -282,8 +282,7 @@ static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo, { uint64_t addr = 0; - if (mem->mem_type != TTM_PL_TT || - amdgpu_gtt_mgr_is_allocated(mem)) { + if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) { addr = mm_node->start << PAGE_SHIFT; addr += bo->bdev->man[mem->mem_type].gpu_offset; } @@ -369,7 +368,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, * dst to window 1 */ if (src->mem->mem_type == TTM_PL_TT && - !amdgpu_gtt_mgr_is_allocated(src->mem)) { + !amdgpu_gtt_mgr_has_gart_addr(src->mem)) { r = amdgpu_map_buffer(src->bo, src->mem, PFN_UP(cur_size + src_page_offset), src_node_start, 0, ring, @@ -383,7 +382,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, } if (dst->mem->mem_type == TTM_PL_TT && - !amdgpu_gtt_mgr_is_allocated(dst->mem)) { + !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) { r = amdgpu_map_buffer(dst->bo, dst->mem, PFN_UP(cur_size + dst_page_offset), dst_node_start, 1, ring, @@ -467,9 +466,8 @@ error: return r; } -static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { struct amdgpu_device *adev; @@ -489,8 +487,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); if (unlikely(r)) { return r; } @@ -504,19 +501,18 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, if (unlikely(r)) { goto out_cleanup; } - r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); + r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem); if (unlikely(r)) { goto out_cleanup; } - r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, new_mem); out_cleanup: ttm_bo_mem_put(bo, &tmp_mem); return r; } -static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { struct amdgpu_device *adev; @@ -536,16 +532,15 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx); if (unlikely(r)) { return r; } - r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem); + r = ttm_bo_move_ttm(bo, ctx->interruptible, ctx->no_wait_gpu, &tmp_mem); if (unlikely(r)) { goto out_cleanup; } - r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); + r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem); if (unlikely(r)) { goto out_cleanup; } @@ -554,10 +549,9 @@ out_cleanup: return r; } -static int amdgpu_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, - struct ttm_mem_reg *new_mem) +static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, + struct ttm_mem_reg *new_mem) { struct amdgpu_device *adev; struct amdgpu_bo *abo; @@ -592,19 +586,19 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { - r = amdgpu_move_vram_ram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem); } else if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_VRAM) { - r = amdgpu_move_ram_vram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem); } else { - r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); + r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, + new_mem, old_mem); } if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, new_mem); if (r) { return r; } @@ -690,7 +684,6 @@ struct amdgpu_ttm_tt { struct list_head guptasks; atomic_t mmu_invalidations; uint32_t last_set_pages; - struct list_head list; }; int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages) @@ -861,44 +854,35 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm, bo_mem->mem_type == AMDGPU_PL_OA) return -EINVAL; - if (!amdgpu_gtt_mgr_is_allocated(bo_mem)) + if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { + gtt->offset = AMDGPU_BO_INVALID_OFFSET; return 0; + } - spin_lock(>t->adev->gtt_list_lock); flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem); gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages, ttm->pages, gtt->ttm.dma_address, flags); - if (r) { + if (r) DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", ttm->num_pages, gtt->offset); - goto error_gart_bind; - } - - list_add_tail(>t->list, >t->adev->gtt_list); -error_gart_bind: - spin_unlock(>t->adev->gtt_list_lock); return r; } -bool amdgpu_ttm_is_bound(struct ttm_tt *ttm) -{ - struct amdgpu_ttm_tt *gtt = (void *)ttm; - - return gtt && !list_empty(>t->list); -} - -int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) +int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); - struct ttm_tt *ttm = bo->ttm; + struct ttm_operation_ctx ctx = { false, false }; + struct amdgpu_ttm_tt *gtt = (void*)bo->ttm; struct ttm_mem_reg tmp; struct ttm_placement placement; struct ttm_place placements; + uint64_t flags; int r; - if (!ttm || amdgpu_ttm_is_bound(ttm)) + if (bo->mem.mem_type != TTM_PL_TT || + amdgpu_gtt_mgr_has_gart_addr(&bo->mem)) return 0; tmp = bo->mem; @@ -912,43 +896,44 @@ int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem) placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp, true, false); + r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); if (unlikely(r)) return r; - r = ttm_bo_move_ttm(bo, true, false, &tmp); - if (unlikely(r)) + flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp); + gtt->offset = (u64)tmp.start << PAGE_SHIFT; + r = amdgpu_gart_bind(adev, gtt->offset, bo->ttm->num_pages, + bo->ttm->pages, gtt->ttm.dma_address, flags); + if (unlikely(r)) { ttm_bo_mem_put(bo, &tmp); - else - bo->offset = (bo->mem.start << PAGE_SHIFT) + - bo->bdev->man[bo->mem.mem_type].gpu_offset; + return r; + } - return r; + ttm_bo_mem_put(bo, &bo->mem); + bo->mem = tmp; + bo->offset = (bo->mem.start << PAGE_SHIFT) + + bo->bdev->man[bo->mem.mem_type].gpu_offset; + + return 0; } -int amdgpu_ttm_recover_gart(struct amdgpu_device *adev) +int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) { - struct amdgpu_ttm_tt *gtt, *tmp; - struct ttm_mem_reg bo_mem; + struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); + struct amdgpu_ttm_tt *gtt = (void *)tbo->ttm; uint64_t flags; int r; - bo_mem.mem_type = TTM_PL_TT; - spin_lock(&adev->gtt_list_lock); - list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) { - flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem); - r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, - gtt->ttm.ttm.pages, gtt->ttm.dma_address, - flags); - if (r) { - spin_unlock(&adev->gtt_list_lock); - DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", - gtt->ttm.ttm.num_pages, gtt->offset); - return r; - } - } - spin_unlock(&adev->gtt_list_lock); - return 0; + if (!gtt) + return 0; + + flags = amdgpu_ttm_tt_pte_flags(adev, >t->ttm.ttm, &tbo->mem); + r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages, + gtt->ttm.ttm.pages, gtt->ttm.dma_address, flags); + if (r) + DRM_ERROR("failed to bind %lu pages at 0x%08llX\n", + gtt->ttm.ttm.num_pages, gtt->offset); + return r; } static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) @@ -959,20 +944,14 @@ static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm) if (gtt->userptr) amdgpu_ttm_tt_unpin_userptr(ttm); - if (!amdgpu_ttm_is_bound(ttm)) + if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) return 0; /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ - spin_lock(>t->adev->gtt_list_lock); r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages); - if (r) { + if (r) DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n", gtt->ttm.ttm.num_pages, gtt->offset); - goto error_unbind; - } - list_del_init(>t->list); -error_unbind: - spin_unlock(>t->adev->gtt_list_lock); return r; } @@ -1009,7 +988,6 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev, kfree(gtt); return NULL; } - INIT_LIST_HEAD(>t->list); return >t->ttm.ttm; } @@ -1348,10 +1326,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of VRAM memory ready\n", (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); - if (amdgpu_gtt_size == -1) - gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), - adev->mc.mc_vram_size); - else + if (amdgpu_gtt_size == -1) { + struct sysinfo si; + + si_meminfo(&si); + gtt_size = max(AMDGPU_DEFAULT_GTT_SIZE_MB << 20, + (uint64_t)si.totalram * si.mem_unit * 3/4); + } else gtt_size = (uint64_t)amdgpu_gtt_size << 20; r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT); if (r) { @@ -1410,19 +1391,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) void amdgpu_ttm_fini(struct amdgpu_device *adev) { - int r; - if (!adev->mman.initialized) return; + amdgpu_ttm_debugfs_fini(adev); - if (adev->stolen_vga_memory) { - r = amdgpu_bo_reserve(adev->stolen_vga_memory, true); - if (r == 0) { - amdgpu_bo_unpin(adev->stolen_vga_memory); - amdgpu_bo_unreserve(adev->stolen_vga_memory); - } - amdgpu_bo_unref(&adev->stolen_vga_memory); - } + amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); + amdgpu_fw_reserve_vram_fini(adev); + ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT); if (adev->gds.mem.total_size) @@ -1432,7 +1407,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) if (adev->gds.oa.total_size) ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA); ttm_bo_device_release(&adev->mman.bdev); - amdgpu_gart_fini(adev); amdgpu_ttm_global_fini(adev); adev->mman.initialized = false; DRM_INFO("amdgpu: ttm finalized\n"); @@ -1628,7 +1602,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, } if (bo->tbo.mem.mem_type == TTM_PL_TT) { - r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem); + r = amdgpu_ttm_alloc_gart(&bo->tbo); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index abd4084982a3..4f9433e61406 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -67,8 +67,9 @@ struct amdgpu_copy_mem { extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func; extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func; -bool amdgpu_gtt_mgr_is_allocated(struct ttm_mem_reg *mem); +bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem); uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man); +int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man); uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man); uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man); @@ -90,9 +91,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_fence **fence); int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); -bool amdgpu_ttm_is_bound(struct ttm_tt *ttm); -int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem); -int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); +int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); +int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index 65649026b836..474f88fbafce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -359,7 +359,6 @@ static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, int amdgpu_ucode_init_bo(struct amdgpu_device *adev) { - struct amdgpu_bo **bo = &adev->firmware.fw_buf; uint64_t fw_offset = 0; int i, err; struct amdgpu_firmware_info *ucode = NULL; @@ -370,36 +369,16 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) return 0; } - if (!amdgpu_sriov_vf(adev) || !adev->in_sriov_reset) { - err = amdgpu_bo_create(adev, adev->firmware.fw_size, PAGE_SIZE, true, + if (!adev->in_gpu_reset) { + err = amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, - NULL, NULL, 0, bo); + &adev->firmware.fw_buf, + &adev->firmware.fw_buf_mc, + &adev->firmware.fw_buf_ptr); if (err) { - dev_err(adev->dev, "(%d) Firmware buffer allocate failed\n", err); + dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); goto failed; } - - err = amdgpu_bo_reserve(*bo, false); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer reserve failed\n", err); - goto failed_reserve; - } - - err = amdgpu_bo_pin(*bo, amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, - &adev->firmware.fw_buf_mc); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer pin failed\n", err); - goto failed_pin; - } - - err = amdgpu_bo_kmap(*bo, &adev->firmware.fw_buf_ptr); - if (err) { - dev_err(adev->dev, "(%d) Firmware buffer kmap failed\n", err); - goto failed_kmap; - } - - amdgpu_bo_unreserve(*bo); } memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); @@ -436,12 +415,6 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev) } return 0; -failed_kmap: - amdgpu_bo_unpin(*bo); -failed_pin: - amdgpu_bo_unreserve(*bo); -failed_reserve: - amdgpu_bo_unref(bo); failed: if (err) adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; @@ -464,8 +437,10 @@ int amdgpu_ucode_fini_bo(struct amdgpu_device *adev) ucode->kaddr = NULL; } } - amdgpu_bo_unref(&adev->firmware.fw_buf); - adev->firmware.fw_buf = NULL; + + amdgpu_bo_free_kernel(&adev->firmware.fw_buf, + &adev->firmware.fw_buf_mc, + &adev->firmware.fw_buf_ptr); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index e8bd50cf9785..2f2a9e17fdb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -232,7 +232,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) ring = &adev->uvd.ring; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up UVD run queue.\n"); return r; @@ -408,6 +408,7 @@ static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) */ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) { + struct ttm_operation_ctx tctx = { false, false }; struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; uint32_t cmd; @@ -430,7 +431,7 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) } amdgpu_uvd_force_into_uvd_segment(bo); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); } return r; @@ -949,6 +950,7 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, bool direct, struct dma_fence **fence) { + struct ttm_operation_ctx ctx = { true, false }; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head head; @@ -975,7 +977,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, amdgpu_uvd_force_into_uvd_segment(bo); } - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) goto err; @@ -1218,7 +1220,7 @@ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h index 3553b92bf69a..845eea993f75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h @@ -31,6 +31,10 @@ #define AMDGPU_UVD_SESSION_SIZE (50*1024) #define AMDGPU_UVD_FIRMWARE_OFFSET 256 +#define AMDGPU_UVD_FIRMWARE_SIZE(adev) \ + (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \ + 8) - AMDGPU_UVD_FIRMWARE_OFFSET) + struct amdgpu_uvd { struct amdgpu_bo *vcpu_bo; void *cpu_addr; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 2918de2f39ec..ba6d846b08ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -176,7 +176,7 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) ring = &adev->vce.ring[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vce.entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCE run queue.\n"); return r; @@ -544,6 +544,55 @@ err: } /** + * amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary + * + * @p: parser context + * @lo: address of lower dword + * @hi: address of higher dword + * @size: minimum size + * @index: bs/fb index + * + * Make sure that no BO cross a 4GB boundary. + */ +static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx, + int lo, int hi, unsigned size, int32_t index) +{ + int64_t offset = ((uint64_t)size) * ((int64_t)index); + struct ttm_operation_ctx ctx = { false, false }; + struct amdgpu_bo_va_mapping *mapping; + unsigned i, fpfn, lpfn; + struct amdgpu_bo *bo; + uint64_t addr; + int r; + + addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) | + ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32; + if (index >= 0) { + addr += offset; + fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT; + lpfn = 0x100000000ULL >> PAGE_SHIFT; + } else { + fpfn = 0; + lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT; + } + + r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping); + if (r) { + DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n", + addr, lo, hi, size, index); + return r; + } + + for (i = 0; i < bo->placement.num_placement; ++i) { + bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn); + bo->placements[i].lpfn = bo->placements[i].fpfn ? + min(bo->placements[i].fpfn, lpfn) : lpfn; + } + return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); +} + + +/** * amdgpu_vce_cs_reloc - command submission relocation * * @p: parser context @@ -648,12 +697,13 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) uint32_t allocated = 0; uint32_t tmp, handle = 0; uint32_t *size = &tmp; - int i, r = 0, idx = 0; + unsigned idx; + int i, r = 0; p->job->vm = NULL; ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); - while (idx < ib->length_dw) { + for (idx = 0; idx < ib->length_dw;) { uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); @@ -664,6 +714,54 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) } switch (cmd) { + case 0x00000002: /* task info */ + fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6); + bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7); + break; + + case 0x03000001: /* encode */ + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10, + idx + 9, 0, 0); + if (r) + goto out; + + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12, + idx + 11, 0, 0); + if (r) + goto out; + break; + + case 0x05000001: /* context buffer */ + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, + idx + 2, 0, 0); + if (r) + goto out; + break; + + case 0x05000004: /* video bitstream buffer */ + tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4); + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2, + tmp, bs_idx); + if (r) + goto out; + break; + + case 0x05000005: /* feedback buffer */ + r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2, + 4096, fb_idx); + if (r) + goto out; + break; + } + + idx += len / 4; + } + + for (idx = 0; idx < ib->length_dw;) { + uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx); + uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1); + + switch (cmd) { case 0x00000001: /* session */ handle = amdgpu_get_ib_value(p, ib_idx, idx + 2); session_idx = amdgpu_vce_validate_handle(p, handle, @@ -954,7 +1052,7 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) } if (i < timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -999,7 +1097,7 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 041e0121590c..d7ba048c2f80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -35,8 +35,8 @@ #include "soc15d.h" #include "soc15_common.h" -#include "vega10/soc15ip.h" -#include "raven1/VCN/vcn_1_0_offset.h" +#include "soc15ip.h" +#include "vcn/vcn_1_0_offset.h" /* 1 second timeout */ #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000) @@ -106,7 +106,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ring = &adev->vcn.ring_dec; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCN dec run queue.\n"); return r; @@ -115,7 +115,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ring = &adev->vcn.ring_enc[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r != 0) { DRM_ERROR("Failed setting up VCN enc run queue.\n"); return r; @@ -261,7 +261,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", @@ -274,6 +274,7 @@ int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring) static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, bool direct, struct dma_fence **fence) { + struct ttm_operation_ctx ctx = { true, false }; struct ttm_validate_buffer tv; struct ww_acquire_ctx ticket; struct list_head head; @@ -294,7 +295,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *b if (r) return r; - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) goto err; @@ -467,7 +468,7 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } @@ -500,7 +501,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -643,7 +644,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 6738df836a70..e7dfb7b44b4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -24,6 +24,14 @@ #include "amdgpu.h" #define MAX_KIQ_REG_WAIT 100000000 /* in usecs */ +bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) +{ + /* By now all MMIO pages except mailbox are blocked */ + /* if blocking is enabled in hypervisor. Choose the */ + /* SCRATCH_REG0 to test. */ + return RREG32_NO_KIQ(0xc040) == 0xffffffff; +} + int amdgpu_allocate_static_csa(struct amdgpu_device *adev) { int r; @@ -39,6 +47,12 @@ int amdgpu_allocate_static_csa(struct amdgpu_device *adev) return 0; } +void amdgpu_free_static_csa(struct amdgpu_device *adev) { + amdgpu_bo_free_kernel(&adev->virt.csa_obj, + &adev->virt.csa_vmid0_addr, + NULL); +} + /* * amdgpu_map_static_csa should be called during amdgpu_vm_init * it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE" @@ -107,8 +121,6 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->enable_virtual_display = true; adev->cg_flags = 0; adev->pg_flags = 0; - - mutex_init(&adev->virt.lock_reset); } uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) @@ -228,6 +240,22 @@ int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) } /** + * amdgpu_virt_wait_reset() - wait for reset gpu completed + * @amdgpu: amdgpu device. + * Wait for GPU reset completed. + * Return: Zero if reset success, otherwise will return error. + */ +int amdgpu_virt_wait_reset(struct amdgpu_device *adev) +{ + struct amdgpu_virt *virt = &adev->virt; + + if (!virt->ops || !virt->ops->wait_reset) + return -EINVAL; + + return virt->ops->wait_reset(adev); +} + +/** * amdgpu_virt_alloc_mm_table() - alloc memory for mm table * @amdgpu: amdgpu device. * MM table is used by UVD and VCE for its initialization @@ -296,7 +324,6 @@ int amdgpu_virt_fw_reserve_get_checksum(void *obj, void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) { - uint32_t pf2vf_ver = 0; uint32_t pf2vf_size = 0; uint32_t checksum = 0; uint32_t checkval; @@ -309,9 +336,9 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) adev->virt.fw_reserve.p_pf2vf = (struct amdgim_pf2vf_info_header *)( adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET); - pf2vf_ver = adev->virt.fw_reserve.p_pf2vf->version; AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size); AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum); + AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature); /* pf2vf message must be in 4K */ if (pf2vf_size > 0 && pf2vf_size < 4096) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index b89d37fc406f..6a83425aa9ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -55,6 +55,7 @@ struct amdgpu_virt_ops { int (*req_full_gpu)(struct amdgpu_device *adev, bool init); int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); int (*reset_gpu)(struct amdgpu_device *adev); + int (*wait_reset)(struct amdgpu_device *adev); void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); }; @@ -80,6 +81,8 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, /* GIM supports feature of loading uCodes */ AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, + /* VRAM LOST by GIM */ + AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, }; struct amdgim_pf2vf_info_header { @@ -238,7 +241,6 @@ struct amdgpu_virt { uint64_t csa_vmid0_addr; bool chained_ib_support; uint32_t reg_val_offs; - struct mutex lock_reset; struct amdgpu_irq_src ack_irq; struct amdgpu_irq_src rcv_irq; struct work_struct flr_work; @@ -246,6 +248,7 @@ struct amdgpu_virt { const struct amdgpu_virt_ops *ops; struct amdgpu_vf_error_buffer vf_errors; struct amdgpu_virt_fw_reserve fw_reserve; + uint32_t gim_feature; }; #define AMDGPU_CSA_SIZE (8 * 1024) @@ -276,16 +279,18 @@ static inline bool is_virtual_machine(void) } struct amdgpu_vm; +bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); int amdgpu_allocate_static_csa(struct amdgpu_device *adev); int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo_va **bo_va); +void amdgpu_free_static_csa(struct amdgpu_device *adev); void amdgpu_virt_init_setting(struct amdgpu_device *adev); uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); -int amdgpu_sriov_gpu_reset(struct amdgpu_device *adev, struct amdgpu_job *job); +int amdgpu_virt_wait_reset(struct amdgpu_device *adev); int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index c8c26f21993c..3ecdbdfb04dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -139,6 +139,24 @@ struct amdgpu_prt_cb { }; /** + * amdgpu_vm_level_shift - return the addr shift for each level + * + * @adev: amdgpu_device pointer + * + * Returns the number of bits the pfn needs to be right shifted for a level. + */ +static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev, + unsigned level) +{ + if (level != adev->vm_manager.num_level) + return 9 * (adev->vm_manager.num_level - level - 1) + + adev->vm_manager.block_size; + else + /* For the page tables on the leaves */ + return 0; +} + +/** * amdgpu_vm_num_entries - return the number of entries in a PD/PT * * @adev: amdgpu_device pointer @@ -148,17 +166,17 @@ struct amdgpu_prt_cb { static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev, unsigned level) { + unsigned shift = amdgpu_vm_level_shift(adev, 0); + if (level == 0) /* For the root directory */ - return adev->vm_manager.max_pfn >> - (adev->vm_manager.block_size * - adev->vm_manager.num_level); - else if (level == adev->vm_manager.num_level) + return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; + else if (level != adev->vm_manager.num_level) + /* Everything in between */ + return 512; + else /* For the page tables on the leaves */ return AMDGPU_VM_PTE_COUNT(adev); - else - /* Everything in between */ - return 1 << adev->vm_manager.block_size; } /** @@ -288,8 +306,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev, uint64_t saddr, uint64_t eaddr, unsigned level) { - unsigned shift = (adev->vm_manager.num_level - level) * - adev->vm_manager.block_size; + unsigned shift = amdgpu_vm_level_shift(adev, level); unsigned pt_idx, from, to; int r; u64 flags; @@ -471,7 +488,7 @@ static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, id->pd_gpu_addr = 0; tmp = amdgpu_sync_peek_fence(&id->active, ring); if (tmp) { - r = amdgpu_sync_fence(adev, sync, tmp); + r = amdgpu_sync_fence(adev, sync, tmp, false); return r; } } @@ -479,7 +496,7 @@ static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm, /* Good we can use this VMID. Remember this submission as * user of the VMID. */ - r = amdgpu_sync_fence(ring->adev, &id->active, fence); + r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); if (r) goto out; @@ -566,7 +583,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, } - r = amdgpu_sync_fence(ring->adev, sync, &array->base); + r = amdgpu_sync_fence(ring->adev, sync, &array->base, false); dma_fence_put(&array->base); if (r) goto error; @@ -609,7 +626,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, /* Good we can use this VMID. Remember this submission as * user of the VMID. */ - r = amdgpu_sync_fence(ring->adev, &id->active, fence); + r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); if (r) goto error; @@ -629,7 +646,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, id = idle; /* Remember this submission as user of the VMID */ - r = amdgpu_sync_fence(ring->adev, &id->active, fence); + r = amdgpu_sync_fence(ring->adev, &id->active, fence, false); if (r) goto error; @@ -1302,18 +1319,19 @@ void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr, struct amdgpu_vm_pt **entry, struct amdgpu_vm_pt **parent) { - unsigned idx, level = p->adev->vm_manager.num_level; + unsigned level = 0; *parent = NULL; *entry = &p->vm->root; while ((*entry)->entries) { - idx = addr >> (p->adev->vm_manager.block_size * level--); + unsigned idx = addr >> amdgpu_vm_level_shift(p->adev, level++); + idx %= amdgpu_bo_size((*entry)->base.bo) / 8; *parent = *entry; *entry = &(*entry)->entries[idx]; } - if (level) + if (level != p->adev->vm_manager.num_level) *entry = NULL; } @@ -1639,7 +1657,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, addr = 0; } - r = amdgpu_sync_fence(adev, &job->sync, exclusive); + r = amdgpu_sync_fence(adev, &job->sync, exclusive, false); if (r) goto error_free; @@ -2556,47 +2574,57 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) } /** - * amdgpu_vm_set_fragment_size - adjust fragment size in PTE - * - * @adev: amdgpu_device pointer - * @fragment_size_default: the default fragment size if it's set auto - */ -void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, - uint32_t fragment_size_default) -{ - if (amdgpu_vm_fragment_size == -1) - adev->vm_manager.fragment_size = fragment_size_default; - else - adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; -} - -/** * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size * * @adev: amdgpu_device pointer * @vm_size: the default vm size if it's set auto */ -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, - uint32_t fragment_size_default) +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, + uint32_t fragment_size_default, unsigned max_level, + unsigned max_bits) { - /* adjust vm size firstly */ - if (amdgpu_vm_size == -1) - adev->vm_manager.vm_size = vm_size; - else - adev->vm_manager.vm_size = amdgpu_vm_size; + uint64_t tmp; - /* block size depends on vm size */ - if (amdgpu_vm_block_size == -1) + /* adjust vm size first */ + if (amdgpu_vm_size != -1) { + unsigned max_size = 1 << (max_bits - 30); + + vm_size = amdgpu_vm_size; + if (vm_size > max_size) { + dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n", + amdgpu_vm_size, max_size); + vm_size = max_size; + } + } + + adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; + + tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); + if (amdgpu_vm_block_size != -1) + tmp >>= amdgpu_vm_block_size - 9; + tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; + adev->vm_manager.num_level = min(max_level, (unsigned)tmp); + + /* block size depends on vm size and hw setup*/ + if (amdgpu_vm_block_size != -1) adev->vm_manager.block_size = - amdgpu_vm_get_block_size(adev->vm_manager.vm_size); + min((unsigned)amdgpu_vm_block_size, max_bits + - AMDGPU_GPU_PAGE_SHIFT + - 9 * adev->vm_manager.num_level); + else if (adev->vm_manager.num_level > 1) + adev->vm_manager.block_size = 9; else - adev->vm_manager.block_size = amdgpu_vm_block_size; + adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp); - amdgpu_vm_set_fragment_size(adev, fragment_size_default); + if (amdgpu_vm_fragment_size == -1) + adev->vm_manager.fragment_size = fragment_size_default; + else + adev->vm_manager.fragment_size = amdgpu_vm_fragment_size; - DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n", - adev->vm_manager.vm_size, adev->vm_manager.block_size, - adev->vm_manager.fragment_size); + DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n", + vm_size, adev->vm_manager.num_level + 1, + adev->vm_manager.block_size, + adev->vm_manager.fragment_size); } /** @@ -2637,7 +2665,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ring = adev->vm_manager.vm_pte_rings[ring_instance]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL]; r = amd_sched_entity_init(&ring->sched, &vm->entity, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index bae77353447b..43ea131dd411 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -96,6 +96,19 @@ struct amdgpu_bo_list_entry; /* hardcode that limit for now */ #define AMDGPU_VA_RESERVED_SIZE (8ULL << 20) +/* VA hole for 48bit addresses on Vega10 */ +#define AMDGPU_VA_HOLE_START 0x0000800000000000ULL +#define AMDGPU_VA_HOLE_END 0xffff800000000000ULL + +/* + * Hardware is programmed as if the hole doesn't exists with start and end + * address values. + * + * This mask is used to remove the upper 16bits of the VA and so come up with + * the linear addr value. + */ +#define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL + /* max vmids dedicated for process */ #define AMDGPU_VM_MAX_RESERVED_VMID 1 @@ -221,7 +234,6 @@ struct amdgpu_vm_manager { uint64_t max_pfn; uint32_t num_level; - uint64_t vm_size; uint32_t block_size; uint32_t fragment_size; /* vram base address for page table entry */ @@ -312,10 +324,9 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, uint64_t addr); void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va); -void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, - uint32_t fragment_size_default); -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size, - uint32_t fragment_size_default); +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, + uint32_t fragment_size_default, unsigned max_level, + unsigned max_bits); int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, struct amdgpu_job *job); diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c index b374653bd6cf..f9b2ce9a98f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_i2c.c @@ -65,8 +65,15 @@ static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan, args.ucRegIndex = buf[0]; if (num) num--; - if (num) - memcpy(&out, &buf[1], num); + if (num) { + if (buf) { + memcpy(&out, &buf[1], num); + } else { + DRM_ERROR("hw i2c: missing buf with num > 1\n"); + r = -EINVAL; + goto done; + } + } args.lpI2CDataOut = cpu_to_le16(out); } else { if (num > ATOM_MAX_HW_I2C_READ) { diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 68b505c768ad..f11c0aacf19f 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -4540,9 +4540,9 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) return -EINVAL; - temp_reg = RREG32(mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -4553,10 +4553,10 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { @@ -4564,8 +4564,6 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; } j++; - if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; } break; case mmMC_SEQ_RESERVE_M: @@ -4577,8 +4575,6 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; default: break; @@ -6625,9 +6621,9 @@ static int ci_dpm_print_clock_levels(void *handle, for (i = 0; i < pcie_table->count; i++) size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" : - (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : - (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", (i == now) ? "*" : ""); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index a296f7bbe57c..8ba056a2a5da 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) case CHIP_BONAIRE: amdgpu_program_register_sequence(adev, bonaire_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); + ARRAY_SIZE(bonaire_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, bonaire_golden_registers, - (const u32)ARRAY_SIZE(bonaire_golden_registers)); + ARRAY_SIZE(bonaire_golden_registers)); amdgpu_program_register_sequence(adev, bonaire_golden_common_registers, - (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); + ARRAY_SIZE(bonaire_golden_common_registers)); amdgpu_program_register_sequence(adev, bonaire_golden_spm_registers, - (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); + ARRAY_SIZE(bonaire_golden_spm_registers)); break; case CHIP_KABINI: amdgpu_program_register_sequence(adev, kalindi_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, kalindi_golden_registers, - (const u32)ARRAY_SIZE(kalindi_golden_registers)); + ARRAY_SIZE(kalindi_golden_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_common_registers, - (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + ARRAY_SIZE(kalindi_golden_common_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_spm_registers, - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_MULLINS: amdgpu_program_register_sequence(adev, kalindi_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); + ARRAY_SIZE(kalindi_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, godavari_golden_registers, - (const u32)ARRAY_SIZE(godavari_golden_registers)); + ARRAY_SIZE(godavari_golden_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_common_registers, - (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); + ARRAY_SIZE(kalindi_golden_common_registers)); amdgpu_program_register_sequence(adev, kalindi_golden_spm_registers, - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); + ARRAY_SIZE(kalindi_golden_spm_registers)); break; case CHIP_KAVERI: amdgpu_program_register_sequence(adev, spectre_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); + ARRAY_SIZE(spectre_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, spectre_golden_registers, - (const u32)ARRAY_SIZE(spectre_golden_registers)); + ARRAY_SIZE(spectre_golden_registers)); amdgpu_program_register_sequence(adev, spectre_golden_common_registers, - (const u32)ARRAY_SIZE(spectre_golden_common_registers)); + ARRAY_SIZE(spectre_golden_common_registers)); amdgpu_program_register_sequence(adev, spectre_golden_spm_registers, - (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); + ARRAY_SIZE(spectre_golden_spm_registers)); break; case CHIP_HAWAII: amdgpu_program_register_sequence(adev, hawaii_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); + ARRAY_SIZE(hawaii_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, hawaii_golden_registers, - (const u32)ARRAY_SIZE(hawaii_golden_registers)); + ARRAY_SIZE(hawaii_golden_registers)); amdgpu_program_register_sequence(adev, hawaii_golden_common_registers, - (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); + ARRAY_SIZE(hawaii_golden_common_registers)); amdgpu_program_register_sequence(adev, hawaii_golden_spm_registers, - (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); + ARRAY_SIZE(hawaii_golden_spm_registers)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 60cecd117705..ed26dcbc4f79 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -657,7 +657,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -724,7 +724,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 4e519dc42916..a397111c2ced 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; default: break; @@ -2773,7 +2773,6 @@ static int dce_v10_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; dce_v10_0_set_display_funcs(adev); - dce_v10_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); @@ -2788,6 +2787,8 @@ static int dce_v10_0_early_init(void *handle) return -EINVAL; } + dce_v10_0_set_irq_funcs(adev); + return 0; } @@ -3635,13 +3636,16 @@ static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 11edc75edaa9..67e670989e81 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, polaris11_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); + ARRAY_SIZE(polaris11_golden_settings_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, polaris10_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); + ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; @@ -2876,7 +2876,6 @@ static int dce_v11_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; dce_v11_0_set_display_funcs(adev); - dce_v11_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); @@ -2903,6 +2902,8 @@ static int dce_v11_0_early_init(void *handle) return -EINVAL; } + dce_v11_0_set_irq_funcs(adev); + return 0; } @@ -3759,13 +3760,16 @@ static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index a51e35f824a1..bd2c4f727df6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2639,7 +2639,6 @@ static int dce_v6_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; dce_v6_0_set_display_funcs(adev); - dce_v6_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); @@ -2658,6 +2657,8 @@ static int dce_v6_0_early_init(void *handle) return -EINVAL; } + dce_v6_0_set_irq_funcs(adev); + return 0; } @@ -3441,13 +3442,16 @@ static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 9cf14b8b2db9..c008dc030687 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2664,7 +2664,6 @@ static int dce_v8_0_early_init(void *handle) adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; dce_v8_0_set_display_funcs(adev); - dce_v8_0_set_irq_funcs(adev); adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev); @@ -2688,6 +2687,8 @@ static int dce_v8_0_early_init(void *handle) return -EINVAL; } + dce_v8_0_set_irq_funcs(adev); + return 0; } @@ -3525,13 +3526,16 @@ static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c index a8829af120c1..120dd3b26fc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c @@ -44,6 +44,9 @@ static void dce_virtual_set_display_funcs(struct amdgpu_device *adev); static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev); static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev, int index); +static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, + int crtc, + enum amdgpu_interrupt_state state); /** * dce_virtual_vblank_wait - vblank wait asic callback. @@ -437,6 +440,8 @@ static int dce_virtual_sw_fini(void *handle) drm_kms_helper_poll_fini(adev->ddev); drm_mode_config_cleanup(adev->ddev); + /* clear crtcs pointer to avoid dce irq finish routine access freed data */ + memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS); adev->mode_info.mode_config_initialized = false; return 0; } @@ -489,6 +494,13 @@ static int dce_virtual_hw_init(void *handle) static int dce_virtual_hw_fini(void *handle) { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i = 0; + + for (i = 0; i<adev->mode_info.num_crtc; i++) + if (adev->mode_info.crtcs[i]) + dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE); + return 0; } @@ -723,7 +735,7 @@ static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *ad int crtc, enum amdgpu_interrupt_state state) { - if (crtc >= adev->mode_info.num_crtc) { + if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) { DRM_DEBUG("invalid crtc %d\n", crtc); return; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index dbbe986f90f2..edef17d93527 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1798,7 +1798,7 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", ring->idx, scratch, tmp); @@ -1951,7 +1951,7 @@ static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", @@ -2962,25 +2962,7 @@ static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - - switch (adev->asic_type) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - buffer[count++] = cpu_to_le32(0x2a00126a); - break; - case CHIP_VERDE: - buffer[count++] = cpu_to_le32(0x0000124a); - break; - case CHIP_OLAND: - buffer[count++] = cpu_to_le32(0x00000082); - break; - case CHIP_HAINAN: - buffer[count++] = cpu_to_le32(0x00000000); - break; - default: - buffer[count++] = cpu_to_le32(0x00000000); - break; - } + buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 419ba0ce7ee5..83d94c23aa78 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2085,7 +2085,7 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", ring->idx, scratch, tmp); @@ -2365,7 +2365,7 @@ static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", @@ -2551,29 +2551,8 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_BONAIRE: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_KAVERI: - amdgpu_ring_write(ring, 0x00000000); /* XXX */ - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_KABINI: - case CHIP_MULLINS: - amdgpu_ring_write(ring, 0x00000000); /* XXX */ - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_HAWAII: - amdgpu_ring_write(ring, 0x3a00161a); - amdgpu_ring_write(ring, 0x0000002e); - break; - default: - amdgpu_ring_write(ring, 0x00000000); - amdgpu_ring_write(ring, 0x00000000); - break; - } + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 9ecdf621a74a..d02493cf9175 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); amdgpu_program_register_sequence(adev, iceland_golden_common_all, - (const u32)ARRAY_SIZE(iceland_golden_common_all)); + ARRAY_SIZE(iceland_golden_common_all)); break; case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); amdgpu_program_register_sequence(adev, fiji_golden_common_all, - (const u32)ARRAY_SIZE(fiji_golden_common_all)); + ARRAY_SIZE(fiji_golden_common_all)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); amdgpu_program_register_sequence(adev, tonga_golden_common_all, - (const u32)ARRAY_SIZE(tonga_golden_common_all)); + ARRAY_SIZE(tonga_golden_common_all)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); amdgpu_program_register_sequence(adev, polaris11_golden_common_all, - (const u32)ARRAY_SIZE(polaris11_golden_common_all)); + ARRAY_SIZE(polaris11_golden_common_all)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); amdgpu_program_register_sequence(adev, polaris10_golden_common_all, - (const u32)ARRAY_SIZE(polaris10_golden_common_all)); + ARRAY_SIZE(polaris10_golden_common_all)); WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); if (adev->pdev->revision == 0xc7 && ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || @@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); amdgpu_program_register_sequence(adev, cz_golden_common_all, - (const u32)ARRAY_SIZE(cz_golden_common_all)); + ARRAY_SIZE(cz_golden_common_all)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); amdgpu_program_register_sequence(adev, stoney_golden_common_all, - (const u32)ARRAY_SIZE(stoney_golden_common_all)); + ARRAY_SIZE(stoney_golden_common_all)); break; default: break; @@ -804,7 +804,7 @@ static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", @@ -856,7 +856,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", @@ -2114,7 +2114,6 @@ static int gfx_v8_0_sw_fini(void *handle) amdgpu_gfx_compute_mqd_sw_fini(adev); amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); amdgpu_gfx_kiq_fini(adev); - amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); gfx_v8_0_mec_fini(adev); gfx_v8_0_rlc_fini(adev); @@ -3851,6 +3850,14 @@ static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) break; udelay(1); } + if (k == adev->usec_timeout) { + gfx_v8_0_select_se_sh(adev, 0xffffffff, + 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + i, j); + return; + } } } gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -4305,37 +4312,8 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); - switch (adev->asic_type) { - case CHIP_TONGA: - case CHIP_POLARIS10: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x0000002A); - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - amdgpu_ring_write(ring, 0x16000012); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_FIJI: - amdgpu_ring_write(ring, 0x3a00161a); - amdgpu_ring_write(ring, 0x0000002e); - break; - case CHIP_CARRIZO: - amdgpu_ring_write(ring, 0x00000002); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_TOPAZ: - amdgpu_ring_write(ring, adev->gfx.config.num_rbs == 1 ? - 0x00000000 : 0x00000002); - amdgpu_ring_write(ring, 0x00000000); - break; - case CHIP_STONEY: - amdgpu_ring_write(ring, 0x00000000); - amdgpu_ring_write(ring, 0x00000000); - break; - default: - BUG(); - } + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); + amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); @@ -4816,7 +4794,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) gfx_v8_0_kiq_setting(ring); - if (adev->in_sriov_reset) { /* for GPU_RESET case */ + if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); @@ -4853,7 +4831,7 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) struct vi_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation)); ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -4865,13 +4843,10 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation)); - } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ + } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); - /* reset ring buffer */ - ring->wptr = 0; - amdgpu_ring_clear_ring(ring); } else { amdgpu_ring_clear_ring(ring); } @@ -4946,6 +4921,13 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) /* Test KCQs */ for (i = 0; i < adev->gfx.num_compute_rings; i++) { ring = &adev->gfx.compute_ring[i]; + if (adev->in_gpu_reset) { + /* move reset ring buffer to here to workaround + * compute ring test failed + */ + ring->wptr = 0; + amdgpu_ring_clear_ring(ring); + } ring->ready = true; r = amdgpu_ring_test_ring(ring); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index da43813d67a4..6c5289ae67be 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -28,11 +28,11 @@ #include "soc15.h" #include "soc15d.h" -#include "vega10/soc15ip.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/vega10_enum.h" -#include "vega10/HDP/hdp_4_0_offset.h" +#include "soc15ip.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" +#include "vega10_enum.h" +#include "hdp/hdp_4_0_offset.h" #include "soc15_common.h" #include "clearstate_gfx9.h" @@ -232,18 +232,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_gc_9_0, - (const u32)ARRAY_SIZE(golden_settings_gc_9_0)); + ARRAY_SIZE(golden_settings_gc_9_0)); amdgpu_program_register_sequence(adev, golden_settings_gc_9_0_vg10, - (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10)); + ARRAY_SIZE(golden_settings_gc_9_0_vg10)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_gc_9_1, - (const u32)ARRAY_SIZE(golden_settings_gc_9_1)); + ARRAY_SIZE(golden_settings_gc_9_1)); amdgpu_program_register_sequence(adev, golden_settings_gc_9_1_rv1, - (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1)); + ARRAY_SIZE(golden_settings_gc_9_1_rv1)); break; default: break; @@ -327,7 +327,7 @@ static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) DRM_UDELAY(1); } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", @@ -379,7 +379,7 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", @@ -1464,7 +1464,6 @@ static int gfx_v9_0_sw_fini(void *handle) amdgpu_gfx_compute_mqd_sw_fini(adev); amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); amdgpu_gfx_kiq_fini(adev); - amdgpu_bo_free_kernel(&adev->virt.csa_obj, &adev->virt.csa_vmid0_addr, NULL); gfx_v9_0_mec_fini(adev); gfx_v9_0_ngg_fini(adev); @@ -1645,6 +1644,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) break; udelay(1); } + if (k == adev->usec_timeout) { + gfx_v9_0_select_se_sh(adev, 0xffffffff, + 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + i, j); + return; + } } } gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); @@ -2749,7 +2756,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) gfx_v9_0_kiq_setting(ring); - if (adev->in_sriov_reset) { /* for GPU_RESET case */ + if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); @@ -2787,7 +2794,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) struct v9_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!adev->in_sriov_reset && !adev->gfx.in_suspend) { + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -2799,7 +2806,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); - } else if (adev->in_sriov_reset) { /* for GPU_RESET case */ + } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ /* reset MQD to a clean status */ if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index c17996e18086..f1effadfbaa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -23,11 +23,11 @@ #include "amdgpu.h" #include "gfxhub_v1_0.h" -#include "vega10/soc15ip.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/GC/gc_9_0_default.h" -#include "vega10/vega10_enum.h" +#include "soc15ip.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" +#include "gc/gc_9_0_default.h" +#include "vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index f4603a7c8ef3..468281f10e8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -222,11 +222,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - if (mc->mc_vram_size > 0xFFC0000000ULL) { - dev_warn(adev->dev, "limiting VRAM\n"); - mc->real_vram_size = 0xFFC0000000ULL; - mc->mc_vram_size = 0xFFC0000000ULL; - } amdgpu_vram_location(adev, &adev->mc, base); amdgpu_gart_location(adev, mc); } @@ -283,6 +278,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) u32 tmp; int chansize, numchan; + int r; tmp = RREG32(mmMC_ARB_RAMCFG); if (tmp & (1 << 11)) { @@ -324,12 +320,17 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) break; } adev->mc.vram_width = numchan * chansize; - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); adev->mc.visible_vram_size = adev->mc.aper_size; /* set the gart size */ @@ -831,8 +832,7 @@ static int gmc_v6_0_sw_init(void *handle) if (r) return r; - amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); adev->mc.mc_mask = 0xffffffffffULL; @@ -877,7 +877,6 @@ static int gmc_v6_0_sw_init(void *handle) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ @@ -897,9 +896,9 @@ static int gmc_v6_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v6_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); release_firmware(adev->mc.fw); adev->mc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index b0528ca9207b..68a85051f4b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; @@ -240,12 +240,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - if (mc->mc_vram_size > 0xFFC0000000ULL) { - /* leave room for at least 1024M GTT */ - dev_warn(adev->dev, "limiting VRAM\n"); - mc->real_vram_size = 0xFFC0000000ULL; - mc->mc_vram_size = 0xFFC0000000ULL; - } amdgpu_vram_location(adev, &adev->mc, base); amdgpu_gart_location(adev, mc); } @@ -322,6 +316,8 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev) */ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) { + int r; + adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); if (!adev->mc.vram_width) { u32 tmp; @@ -367,13 +363,18 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) } adev->mc.vram_width = numchan * chansize; } - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + #ifdef CONFIG_X86_64 if (adev->flags & AMD_IS_APU) { adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; @@ -970,8 +971,7 @@ static int gmc_v7_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); /* Set the internal MC address mask * This is the max address of the GPU's @@ -1026,7 +1026,6 @@ static int gmc_v7_0_sw_init(void *handle) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ @@ -1046,9 +1045,9 @@ static int gmc_v7_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v7_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); release_firmware(adev->mc.fw); adev->mc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f368cfe2f585..46ec97e70e5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_stoney_common, - (const u32)ARRAY_SIZE(golden_settings_stoney_common)); + ARRAY_SIZE(golden_settings_stoney_common)); break; default: break; @@ -405,12 +405,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - if (mc->mc_vram_size > 0xFFC0000000ULL) { - /* leave room for at least 1024M GTT */ - dev_warn(adev->dev, "limiting VRAM\n"); - mc->real_vram_size = 0xFFC0000000ULL; - mc->mc_vram_size = 0xFFC0000000ULL; - } amdgpu_vram_location(adev, &adev->mc, base); amdgpu_gart_location(adev, mc); } @@ -498,6 +492,8 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) */ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) { + int r; + adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); if (!adev->mc.vram_width) { u32 tmp; @@ -543,13 +539,18 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) } adev->mc.vram_width = numchan * chansize; } - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); + #ifdef CONFIG_X86_64 if (adev->flags & AMD_IS_APU) { adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; @@ -1067,8 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle) * Currently set to 4GB ((1 << 20) 4k pages). * Max GPUVM size for cayman and SI is 40 bits. */ - amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); /* Set the internal MC address mask * This is the max address of the GPU's @@ -1123,7 +1123,6 @@ static int gmc_v8_0_sw_init(void *handle) * amdkfd will use VMIDs 8-15 */ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; - adev->vm_manager.num_level = 1; amdgpu_vm_manager_init(adev); /* base offset of vram pages */ @@ -1143,9 +1142,9 @@ static int gmc_v8_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v8_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); release_firmware(adev->mc.fw); adev->mc.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index c8f1aebeac7a..cc972153d401 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -25,17 +25,18 @@ #include "gmc_v9_0.h" #include "amdgpu_atomfirmware.h" -#include "vega10/soc15ip.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "vega10/HDP/hdp_4_0_sh_mask.h" -#include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/vega10_enum.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/ATHUB/athub_1_0_offset.h" +#include "soc15ip.h" +#include "hdp/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_sh_mask.h" +#include "gc/gc_9_0_sh_mask.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "vega10_enum.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "athub/athub_1_0_offset.h" #include "soc15_common.h" +#include "umc/umc_6_0_sh_mask.h" #include "nbio_v6_1.h" #include "nbio_v7_0.h" @@ -85,6 +86,121 @@ static const u32 golden_settings_athub_1_0_0[] = SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008 }; +/* Ecc related register addresses, (BASE + reg offset) */ +/* Universal Memory Controller caps (may be fused). */ +/* UMCCH:UmcLocalCap */ +#define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000) +#define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800) +#define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000) +#define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800) +#define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000) +#define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800) +#define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000) +#define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800) +#define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000) +#define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800) +#define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000) +#define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800) +#define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000) +#define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800) +#define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000) +#define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800) + +/* Universal Memory Controller Channel config. */ +/* UMCCH:UMC_CONFIG */ +#define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800) +#define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800) +#define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800) +#define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000) +#define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800) +#define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000) +#define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800) + +/* Universal Memory Controller Channel Ecc config. */ +/* UMCCH:EccCtrl */ +#define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800) +#define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800) +#define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800) +#define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000) +#define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800) +#define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000) +#define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800) + +static const uint32_t ecc_umclocalcap_addrs[] = { + UMCLOCALCAPS_ADDR0, + UMCLOCALCAPS_ADDR1, + UMCLOCALCAPS_ADDR2, + UMCLOCALCAPS_ADDR3, + UMCLOCALCAPS_ADDR4, + UMCLOCALCAPS_ADDR5, + UMCLOCALCAPS_ADDR6, + UMCLOCALCAPS_ADDR7, + UMCLOCALCAPS_ADDR8, + UMCLOCALCAPS_ADDR9, + UMCLOCALCAPS_ADDR10, + UMCLOCALCAPS_ADDR11, + UMCLOCALCAPS_ADDR12, + UMCLOCALCAPS_ADDR13, + UMCLOCALCAPS_ADDR14, + UMCLOCALCAPS_ADDR15, +}; + +static const uint32_t ecc_umcch_umc_config_addrs[] = { + UMCCH_UMC_CONFIG_ADDR0, + UMCCH_UMC_CONFIG_ADDR1, + UMCCH_UMC_CONFIG_ADDR2, + UMCCH_UMC_CONFIG_ADDR3, + UMCCH_UMC_CONFIG_ADDR4, + UMCCH_UMC_CONFIG_ADDR5, + UMCCH_UMC_CONFIG_ADDR6, + UMCCH_UMC_CONFIG_ADDR7, + UMCCH_UMC_CONFIG_ADDR8, + UMCCH_UMC_CONFIG_ADDR9, + UMCCH_UMC_CONFIG_ADDR10, + UMCCH_UMC_CONFIG_ADDR11, + UMCCH_UMC_CONFIG_ADDR12, + UMCCH_UMC_CONFIG_ADDR13, + UMCCH_UMC_CONFIG_ADDR14, + UMCCH_UMC_CONFIG_ADDR15, +}; + +static const uint32_t ecc_umcch_eccctrl_addrs[] = { + UMCCH_ECCCTRL_ADDR0, + UMCCH_ECCCTRL_ADDR1, + UMCCH_ECCCTRL_ADDR2, + UMCCH_ECCCTRL_ADDR3, + UMCCH_ECCCTRL_ADDR4, + UMCCH_ECCCTRL_ADDR5, + UMCCH_ECCCTRL_ADDR6, + UMCCH_ECCCTRL_ADDR7, + UMCCH_ECCCTRL_ADDR8, + UMCCH_ECCCTRL_ADDR9, + UMCCH_ECCCTRL_ADDR10, + UMCCH_ECCCTRL_ADDR11, + UMCCH_ECCCTRL_ADDR12, + UMCCH_ECCCTRL_ADDR13, + UMCCH_ECCCTRL_ADDR14, + UMCCH_ECCCTRL_ADDR15, +}; + static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, @@ -389,6 +505,85 @@ static int gmc_v9_0_early_init(void *handle) return 0; } +static int gmc_v9_0_ecc_available(struct amdgpu_device *adev) +{ + uint32_t reg_val; + uint32_t reg_addr; + uint32_t field_val; + size_t i; + uint32_t fv2; + size_t lost_sheep; + + DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n"); + + lost_sheep = 0; + for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) { + reg_addr = ecc_umclocalcap_addrs[i]; + DRM_DEBUG("ecc: " + "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n", + i, reg_addr); + reg_val = RREG32(reg_addr); + field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap, + EccDis); + DRM_DEBUG("ecc: " + "reg_val: 0x%08x, " + "EccDis: 0x%08x, ", + reg_val, field_val); + if (field_val) { + DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n"); + ++lost_sheep; + } + } + + for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) { + reg_addr = ecc_umcch_umc_config_addrs[i]; + DRM_DEBUG("ecc: " + "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x", + i, reg_addr); + reg_val = RREG32(reg_addr); + field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG, + DramReady); + DRM_DEBUG("ecc: " + "reg_val: 0x%08x, " + "DramReady: 0x%08x\n", + reg_val, field_val); + + if (!field_val) { + DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n"); + ++lost_sheep; + } + } + + for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) { + reg_addr = ecc_umcch_eccctrl_addrs[i]; + DRM_DEBUG("ecc: " + "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ", + i, reg_addr); + reg_val = RREG32(reg_addr); + field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, + WrEccEn); + fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl, + RdEccEn); + DRM_DEBUG("ecc: " + "reg_val: 0x%08x, " + "WrEccEn: 0x%08x, " + "RdEccEn: 0x%08x\n", + reg_val, field_val, fv2); + + if (!field_val) { + DRM_DEBUG("ecc: WrEccEn is not set\n"); + ++lost_sheep; + } + if (!fv2) { + DRM_DEBUG("ecc: RdEccEn is not set\n"); + ++lost_sheep; + } + } + + DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep); + return lost_sheep == 0; +} + static int gmc_v9_0_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -403,6 +598,7 @@ static int gmc_v9_0_late_init(void *handle) */ unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; unsigned i; + int r; for(i = 0; i < adev->num_rings; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -418,6 +614,16 @@ static int gmc_v9_0_late_init(void *handle) for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) BUG_ON(vm_inv_eng[i] > 16); + r = gmc_v9_0_ecc_available(adev); + if (r == 1) { + DRM_INFO("ECC is active.\n"); + } else if (r == 0) { + DRM_INFO("ECC is not present.\n"); + } else { + DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r); + return r; + } + return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); } @@ -449,6 +655,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) { u32 tmp; int chansize, numchan; + int r; adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); if (!adev->mc.vram_width) { @@ -491,17 +698,22 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) adev->mc.vram_width = numchan * chansize; } - /* Could aper size report 0 ? */ - adev->mc.aper_base = pci_resource_start(adev->pdev, 0); - adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* size in MB on si */ adev->mc.mc_vram_size = ((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) : nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL; adev->mc.real_vram_size = adev->mc.mc_vram_size; - adev->mc.visible_vram_size = adev->mc.aper_size; + + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_device_resize_fb_bar(adev); + if (r) + return r; + } + adev->mc.aper_base = pci_resource_start(adev->pdev, 0); + adev->mc.aper_size = pci_resource_len(adev->pdev, 0); /* In case the PCI BAR is larger than the actual amount of vram */ + adev->mc.visible_vram_size = adev->mc.aper_size; if (adev->mc.visible_vram_size > adev->mc.real_vram_size) adev->mc.visible_vram_size = adev->mc.real_vram_size; @@ -557,16 +769,11 @@ static int gmc_v9_0_sw_init(void *handle) switch (adev->asic_type) { case CHIP_RAVEN: adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; - if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { - adev->vm_manager.vm_size = 1U << 18; - adev->vm_manager.block_size = 9; - adev->vm_manager.num_level = 3; - amdgpu_vm_set_fragment_size(adev, 9); - } else { + if (adev->rev_id == 0x0 || adev->rev_id == 0x1) + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); + else /* vm_size is 64GB for legacy 2-level page support */ - amdgpu_vm_adjust_size(adev, 64, 9); - adev->vm_manager.num_level = 1; - } + amdgpu_vm_adjust_size(adev, 64, 9, 1, 48); break; case CHIP_VEGA10: /* XXX Don't know how to get VRAM type yet. */ @@ -576,20 +783,12 @@ static int gmc_v9_0_sw_init(void *handle) * vm size is 256TB (48bit), maximum size of Vega10, * block size 512 (9bit) */ - adev->vm_manager.vm_size = 1U << 18; - adev->vm_manager.block_size = 9; - adev->vm_manager.num_level = 3; - amdgpu_vm_set_fragment_size(adev, 9); + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); break; default: break; } - DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n", - adev->vm_manager.vm_size, - adev->vm_manager.block_size, - adev->vm_manager.fragment_size); - /* This interrupt is VMC page fault.*/ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, &adev->mc.vm_fault); @@ -599,8 +798,6 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; - /* Set the internal MC address mask * This is the max address of the GPU's * internal address space. @@ -660,7 +857,7 @@ static int gmc_v9_0_sw_init(void *handle) } /** - * gmc_v8_0_gart_fini - vm fini callback + * gmc_v9_0_gart_fini - vm fini callback * * @adev: amdgpu_device pointer * @@ -676,9 +873,9 @@ static int gmc_v9_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); gmc_v9_0_gart_fini(adev); - amdgpu_gem_force_release(adev); amdgpu_bo_fini(adev); return 0; @@ -690,15 +887,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_mmhub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0)); + ARRAY_SIZE(golden_settings_mmhub_1_0_0)); amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); + ARRAY_SIZE(golden_settings_athub_1_0_0)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); + ARRAY_SIZE(golden_settings_athub_1_0_0)); break; default: break; @@ -718,7 +915,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) amdgpu_program_register_sequence(adev, golden_settings_vega10_hdp, - (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); + ARRAY_SIZE(golden_settings_vega10_hdp)); if (adev->gart.robj == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index cc21c4bdec27..bd160d8700e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -23,14 +23,13 @@ #include "amdgpu.h" #include "mmhub_v1_0.h" -#include "vega10/soc15ip.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" -#include "vega10/MMHUB/mmhub_1_0_default.h" -#include "vega10/ATHUB/athub_1_0_offset.h" -#include "vega10/ATHUB/athub_1_0_sh_mask.h" -#include "vega10/ATHUB/athub_1_0_default.h" -#include "vega10/vega10_enum.h" +#include "soc15ip.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" +#include "mmhub/mmhub_1_0_default.h" +#include "athub/athub_1_0_offset.h" +#include "athub/athub_1_0_sh_mask.h" +#include "vega10_enum.h" #include "soc15_common.h" diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c index b4906d2f30d3..ad9054e3903c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c @@ -22,11 +22,11 @@ */ #include "amdgpu.h" -#include "vega10/soc15ip.h" -#include "vega10/NBIO/nbio_6_1_offset.h" -#include "vega10/NBIO/nbio_6_1_sh_mask.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" +#include "soc15ip.h" +#include "nbio/nbio_6_1_offset.h" +#include "nbio/nbio_6_1_sh_mask.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" #include "soc15.h" #include "vega10_ih.h" #include "soc15_common.h" @@ -254,7 +254,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_sriov_gpu_reset(adev, NULL); + amdgpu_gpu_recover(adev, NULL); } static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ -282,9 +282,17 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, /* see what event we get */ r = xgpu_ai_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION); - /* only handle FLR_NOTIFY now */ - if (!r) - schedule_work(&adev->virt.flr_work); + /* sometimes the interrupt is delayed to inject to VM, so under such case + * the IDH_FLR_NOTIFICATION is overwritten by VF FLR from GIM side, thus + * above recieve message could be failed, we should schedule the flr_work + * anyway + */ + if (r) { + DRM_ERROR("FLR_NOTIFICATION is missed\n"); + xgpu_ai_mailbox_send_ack(adev); + } + + schedule_work(&adev->virt.flr_work); } return 0; @@ -353,5 +361,6 @@ const struct amdgpu_virt_ops xgpu_ai_virt_ops = { .req_full_gpu = xgpu_ai_request_full_gpu_access, .rel_full_gpu = xgpu_ai_release_full_gpu_access, .reset_gpu = xgpu_ai_request_reset, + .wait_reset = NULL, .trans_msg = xgpu_ai_mailbox_trans_msg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c index c25a831f94ec..df52824c0cd4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c @@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, xgpu_fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, xgpu_fiji_golden_settings_a10, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_golden_settings_a10)); amdgpu_program_register_sequence(adev, xgpu_fiji_golden_common_all, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_fiji_golden_common_all)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, xgpu_tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, xgpu_tonga_golden_settings_a11, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_golden_settings_a11)); amdgpu_program_register_sequence(adev, xgpu_tonga_golden_common_all, - (const u32)ARRAY_SIZE( + ARRAY_SIZE( xgpu_tonga_golden_common_all)); break; default: @@ -446,8 +446,10 @@ static int xgpu_vi_send_access_requests(struct amdgpu_device *adev, request == IDH_REQ_GPU_FINI_ACCESS || request == IDH_REQ_GPU_RESET_ACCESS) { r = xgpu_vi_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); - if (r) - pr_err("Doesn't get ack from pf, continue\n"); + if (r) { + pr_err("Doesn't get ack from pf, give up\n"); + return r; + } } return 0; @@ -458,6 +460,11 @@ static int xgpu_vi_request_reset(struct amdgpu_device *adev) return xgpu_vi_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); } +static int xgpu_vi_wait_reset_cmpl(struct amdgpu_device *adev) +{ + return xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL); +} + static int xgpu_vi_request_full_gpu_access(struct amdgpu_device *adev, bool init) { @@ -514,7 +521,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) } /* Trigger recovery due to world switch failure */ - amdgpu_sriov_gpu_reset(adev, NULL); + amdgpu_gpu_recover(adev, NULL); } static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev, @@ -613,5 +620,6 @@ const struct amdgpu_virt_ops xgpu_vi_virt_ops = { .req_full_gpu = xgpu_vi_request_full_gpu_access, .rel_full_gpu = xgpu_vi_release_full_gpu_access, .reset_gpu = xgpu_vi_request_reset, + .wait_reset = xgpu_vi_wait_reset_cmpl, .trans_msg = NULL, /* Does not need to trans VF errors to host. */ }; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 904a1bab9b9f..76db711097c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -24,11 +24,11 @@ #include "amdgpu_atombios.h" #include "nbio_v6_1.h" -#include "vega10/soc15ip.h" -#include "vega10/NBIO/nbio_6_1_default.h" -#include "vega10/NBIO/nbio_6_1_offset.h" -#include "vega10/NBIO/nbio_6_1_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "soc15ip.h" +#include "nbio/nbio_6_1_default.h" +#include "nbio/nbio_6_1_offset.h" +#include "nbio/nbio_6_1_sh_mask.h" +#include "vega10_enum.h" #define smnCPM_CONTROL 0x11180460 #define smnPCIE_CNTL2 0x11180070 diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index f802b973410a..1fb77174e02c 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -24,11 +24,11 @@ #include "amdgpu_atombios.h" #include "nbio_v7_0.h" -#include "vega10/soc15ip.h" -#include "raven1/NBIO/nbio_7_0_default.h" -#include "raven1/NBIO/nbio_7_0_offset.h" -#include "raven1/NBIO/nbio_7_0_sh_mask.h" -#include "vega10/vega10_enum.h" +#include "soc15ip.h" +#include "nbio/nbio_7_0_default.h" +#include "nbio/nbio_7_0_offset.h" +#include "nbio/nbio_7_0_sh_mask.h" +#include "vega10_enum.h" #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 4e20d91d5d50..78fe3f2917a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -30,10 +30,10 @@ #include "soc15_common.h" #include "psp_v10_0.h" -#include "vega10/soc15ip.h" -#include "raven1/MP/mp_10_0_offset.h" -#include "raven1/GC/gc_9_1_offset.h" -#include "raven1/SDMA0/sdma0_4_1_offset.h" +#include "soc15ip.h" +#include "mp/mp_10_0_offset.h" +#include "gc/gc_9_1_offset.h" +#include "sdma0/sdma0_4_1_offset.h" MODULE_FIRMWARE("amdgpu/raven_asd.bin"); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index c7bcfe8e286c..e75a23d858ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -31,12 +31,12 @@ #include "soc15_common.h" #include "psp_v3_1.h" -#include "vega10/soc15ip.h" -#include "vega10/MP/mp_9_0_offset.h" -#include "vega10/MP/mp_9_0_sh_mask.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/SDMA0/sdma0_4_0_offset.h" -#include "vega10/NBIO/nbio_6_1_offset.h" +#include "soc15ip.h" +#include "mp/mp_9_0_offset.h" +#include "mp/mp_9_0_sh_mask.h" +#include "gc/gc_9_0_offset.h" +#include "sdma0/sdma0_4_0_offset.h" +#include "nbio/nbio_6_1_offset.h" MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 67f375bfe452..121e628e7cdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, - (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); + ARRAY_SIZE(golden_settings_iceland_a11)); break; default: break; @@ -633,7 +633,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -704,7 +704,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 6d06f8eb659f..c8c93f9dac21 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, - (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); + ARRAY_SIZE(golden_settings_fiji_a10)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, - (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); + ARRAY_SIZE(golden_settings_tonga_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); + ARRAY_SIZE(golden_settings_polaris11_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); + ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; default: break; @@ -893,7 +893,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -964,7 +964,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 46009db3d195..4c55f21e37a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -27,15 +27,15 @@ #include "amdgpu_ucode.h" #include "amdgpu_trace.h" -#include "vega10/soc15ip.h" -#include "vega10/SDMA0/sdma0_4_0_offset.h" -#include "vega10/SDMA0/sdma0_4_0_sh_mask.h" -#include "vega10/SDMA1/sdma1_4_0_offset.h" -#include "vega10/SDMA1/sdma1_4_0_sh_mask.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "raven1/SDMA0/sdma0_4_1_default.h" +#include "soc15ip.h" +#include "sdma0/sdma0_4_0_offset.h" +#include "sdma0/sdma0_4_0_sh_mask.h" +#include "sdma1/sdma1_4_0_offset.h" +#include "sdma1/sdma1_4_0_sh_mask.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" +#include "hdp/hdp_4_0_offset.h" +#include "sdma0/sdma0_4_1_default.h" #include "soc15_common.h" #include "soc15.h" @@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, golden_settings_sdma_4, - (const u32)ARRAY_SIZE(golden_settings_sdma_4)); + ARRAY_SIZE(golden_settings_sdma_4)); amdgpu_program_register_sequence(adev, golden_settings_sdma_vg10, - (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); + ARRAY_SIZE(golden_settings_sdma_vg10)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_sdma_4_1, - (const u32)ARRAY_SIZE(golden_settings_sdma_4_1)); + ARRAY_SIZE(golden_settings_sdma_4_1)); amdgpu_program_register_sequence(adev, golden_settings_sdma_rv1, - (const u32)ARRAY_SIZE(golden_settings_sdma_rv1)); + ARRAY_SIZE(golden_settings_sdma_rv1)); break; default: break; @@ -919,7 +919,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -990,7 +990,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 8284d5dbfc30..49eef3090f08 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev) case CHIP_TAHITI: amdgpu_program_register_sequence(adev, tahiti_golden_registers, - (const u32)ARRAY_SIZE(tahiti_golden_registers)); + ARRAY_SIZE(tahiti_golden_registers)); amdgpu_program_register_sequence(adev, tahiti_golden_rlc_registers, - (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers)); + ARRAY_SIZE(tahiti_golden_rlc_registers)); amdgpu_program_register_sequence(adev, tahiti_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init)); + ARRAY_SIZE(tahiti_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, tahiti_golden_registers2, - (const u32)ARRAY_SIZE(tahiti_golden_registers2)); + ARRAY_SIZE(tahiti_golden_registers2)); break; case CHIP_PITCAIRN: amdgpu_program_register_sequence(adev, pitcairn_golden_registers, - (const u32)ARRAY_SIZE(pitcairn_golden_registers)); + ARRAY_SIZE(pitcairn_golden_registers)); amdgpu_program_register_sequence(adev, pitcairn_golden_rlc_registers, - (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers)); + ARRAY_SIZE(pitcairn_golden_rlc_registers)); amdgpu_program_register_sequence(adev, pitcairn_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); + ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); break; case CHIP_VERDE: amdgpu_program_register_sequence(adev, verde_golden_registers, - (const u32)ARRAY_SIZE(verde_golden_registers)); + ARRAY_SIZE(verde_golden_registers)); amdgpu_program_register_sequence(adev, verde_golden_rlc_registers, - (const u32)ARRAY_SIZE(verde_golden_rlc_registers)); + ARRAY_SIZE(verde_golden_rlc_registers)); amdgpu_program_register_sequence(adev, verde_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init)); + ARRAY_SIZE(verde_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, verde_pg_init, - (const u32)ARRAY_SIZE(verde_pg_init)); + ARRAY_SIZE(verde_pg_init)); break; case CHIP_OLAND: amdgpu_program_register_sequence(adev, oland_golden_registers, - (const u32)ARRAY_SIZE(oland_golden_registers)); + ARRAY_SIZE(oland_golden_registers)); amdgpu_program_register_sequence(adev, oland_golden_rlc_registers, - (const u32)ARRAY_SIZE(oland_golden_rlc_registers)); + ARRAY_SIZE(oland_golden_rlc_registers)); amdgpu_program_register_sequence(adev, oland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); + ARRAY_SIZE(oland_mgcg_cgcg_init)); break; case CHIP_HAINAN: amdgpu_program_register_sequence(adev, hainan_golden_registers, - (const u32)ARRAY_SIZE(hainan_golden_registers)); + ARRAY_SIZE(hainan_golden_registers)); amdgpu_program_register_sequence(adev, hainan_golden_registers2, - (const u32)ARRAY_SIZE(hainan_golden_registers2)); + ARRAY_SIZE(hainan_golden_registers2)); amdgpu_program_register_sequence(adev, hainan_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init)); + ARRAY_SIZE(hainan_mgcg_cgcg_init)); break; diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 3fa2fbf8c9a1..ee469a906cd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -252,7 +252,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", ring->idx, tmp); @@ -317,7 +317,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) } tmp = le32_to_cpu(adev->wb.wb[index]); if (tmp == 0xDEADBEEF) { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } else { DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c index 51fd0c9a20a5..299cb3161b2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -5845,9 +5845,9 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); j++; + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) return -EINVAL; - temp_reg = RREG32(MC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; @@ -5859,18 +5859,16 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) table->mc_reg_table_entry[k].mc_data[j] = (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; } break; case MC_SEQ_RESERVE_M: @@ -5882,8 +5880,6 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); j++; - if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) - return -EINVAL; break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4e67fe1e7955..f134ca0c093c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -34,18 +34,18 @@ #include "atom.h" #include "amd_pcie.h" -#include "vega10/soc15ip.h" -#include "vega10/UVD/uvd_7_0_offset.h" -#include "vega10/GC/gc_9_0_offset.h" -#include "vega10/GC/gc_9_0_sh_mask.h" -#include "vega10/SDMA0/sdma0_4_0_offset.h" -#include "vega10/SDMA1/sdma1_4_0_offset.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "vega10/HDP/hdp_4_0_sh_mask.h" -#include "vega10/MP/mp_9_0_offset.h" -#include "vega10/MP/mp_9_0_sh_mask.h" -#include "vega10/SMUIO/smuio_9_0_offset.h" -#include "vega10/SMUIO/smuio_9_0_sh_mask.h" +#include "soc15ip.h" +#include "uvd/uvd_7_0_offset.h" +#include "gc/gc_9_0_offset.h" +#include "gc/gc_9_0_sh_mask.h" +#include "sdma0/sdma0_4_0_offset.h" +#include "sdma1/sdma1_4_0_offset.h" +#include "hdp/hdp_4_0_offset.h" +#include "hdp/hdp_4_0_sh_mask.h" +#include "mp/mp_9_0_offset.h" +#include "mp/mp_9_0_sh_mask.h" +#include "smuio/smuio_9_0_offset.h" +#include "smuio/smuio_9_0_sh_mask.h" #include "soc15.h" #include "soc15_common.h" @@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev) case CHIP_VEGA10: amdgpu_program_register_sequence(adev, vega10_golden_init, - (const u32)ARRAY_SIZE(vega10_golden_init)); + ARRAY_SIZE(vega10_golden_init)); break; case CHIP_RAVEN: amdgpu_program_register_sequence(adev, raven_golden_init, - (const u32)ARRAY_SIZE(raven_golden_init)); + ARRAY_SIZE(raven_golden_init)); break; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 8ab0f78794a5..b13ae34be1c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -521,7 +521,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", @@ -563,7 +563,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) /* programm the VCPU memory controller bits 0-27 */ addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; + size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3; WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index bb6d46e168a3..a4b0f1d842b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -258,7 +258,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) upper_32_bits(adev->uvd.gpu_addr)); offset = AMDGPU_UVD_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + size = AMDGPU_UVD_FIRMWARE_SIZE(adev); WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); @@ -536,7 +536,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 920910ac8663..0e8b887cf03e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -184,7 +184,7 @@ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -360,7 +360,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: @@ -416,7 +416,7 @@ static int uvd_v6_0_sw_init(void *handle) ring = &adev->uvd.ring_enc[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up UVD ENC run queue.\n"); return r; @@ -603,7 +603,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) upper_32_bits(adev->uvd.gpu_addr)); offset = AMDGPU_UVD_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + size = AMDGPU_UVD_FIRMWARE_SIZE(adev); WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); WREG32(mmUVD_VCPU_CACHE_SIZE0, size); @@ -1008,7 +1008,7 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 6634545060fd..660fa41dc877 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -29,16 +29,16 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "vega10/soc15ip.h" -#include "vega10/UVD/uvd_7_0_offset.h" -#include "vega10/UVD/uvd_7_0_sh_mask.h" -#include "vega10/VCE/vce_4_0_offset.h" -#include "vega10/VCE/vce_4_0_default.h" -#include "vega10/VCE/vce_4_0_sh_mask.h" -#include "vega10/NBIF/nbif_6_1_offset.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "soc15ip.h" +#include "uvd/uvd_7_0_offset.h" +#include "uvd/uvd_7_0_sh_mask.h" +#include "vce/vce_4_0_offset.h" +#include "vce/vce_4_0_default.h" +#include "vce/vce_4_0_sh_mask.h" +#include "nbif/nbif_6_1_offset.h" +#include "hdp/hdp_4_0_offset.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); @@ -184,7 +184,7 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed\n", @@ -359,7 +359,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) } else if (r < 0) { DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); } else { - DRM_INFO("ib test on ring %d succeeded\n", ring->idx); + DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); r = 0; } error: @@ -418,7 +418,7 @@ static int uvd_v7_0_sw_init(void *handle) ring = &adev->uvd.ring_enc[0]; rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL]; r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, - rq, amdgpu_sched_jobs); + rq, amdgpu_sched_jobs, NULL); if (r) { DRM_ERROR("Failed setting up UVD ENC run queue.\n"); return r; @@ -616,7 +616,7 @@ static int uvd_v7_0_resume(void *handle) */ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) { - uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); + uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); uint32_t offset; if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { @@ -1192,7 +1192,7 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) } if (i < adev->usec_timeout) { - DRM_INFO("ring test on %d succeeded in %d usecs\n", + DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); } else { DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 75745544600a..f2f713650074 100644..100755 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -32,12 +32,12 @@ #include "soc15_common.h" #include "mmsch_v1_0.h" -#include "vega10/soc15ip.h" -#include "vega10/VCE/vce_4_0_offset.h" -#include "vega10/VCE/vce_4_0_default.h" -#include "vega10/VCE/vce_4_0_sh_mask.h" -#include "vega10/MMHUB/mmhub_1_0_offset.h" -#include "vega10/MMHUB/mmhub_1_0_sh_mask.h" +#include "soc15ip.h" +#include "vce/vce_4_0_offset.h" +#include "vce/vce_4_0_default.h" +#include "vce/vce_4_0_sh_mask.h" +#include "mmhub/mmhub_1_0_offset.h" +#include "mmhub/mmhub_1_0_sh_mask.h" #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 @@ -243,37 +243,49 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), - adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff); } else { - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), adev->vce.gpu_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), + (adev->vce.gpu_addr >> 40) & 0xff); + } + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), adev->vce.gpu_addr >> 8); - MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), + (adev->vce.gpu_addr >> 40) & 0xff); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), adev->vce.gpu_addr >> 8); - } + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, + mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), + (adev->vce.gpu_addr >> 40) & 0xff); offset = AMDGPU_VCE_FIRMWARE_OFFSET; size = VCE_V4_0_FW_SIZE; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), - offset & 0x7FFFFFFF); + offset & ~0x0f000000); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); - offset += size; + offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0; size = VCE_V4_0_STACK_SIZE; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), - offset & 0x7FFFFFFF); + (offset & ~0x0f000000) | (1 << 24)); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); offset += size; size = VCE_V4_0_DATA_SIZE; MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), - offset & 0x7FFFFFFF); + (offset & ~0x0f000000) | (2 << 24)); MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 0450ac5ba6b6..e4673f792545 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -28,12 +28,12 @@ #include "soc15d.h" #include "soc15_common.h" -#include "vega10/soc15ip.h" -#include "raven1/VCN/vcn_1_0_offset.h" -#include "raven1/VCN/vcn_1_0_sh_mask.h" -#include "vega10/HDP/hdp_4_0_offset.h" -#include "raven1/MMHUB/mmhub_9_1_offset.h" -#include "raven1/MMHUB/mmhub_9_1_sh_mask.h" +#include "soc15ip.h" +#include "vcn/vcn_1_0_offset.h" +#include "vcn/vcn_1_0_sh_mask.h" +#include "hdp/hdp_4_0_offset.h" +#include "mmhub/mmhub_9_1_offset.h" +#include "mmhub/mmhub_9_1_sh_mask.h" static int vcn_v1_0_start(struct amdgpu_device *adev); static int vcn_v1_0_stop(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 697325737ba8..ca778cd4e6e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -26,9 +26,9 @@ #include "soc15.h" -#include "vega10/soc15ip.h" -#include "vega10/OSSSYS/osssys_4_0_offset.h" -#include "vega10/OSSSYS/osssys_4_0_sh_mask.h" +#include "soc15ip.h" +#include "oss/osssys_4_0_offset.h" +#include "oss/osssys_4_0_sh_mask.h" #include "soc15_common.h" #include "vega10_ih.h" @@ -46,11 +46,11 @@ static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev); */ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) { - u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); adev->irq.ih.enabled = true; } @@ -63,14 +63,14 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev) */ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev) { - u32 ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); /* set rptr, wptr to 0 */ - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); adev->irq.ih.enabled = false; adev->irq.ih.rptr = 0; } @@ -102,15 +102,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) else nbio_v6_1_ih_control(adev); - ih_rb_cntl = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); + ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ if (adev->irq.ih.use_bus_addr) { - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.rb_dma_addr >> 8); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); } else { - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE), adev->irq.ih.gpu_addr >> 8); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI), (adev->irq.ih.gpu_addr >> 40) & 0xff); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff); ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); } rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); @@ -126,21 +126,21 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) if (adev->irq.msi_enabled) ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), ih_rb_cntl); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); /* set the writeback address whether it's enabled or not */ if (adev->irq.ih.use_bus_addr) wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); else wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO), lower_32_bits(wptr_off)); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI), upper_32_bits(wptr_off) & 0xFF); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); /* set rptr, wptr to 0 */ - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), 0); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR), 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); - ih_doorbell_rtpr = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR)); + ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); if (adev->irq.ih.use_doorbell) { ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, OFFSET, adev->irq.ih.doorbell_index); @@ -150,20 +150,20 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, ENABLE, 0); } - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR), ih_doorbell_rtpr); + WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); if (adev->flags & AMD_IS_APU) nbio_v7_0_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); else nbio_v6_1_ih_doorbell_range(adev, adev->irq.ih.use_doorbell, adev->irq.ih.doorbell_index); - tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL)); + tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, CLIENT18_IS_STORM_CLIENT, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL), tmp); + WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); - tmp = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL)); + tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_INT_FLOOD_CNTL), tmp); + WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); pci_set_master(adev->pdev); @@ -367,7 +367,7 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev) adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); } else { - WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR), adev->irq.ih.rptr); + WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr); } } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 3a4c2fa7e36d..bb8ca9489546 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); + ARRAY_SIZE(iceland_mgcg_cgcg_init)); break; case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); + ARRAY_SIZE(fiji_mgcg_cgcg_init)); break; case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); + ARRAY_SIZE(tonga_mgcg_cgcg_init)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; case CHIP_POLARIS11: case CHIP_POLARIS10: diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c324c3b76fac..ccbf10e3bbb6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -59,9 +59,9 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "ivsrcid/irqsrcs_dcn_1_0.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" +#include "soc15ip.h" #include "soc15_common.h" #endif @@ -792,7 +792,7 @@ dm_atomic_state_alloc_free(struct drm_atomic_state *state) static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, - .output_poll_changed = amdgpu_output_poll_changed, + .output_poll_changed = drm_fb_helper_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = amdgpu_dm_atomic_commit, .atomic_state_alloc = dm_atomic_state_alloc, @@ -1590,7 +1590,6 @@ static int dm_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; adev->ddev->driver->driver_features |= DRIVER_ATOMIC; - amdgpu_dm_set_irq_funcs(adev); switch (adev->asic_type) { case CHIP_BONAIRE: @@ -1664,6 +1663,8 @@ static int dm_early_init(void *handle) return -EINVAL; } + amdgpu_dm_set_irq_funcs(adev); + if (adev->mode_info.funcs == NULL) adev->mode_info.funcs = &dm_display_funcs; @@ -1679,18 +1680,6 @@ static int dm_early_init(void *handle) return 0; } -struct dm_connector_state { - struct drm_connector_state base; - - enum amdgpu_rmx_type scaling; - uint8_t underscan_vborder; - uint8_t underscan_hborder; - bool underscan_enable; -}; - -#define to_dm_connector_state(x)\ - container_of((x), struct dm_connector_state, base) - static bool modeset_required(struct drm_crtc_state *crtc_state, struct dc_stream_state *new_stream, struct dc_stream_state *old_stream) @@ -1773,8 +1762,7 @@ static bool fill_rects_from_plane_state(const struct drm_plane_state *state, return true; } static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, - uint64_t *tiling_flags, - uint64_t *fb_location) + uint64_t *tiling_flags) { struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); int r = amdgpu_bo_reserve(rbo, false); @@ -1786,9 +1774,6 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, return r; } - if (fb_location) - *fb_location = amdgpu_bo_gpu_offset(rbo); - if (tiling_flags) amdgpu_bo_get_tiling_flags(rbo, tiling_flags); @@ -1799,12 +1784,9 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, struct dc_plane_state *plane_state, - const struct amdgpu_framebuffer *amdgpu_fb, - bool addReq) + const struct amdgpu_framebuffer *amdgpu_fb) { uint64_t tiling_flags; - uint64_t fb_location = 0; - uint64_t chroma_addr = 0; unsigned int awidth; const struct drm_framebuffer *fb = &amdgpu_fb->base; int ret = 0; @@ -1812,8 +1794,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, ret = get_fb_info( amdgpu_fb, - &tiling_flags, - addReq == true ? &fb_location:NULL); + &tiling_flags); if (ret) return ret; @@ -1851,8 +1832,6 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; - plane_state->address.grph.addr.low_part = lower_32_bits(fb_location); - plane_state->address.grph.addr.high_part = upper_32_bits(fb_location); plane_state->plane_size.grph.surface_size.x = 0; plane_state->plane_size.grph.surface_size.y = 0; plane_state->plane_size.grph.surface_size.width = fb->width; @@ -1865,15 +1844,6 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, } else { awidth = ALIGN(fb->width, 64); plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - plane_state->address.video_progressive.luma_addr.low_part - = lower_32_bits(fb_location); - plane_state->address.video_progressive.luma_addr.high_part - = upper_32_bits(fb_location); - chroma_addr = fb_location + (u64)(awidth * fb->height); - plane_state->address.video_progressive.chroma_addr.low_part - = lower_32_bits(chroma_addr); - plane_state->address.video_progressive.chroma_addr.high_part - = upper_32_bits(chroma_addr); plane_state->plane_size.video.luma_size.x = 0; plane_state->plane_size.video.luma_size.y = 0; plane_state->plane_size.video.luma_size.width = awidth; @@ -1983,8 +1953,7 @@ static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state, static int fill_plane_attributes(struct amdgpu_device *adev, struct dc_plane_state *dc_plane_state, struct drm_plane_state *plane_state, - struct drm_crtc_state *crtc_state, - bool addrReq) + struct drm_crtc_state *crtc_state) { const struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(plane_state->fb); @@ -1998,8 +1967,7 @@ static int fill_plane_attributes(struct amdgpu_device *adev, ret = fill_plane_attributes_from_fb( crtc->dev->dev_private, dc_plane_state, - amdgpu_fb, - addrReq); + amdgpu_fb); if (ret) return ret; @@ -2174,6 +2142,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, const struct drm_connector *connector) { struct dc_crtc_timing *timing_out = &stream->timing; + struct dc_transfer_func *tf = dc_create_transfer_func(); memset(timing_out, 0, sizeof(struct dc_crtc_timing)); @@ -2217,13 +2186,9 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, stream->output_color_space = get_output_color_space(timing_out); - { - struct dc_transfer_func *tf = dc_create_transfer_func(); - - tf->type = TF_TYPE_PREDEFINED; - tf->tf = TRANSFER_FUNCTION_SRGB; - stream->out_transfer_func = tf; - } + tf->type = TF_TYPE_PREDEFINED; + tf->tf = TRANSFER_FUNCTION_SRGB; + stream->out_transfer_func = tf; } static void fill_audio_info(struct audio_info *audio_info, @@ -2330,6 +2295,56 @@ static int create_fake_sink(struct amdgpu_dm_connector *aconnector) return 0; } +static void set_multisync_trigger_params( + struct dc_stream_state *stream) +{ + if (stream->triggered_crtc_reset.enabled) { + stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING; + stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE; + } +} + +static void set_master_stream(struct dc_stream_state *stream_set[], + int stream_count) +{ + int j, highest_rfr = 0, master_stream = 0; + + for (j = 0; j < stream_count; j++) { + if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { + int refresh_rate = 0; + + refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/ + (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); + if (refresh_rate > highest_rfr) { + highest_rfr = refresh_rate; + master_stream = j; + } + } + } + for (j = 0; j < stream_count; j++) { + if (stream_set[j] && j != master_stream) + stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; + } +} + +static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) +{ + int i = 0; + + if (context->stream_count < 2) + return; + for (i = 0; i < context->stream_count ; i++) { + if (!context->streams[i]) + continue; + /* TODO: add a function to read AMD VSDB bits and will set + * crtc_sync_master.multi_sync_enabled flag + * For now its set to false + */ + set_multisync_trigger_params(context->streams[i]); + } + set_master_stream(context->streams, context->stream_count); +} + static struct dc_stream_state * create_stream_for_sink(struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, @@ -2986,7 +3001,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, = lower_32_bits(afb->address); plane_state->address.video_progressive.luma_addr.high_part = upper_32_bits(afb->address); - chroma_addr = afb->address + (u64)(awidth * new_state->fb->height); + chroma_addr = afb->address + (u64)awidth * new_state->fb->height; plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(chroma_addr); plane_state->address.video_progressive.chroma_addr.high_part @@ -3994,6 +4009,19 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } } +/** + * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC + * @crtc_state: the DRM CRTC state + * @stream_state: the DC stream state. + * + * Copy the mirrored transient state flags from DRM, to DC. It is used to bring + * a dc_stream_state's flags in sync with a drm_crtc_state's flags. + */ +static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state, + struct dc_stream_state *stream_state) +{ + stream_state->mode_changed = crtc_state->mode_changed; +} static int amdgpu_dm_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, @@ -4033,11 +4061,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_display_manager *dm = &adev->dm; struct dm_atomic_state *dm_state; uint32_t i, j; - uint32_t new_crtcs_count = 0; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; - struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - struct dc_stream_state *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -4067,6 +4092,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) new_crtc_state->active_changed, new_crtc_state->connectors_changed); + /* Copy all transient state flags into dc state */ + if (dm_new_crtc_state->stream) { + amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base, + dm_new_crtc_state->stream); + } + /* handles headless hotplug case, updating new_state and * aconnector as needed */ @@ -4096,25 +4127,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) continue; } - if (dm_old_crtc_state->stream) remove_stream(adev, acrtc, dm_old_crtc_state->stream); - - /* - * this loop saves set mode crtcs - * we needed to enable vblanks once all - * resources acquired in dc after dc_commit_streams - */ - - /*TODO move all this into dm_crtc_state, get rid of - * new_crtcs array and use old and new atomic states - * instead - */ - new_crtcs[new_crtcs_count] = acrtc; - new_crtcs_count++; - - new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); acrtc->enabled = true; acrtc->hw_mode = new_crtc_state->mode; crtc->hwmode = new_crtc_state->mode; @@ -4132,31 +4147,61 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) * are removed from freesync module */ if (adev->dm.freesync_module) { - for (i = 0; i < new_crtcs_count; i++) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { struct amdgpu_dm_connector *aconnector = NULL; + struct dm_connector_state *dm_new_con_state = NULL; + struct amdgpu_crtc *acrtc = NULL; + bool modeset_needed; - new_crtc_state = drm_atomic_get_new_crtc_state(state, - &new_crtcs[i]->base); dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + modeset_needed = modeset_required( + new_crtc_state, + dm_new_crtc_state->stream, + dm_old_crtc_state->stream); + /* We add stream to freesync if: + * 1. Said stream is not null, and + * 2. A modeset is requested. This means that the + * stream was removed previously, and needs to be + * replaced. + */ + if (dm_new_crtc_state->stream == NULL || + !modeset_needed) + continue; - new_stream = dm_new_crtc_state->stream; - aconnector = amdgpu_dm_find_first_crtc_matching_connector( - state, - &new_crtcs[i]->base); + acrtc = to_amdgpu_crtc(crtc); + + aconnector = + amdgpu_dm_find_first_crtc_matching_connector( + state, crtc); if (!aconnector) { - DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d " - "skipping freesync init\n", - new_crtcs[i]->crtc_id); + DRM_DEBUG_DRIVER("Atomic commit: Failed to " + "find connector for acrtc " + "id:%d skipping freesync " + "init\n", + acrtc->crtc_id); continue; } mod_freesync_add_stream(adev->dm.freesync_module, - new_stream, &aconnector->caps); + dm_new_crtc_state->stream, + &aconnector->caps); + new_con_state = drm_atomic_get_new_connector_state( + state, &aconnector->base); + dm_new_con_state = to_dm_connector_state(new_con_state); + + mod_freesync_set_user_enable(adev->dm.freesync_module, + &dm_new_crtc_state->stream, + 1, + &dm_new_con_state->user_enable); } } - if (dm_state->context) + if (dm_state->context) { + dm_enable_per_frame_crtc_master_sync(dm_state->context); WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); + } for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); @@ -4214,18 +4259,28 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) dm_error("%s: Failed to update stream scaling!\n", __func__); } - for (i = 0; i < new_crtcs_count; i++) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { /* * loop to enable interrupts on newly arrived crtc */ - struct amdgpu_crtc *acrtc = new_crtcs[i]; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + bool modeset_needed; - new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + modeset_needed = modeset_required( + new_crtc_state, + dm_new_crtc_state->stream, + dm_old_crtc_state->stream); + + if (dm_new_crtc_state->stream == NULL || !modeset_needed) + continue; if (adev->dm.freesync_module) mod_freesync_notify_mode_change( - adev->dm.freesync_module, &dm_new_crtc_state->stream, 1); + adev->dm.freesync_module, + &dm_new_crtc_state->stream, 1); manage_dm_interrupts(adev, acrtc, true); } @@ -4527,6 +4582,7 @@ static int dm_update_crtcs_state(struct dc *dc, WARN_ON(dm_new_crtc_state->stream); dm_new_crtc_state->stream = new_stream; + dc_stream_retain(new_stream); DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", @@ -4652,8 +4708,7 @@ static int dm_update_planes_state(struct dc *dc, new_plane_crtc->dev->dev_private, dm_new_plane_state->dc_state, new_plane_state, - new_crtc_state, - false); + new_crtc_state); if (ret) return ret; @@ -4668,6 +4723,11 @@ static int dm_update_planes_state(struct dc *dc, return ret; } + /* Tell DC to do a full surface update every time there + * is a plane change. Inefficient, but works for now. + */ + dm_new_plane_state->dc_state->update_flags.bits.full_update = 1; + *lock_and_validation_needed = true; } } @@ -4679,8 +4739,6 @@ static int dm_update_planes_state(struct dc *dc, static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { - int i; - int ret; struct amdgpu_device *adev = dev->dev_private; struct dc *dc = adev->dm.dc; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); @@ -4688,6 +4746,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_state *old_con_state, *new_con_state; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; + int ret, i; /* * This bool will be set for true for any modeset/reset @@ -4699,37 +4758,21 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - /* - * legacy_cursor_update should be made false for SoC's having - * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(), - * otherwise for software cursor plane, - * we should not add it to list of affected planes. - */ - if (state->legacy_cursor_update) { - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { - if (new_crtc_state->color_mgmt_changed) { - ret = drm_atomic_add_affected_planes(state, crtc); - if (ret) - goto fail; - } - } - } else { - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && - !new_crtc_state->color_mgmt_changed) - continue; + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && + !new_crtc_state->color_mgmt_changed) + continue; - if (!new_crtc_state->enable) - continue; + if (!new_crtc_state->enable) + continue; - ret = drm_atomic_add_affected_connectors(state, crtc); - if (ret) - return ret; + ret = drm_atomic_add_affected_connectors(state, crtc); + if (ret) + return ret; - ret = drm_atomic_add_affected_planes(state, crtc); - if (ret) - goto fail; - } + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret) + goto fail; } dm_state->context = dc_create_state(); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 117521c6a6ed..8a1e4f5dbd64 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -220,6 +220,18 @@ struct dm_atomic_state { #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) +struct dm_connector_state { + struct drm_connector_state base; + + enum amdgpu_rmx_type scaling; + uint8_t underscan_vborder; + uint8_t underscan_hborder; + bool underscan_enable; + struct mod_freesync_user_enable user_enable; +}; + +#define to_dm_connector_state(x)\ + container_of((x), struct dm_connector_state, base) void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); struct drm_connector_state * diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index ca5d0d1581dc..1874b6cee6af 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -683,13 +683,16 @@ static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = { void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev) { - adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; + if (adev->mode_info.num_crtc > 0) + adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; + else + adev->crtc_irq.num_types = 0; adev->crtc_irq.funcs = &dm_crtc_irq_funcs; - adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; + adev->pageflip_irq.num_types = adev->mode_info.num_crtc; adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs; - adev->hpd_irq.num_types = AMDGPU_HPD_LAST; + adev->hpd_irq.num_types = adev->mode_info.num_hpd; adev->hpd_irq.funcs = &dm_hpd_irq_funcs; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 5df8fd5b537c..56e549249134 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -41,6 +41,10 @@ unsigned long long dm_get_timestamp(struct dc_context *ctx) return 0; } +void dm_perf_trace_timestamp(const char *func_name, unsigned int line) +{ +} + bool dm_write_persistent_data(struct dc_context *ctx, const struct dc_sink *sink, const char *module_name, @@ -131,11 +135,12 @@ bool dm_pp_apply_display_requirements( adev->pm.pm_display_cfg.min_bus_bandwidth = 0; /* TODO: complete implementation of - * amd_powerplay_display_configuration_change(). + * pp_display_configuration_change(). * Follow example of: * PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c * PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */ - amd_powerplay_display_configuration_change( + if (adev->powerplay.pp_funcs->display_configuration_change) + adev->powerplay.pp_funcs->display_configuration_change( adev->powerplay.pp_handle, &adev->pm.pm_display_cfg); @@ -264,22 +269,26 @@ bool dm_pp_get_clock_levels_by_type( struct amd_pp_simple_clock_info validation_clks = { 0 }; uint32_t i; - if (amd_powerplay_get_clock_by_type(pp_handle, + if (adev->powerplay.pp_funcs->get_clock_by_type) { + if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle, dc_to_pp_clock_type(clk_type), &pp_clks)) { /* Error in pplib. Provide default values. */ - get_default_clock_levels(clk_type, dc_clks); - return true; + get_default_clock_levels(clk_type, dc_clks); + return true; + } } pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); - if (amd_powerplay_get_display_mode_validation_clocks(pp_handle, - &validation_clks)) { - /* Error in pplib. Provide default values. */ - DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); - validation_clks.engine_max_clock = 72000; - validation_clks.memory_max_clock = 80000; - validation_clks.level = 0; + if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) { + if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks( + pp_handle, &validation_clks)) { + /* Error in pplib. Provide default values. */ + DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n"); + validation_clks.engine_max_clock = 72000; + validation_clks.memory_max_clock = 80000; + validation_clks.level = 0; + } } DRM_INFO("DM_PPLIB: Validation clocks:\n"); diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c index 6e43168fbdd6..854678a0c54b 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c @@ -83,15 +83,11 @@ void dc_conn_log(struct dc_context *ctx, link->link_index); va_start(args, msg); - entry.buf_offset += dm_log_to_buffer( - &entry.buf[entry.buf_offset], - LOG_MAX_LINE_SIZE - entry.buf_offset, - msg, args); + dm_logger_append_va(&entry, msg, args); - if (entry.buf[strlen(entry.buf) - 1] == '\n') { - entry.buf[strlen(entry.buf) - 1] = '\0'; + if (entry.buf_offset > 0 && + entry.buf[entry.buf_offset - 1] == '\n') entry.buf_offset--; - } if (hex_data) for (i = 0; i < hex_data_count; i++) diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index e04e8ecd4874..180a9d69d351 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -70,9 +70,8 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; - logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char), - GFP_KERNEL); - + logger->log_buffer = kcalloc(logger->log_buffer_size, sizeof(char), + GFP_KERNEL); if (!logger->log_buffer) return false; @@ -313,6 +312,18 @@ void dm_logger_append( const char *msg, ...) { + va_list args; + + va_start(args, msg); + dm_logger_append_va(entry, msg, args); + va_end(args); +} + +void dm_logger_append_va( + struct log_entry *entry, + const char *msg, + va_list args) +{ struct dal_logger *logger; if (!entry) { @@ -326,11 +337,8 @@ void dm_logger_append( dal_logger_should_log(logger, entry->type)) { uint32_t size; - va_list args; char buffer[LOG_MAX_LINE_SIZE]; - va_start(args, msg); - size = dm_log_to_buffer( buffer, LOG_MAX_LINE_SIZE, msg, args); @@ -339,8 +347,6 @@ void dm_logger_append( } else { append_entry(entry, "LOG_ERROR, line too long\n", 27); } - - va_end(args); } } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 3dce35e66b09..a4fbca34bcdf 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -432,25 +432,13 @@ static void dcn_bw_calc_rq_dlg_ttu( input.clks_cfg.dcfclk_mhz = v->dcfclk; input.clks_cfg.dispclk_mhz = v->dispclk; input.clks_cfg.dppclk_mhz = v->dppclk; - input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000; + input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0; input.clks_cfg.socclk_mhz = v->socclk; input.clks_cfg.voltage = v->voltage_level; // dc->dml.logger = pool->base.logger; input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444; input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp; //input[in_idx].dout.output_standard; - switch (v->output_deep_color[in_idx]) { - case dcn_bw_encoder_12bpc: - input.dout.output_bpc = dm_out_12; - break; - case dcn_bw_encoder_10bpc: - input.dout.output_bpc = dm_out_10; - break; - case dcn_bw_encoder_8bpc: - default: - input.dout.output_bpc = dm_out_8; - break; - } /*todo: soc->sr_enter_plus_exit_time??*/ dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep; @@ -1025,6 +1013,8 @@ bool dcn_validate_bandwidth( if (pipe->plane_state) { struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; + pipe->plane_state->update_flags.bits.full_update = 1; + if (v->dpp_per_plane[input_idx] == 2 || ((pipe->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || @@ -1064,6 +1054,9 @@ bool dcn_validate_bandwidth( hsplit_pipe->stream = NULL; hsplit_pipe->top_pipe = NULL; hsplit_pipe->bottom_pipe = NULL; + /* Clear plane_res and stream_res */ + memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); + memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); resource_build_scaling_params(pipe); } /* for now important to do this after pipe split for building e2e params */ @@ -1231,40 +1224,62 @@ unsigned int dcn_find_dcfclk_suits_all( return dcf_clk; } +static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) +{ + int i; + + if (clks->num_levels == 0) + return false; + + for (i = 0; i < clks->num_levels; i++) + /* Ensure that the result is sane */ + if (clks->data[i].clocks_in_khz == 0) + return false; + + return true; +} + void dcn_bw_update_from_pplib(struct dc *dc) { struct dc_context *ctx = dc->ctx; - struct dm_pp_clock_levels_with_voltage clks = {0}; + struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; + bool res; kernel_fpu_begin(); /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */ - - if (dm_pp_get_clock_levels_by_type_with_voltage( - ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) && - clks.num_levels != 0) { - ASSERT(clks.num_levels >= 3); - dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0; - if (clks.num_levels > 2) { - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; - } else { - dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; - } + res = dm_pp_get_clock_levels_by_type_with_voltage( + ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); + + if (res) + res = verify_clock_values(&fclks); + + if (res) { + ASSERT(fclks.num_levels >= 3); + dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0; + dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * + (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0) + * ddr4_dram_factor_single_Channel / 1000.0; dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; + (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0) + * ddr4_dram_factor_single_Channel / 1000.0; dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels * - (clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; + (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0) + * ddr4_dram_factor_single_Channel / 1000.0; } else BREAK_TO_DEBUGGER(); - if (dm_pp_get_clock_levels_by_type_with_voltage( - ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) && - clks.num_levels >= 3) { - dc->dcn_soc->dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_mid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_nom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0; - dc->dcn_soc->dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0; + + res = dm_pp_get_clock_levels_by_type_with_voltage( + ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); + + if (res) + res = verify_clock_values(&dcfclks); + + if (res && dcfclks.num_levels >= 3) { + dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; + dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0; } else BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7240db2e6f09..d1488d5ee028 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -54,6 +54,13 @@ /******************************************************************************* * Private functions ******************************************************************************/ + +static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) +{ + if (new > *original) + *original = new; +} + static void destroy_links(struct dc *dc) { uint32_t i; @@ -157,7 +164,7 @@ failed_alloc: return false; } -static bool stream_adjust_vmin_vmax(struct dc *dc, +bool dc_stream_adjust_vmin_vmax(struct dc *dc, struct dc_stream_state **streams, int num_streams, int vmin, int vmax) { @@ -182,7 +189,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, return ret; } -static bool stream_get_crtc_position(struct dc *dc, +bool dc_stream_get_crtc_position(struct dc *dc, struct dc_stream_state **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { @@ -207,45 +214,7 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) -{ - int i = 0; - bool ret = false; - struct pipe_ctx *pipes; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_state->res_ctx.pipe_ctx[i]; - dc->hwss.program_gamut_remap(pipes); - ret = true; - } - } - - return ret; -} - -static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) -{ - int i = 0; - bool ret = false; - struct pipe_ctx *pipes; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream - == stream) { - - pipes = &dc->current_state->res_ctx.pipe_ctx[i]; - dc->hwss.program_csc_matrix(pipes, - stream->output_color_space, - stream->csc_color_matrix.matrix); - ret = true; - } - } - - return ret; -} - -static void set_static_screen_events(struct dc *dc, +void dc_stream_set_static_screen_events(struct dc *dc, struct dc_stream_state **streams, int num_streams, const struct dc_static_screen_events *events) @@ -270,177 +239,6 @@ static void set_static_screen_events(struct dc *dc, dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events); } -static void set_drive_settings(struct dc *dc, - struct link_training_settings *lt_settings, - const struct dc_link *link) -{ - - int i; - - for (i = 0; i < dc->link_count; i++) { - if (dc->links[i] == link) - break; - } - - if (i >= dc->link_count) - ASSERT_CRITICAL(false); - - dc_link_dp_set_drive_settings(dc->links[i], lt_settings); -} - -static void perform_link_training(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern) -{ - int i; - - for (i = 0; i < dc->link_count; i++) - dc_link_dp_perform_link_training( - dc->links[i], - link_setting, - skip_video_pattern); -} - -static void set_preferred_link_settings(struct dc *dc, - struct dc_link_settings *link_setting, - struct dc_link *link) -{ - link->preferred_link_setting = *link_setting; - dp_retrain_link_dp_test(link, link_setting, false); -} - -static void enable_hpd(const struct dc_link *link) -{ - dc_link_dp_enable_hpd(link); -} - -static void disable_hpd(const struct dc_link *link) -{ - dc_link_dp_disable_hpd(link); -} - - -static void set_test_pattern( - struct dc_link *link, - enum dp_test_pattern test_pattern, - const struct link_training_settings *p_link_settings, - const unsigned char *p_custom_pattern, - unsigned int cust_pattern_size) -{ - if (link != NULL) - dc_link_dp_set_test_pattern( - link, - test_pattern, - p_link_settings, - p_custom_pattern, - cust_pattern_size); -} - -static void set_dither_option(struct dc_stream_state *stream, - enum dc_dither_option option) -{ - struct bit_depth_reduction_params params; - struct dc_link *link = stream->status.link; - struct pipe_ctx *pipes = NULL; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == - stream) { - pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; - break; - } - } - - memset(¶ms, 0, sizeof(params)); - if (!pipes) - return; - if (option > DITHER_OPTION_MAX) - return; - - stream->dither_option = option; - - resource_build_bit_depth_reduction_params(stream, - ¶ms); - stream->bit_depth_params = params; - pipes->stream_res.opp->funcs-> - opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); -} - -void set_dpms( - struct dc *dc, - struct dc_stream_state *stream, - bool dpms_off) -{ - struct pipe_ctx *pipe_ctx = NULL; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - break; - } - } - - if (!pipe_ctx) { - ASSERT(0); - return; - } - - if (stream->dpms_off != dpms_off) { - stream->dpms_off = dpms_off; - if (dpms_off) - core_link_disable_stream(pipe_ctx, - KEEP_ACQUIRED_RESOURCE); - else - core_link_enable_stream(dc->current_state, pipe_ctx); - } -} - -static void allocate_dc_stream_funcs(struct dc *dc) -{ - if (dc->hwss.set_drr != NULL) { - dc->stream_funcs.adjust_vmin_vmax = - stream_adjust_vmin_vmax; - } - - dc->stream_funcs.set_static_screen_events = - set_static_screen_events; - - dc->stream_funcs.get_crtc_position = - stream_get_crtc_position; - - dc->stream_funcs.set_gamut_remap = - set_gamut_remap; - - dc->stream_funcs.program_csc_matrix = - program_csc_matrix; - - dc->stream_funcs.set_dither_option = - set_dither_option; - - dc->stream_funcs.set_dpms = - set_dpms; - - dc->link_funcs.set_drive_settings = - set_drive_settings; - - dc->link_funcs.perform_link_training = - perform_link_training; - - dc->link_funcs.set_preferred_link_settings = - set_preferred_link_settings; - - dc->link_funcs.enable_hpd = - enable_hpd; - - dc->link_funcs.disable_hpd = - disable_hpd; - - dc->link_funcs.set_test_pattern = - set_test_pattern; -} - static void destruct(struct dc *dc) { dc_release_state(dc->current_state); @@ -558,6 +356,7 @@ static bool construct(struct dc *dc, dc_version = resource_parse_asic_id(init_params->asic_id); dc->ctx->dce_version = dc_version; + #if defined(CONFIG_DRM_AMD_DC_FBC) dc->ctx->fbc_gpu_addr = init_params->fbc_gpu_addr; #endif @@ -616,8 +415,6 @@ static bool construct(struct dc *dc, if (!create_links(dc, init_params->num_virtual_links)) goto fail; - allocate_dc_stream_funcs(dc); - return true; fail: @@ -686,6 +483,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) dc->caps.max_links = dc->link_count; dc->caps.max_audios = dc->res_pool->audio_count; + dc->caps.linear_pitch_alignment = 64; dc->config = init_params->flags; @@ -712,6 +510,28 @@ void dc_destroy(struct dc **dc) *dc = NULL; } +static void enable_timing_multisync( + struct dc *dc, + struct dc_state *ctx) +{ + int i = 0, multisync_count = 0; + int pipe_count = dc->res_pool->pipe_count; + struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL }; + + for (i = 0; i < pipe_count; i++) { + if (!ctx->res_ctx.pipe_ctx[i].stream || + !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) + continue; + multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i]; + multisync_count++; + } + + if (multisync_count > 1) { + dc->hwss.enable_per_frame_crtc_position_reset( + dc, multisync_count, multisync_pipes); + } +} + static void program_timing_sync( struct dc *dc, struct dc_state *ctx) @@ -838,7 +658,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; - int i, j, k, l; + int i, k, l; struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; disable_dangling_plane(dc, context); @@ -849,9 +669,44 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c if (!dcb->funcs->is_accelerated_mode(dcb)) dc->hwss.enable_accelerated_mode(dc); + /* re-program planes for existing stream, in case we need to + * free up plane resource for later use + */ + for (i = 0; i < context->stream_count; i++) { + if (context->streams[i]->mode_changed) + continue; + + dc->hwss.apply_ctx_for_surface( + dc, context->streams[i], + context->stream_status[i].plane_count, + context); /* use new pipe config in new context */ + } + + /* Program hardware */ + dc->hwss.ready_shared_resources(dc, context); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); + } + + result = dc->hwss.apply_ctx_to_hw(dc, context); + + if (result != DC_OK) + return result; + + if (context->stream_count > 1) { + enable_timing_multisync(dc, context); + program_timing_sync(dc, context); + } + + /* Program all planes within new context*/ for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; + if (!context->streams[i]->mode_changed) + continue; + dc->hwss.apply_ctx_for_surface( dc, context->streams[i], context->stream_status[i].plane_count, @@ -880,27 +735,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c context->streams[i]->timing.pix_clk_khz); } - dc->hwss.ready_shared_resources(dc, context); - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - pipe = &context->res_ctx.pipe_ctx[i]; - dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); - } - result = dc->hwss.apply_ctx_to_hw(dc, context); - - program_timing_sync(dc, context); - dc_enable_stereo(dc, context, dc_streams, context->stream_count); - for (i = 0; i < context->stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - pipe = &context->res_ctx.pipe_ctx[j]; - - if (!pipe->top_pipe && pipe->stream == context->streams[i]) - dc->hwss.pipe_control_lock(dc, pipe, false); - } - } - dc_release_state(dc->current_state); dc->current_state = context; @@ -936,7 +772,6 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) return (result == DC_OK); } - bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; @@ -945,9 +780,11 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) post_surface_trace(dc); for (i = 0; i < dc->res_pool->pipe_count; i++) - if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].plane_state == NULL) - dc->hwss.power_down_front_end(dc, i); + if (context->res_ctx.pipe_ctx[i].stream == NULL || + context->res_ctx.pipe_ctx[i].plane_state == NULL) { + context->res_ctx.pipe_ctx[i].pipe_idx = i; + dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); + } /* 3rd param should be true, temp w/a for RV*/ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -1014,6 +851,7 @@ bool dc_commit_planes_to_stream( flip_addr[i].address = plane_states[i]->address; flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; plane_info[i].color_space = plane_states[i]->color_space; + plane_info[i].input_tf = plane_states[i]->input_tf; plane_info[i].format = plane_states[i]->format; plane_info[i].plane_size = plane_states[i]->plane_size; plane_info[i].rotation = plane_states[i]->rotation; @@ -1118,79 +956,91 @@ static unsigned int pixel_format_to_bpp(enum surface_pixel_format format) } } -static enum surface_update_type get_plane_info_update_type( - const struct dc_surface_update *u, - int surface_index) +static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) { - struct dc_plane_info temp_plane_info; - memset(&temp_plane_info, 0, sizeof(temp_plane_info)); + union surface_update_flags *update_flags = &u->surface->update_flags; if (!u->plane_info) return UPDATE_TYPE_FAST; - temp_plane_info = *u->plane_info; + if (u->plane_info->color_space != u->surface->color_space) + update_flags->bits.color_space_change = 1; - /* Copy all parameters that will cause a full update - * from current surface, the rest of the parameters - * from provided plane configuration. - * Perform memory compare and special validation - * for those that can cause fast/medium updates - */ + if (u->plane_info->input_tf != u->surface->input_tf) + update_flags->bits.input_tf_change = 1; - /* Full update parameters */ - temp_plane_info.color_space = u->surface->color_space; - temp_plane_info.dcc = u->surface->dcc; - temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror; - temp_plane_info.plane_size = u->surface->plane_size; - temp_plane_info.rotation = u->surface->rotation; - temp_plane_info.stereo_format = u->surface->stereo_format; - - if (surface_index == 0) - temp_plane_info.visible = u->plane_info->visible; - else - temp_plane_info.visible = u->surface->visible; - - if (memcmp(u->plane_info, &temp_plane_info, - sizeof(struct dc_plane_info)) != 0) - return UPDATE_TYPE_FULL; + if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) + update_flags->bits.horizontal_mirror_change = 1; + + if (u->plane_info->rotation != u->surface->rotation) + update_flags->bits.rotation_change = 1; + + if (u->plane_info->stereo_format != u->surface->stereo_format) + update_flags->bits.stereo_format_change = 1; + + if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) + update_flags->bits.per_pixel_alpha_change = 1; if (pixel_format_to_bpp(u->plane_info->format) != - pixel_format_to_bpp(u->surface->format)) { + pixel_format_to_bpp(u->surface->format)) /* different bytes per element will require full bandwidth * and DML calculation */ - return UPDATE_TYPE_FULL; - } + update_flags->bits.bpp_change = 1; if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, sizeof(union dc_tiling_info)) != 0) { + update_flags->bits.swizzle_change = 1; /* todo: below are HW dependent, we should add a hook to * DCE/N resource and validated there. */ - if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { + if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) /* swizzled mode requires RQ to be setup properly, * thus need to run DML to calculate RQ settings */ - return UPDATE_TYPE_FULL; - } + update_flags->bits.bandwidth_change = 1; } + if (update_flags->bits.rotation_change + || update_flags->bits.stereo_format_change + || update_flags->bits.bpp_change + || update_flags->bits.bandwidth_change) + return UPDATE_TYPE_FULL; + return UPDATE_TYPE_MED; } -static enum surface_update_type get_scaling_info_update_type( +static enum surface_update_type get_scaling_info_update_type( const struct dc_surface_update *u) { + union surface_update_flags *update_flags = &u->surface->update_flags; + if (!u->scaling_info) return UPDATE_TYPE_FAST; - if (u->scaling_info->src_rect.width != u->surface->src_rect.width - || u->scaling_info->src_rect.height != u->surface->src_rect.height - || u->scaling_info->clip_rect.width != u->surface->clip_rect.width + if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width || u->scaling_info->clip_rect.height != u->surface->clip_rect.height || u->scaling_info->dst_rect.width != u->surface->dst_rect.width - || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) - return UPDATE_TYPE_FULL; + || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) { + update_flags->bits.scaling_change = 1; + + if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width + || u->scaling_info->dst_rect.height < u->surface->dst_rect.height) + && (u->scaling_info->dst_rect.width < u->surface->src_rect.width + || u->scaling_info->dst_rect.height < u->surface->src_rect.height)) + /* Making dst rect smaller requires a bandwidth change */ + update_flags->bits.bandwidth_change = 1; + } + + if (u->scaling_info->src_rect.width != u->surface->src_rect.width + || u->scaling_info->src_rect.height != u->surface->src_rect.height) { + + update_flags->bits.scaling_change = 1; + if (u->scaling_info->src_rect.width > u->surface->src_rect.width + && u->scaling_info->src_rect.height > u->surface->src_rect.height) + /* Making src rect bigger requires a bandwidth change */ + update_flags->bits.clock_change = 1; + } if (u->scaling_info->src_rect.x != u->surface->src_rect.x || u->scaling_info->src_rect.y != u->surface->src_rect.y @@ -1198,41 +1048,56 @@ static enum surface_update_type get_scaling_info_update_type( || u->scaling_info->clip_rect.y != u->surface->clip_rect.y || u->scaling_info->dst_rect.x != u->surface->dst_rect.x || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) + update_flags->bits.position_change = 1; + + if (update_flags->bits.clock_change + || update_flags->bits.bandwidth_change) + return UPDATE_TYPE_FULL; + + if (update_flags->bits.scaling_change + || update_flags->bits.position_change) return UPDATE_TYPE_MED; return UPDATE_TYPE_FAST; } -static enum surface_update_type det_surface_update( - const struct dc *dc, - const struct dc_surface_update *u, - int surface_index) +static enum surface_update_type det_surface_update(const struct dc *dc, + const struct dc_surface_update *u) { const struct dc_state *context = dc->current_state; - enum surface_update_type type = UPDATE_TYPE_FAST; + enum surface_update_type type; enum surface_update_type overall_type = UPDATE_TYPE_FAST; + union surface_update_flags *update_flags = &u->surface->update_flags; + + update_flags->raw = 0; // Reset all flags - if (!is_surface_in_context(context, u->surface)) + if (!is_surface_in_context(context, u->surface)) { + update_flags->bits.new_plane = 1; return UPDATE_TYPE_FULL; + } - type = get_plane_info_update_type(u, surface_index); - if (overall_type < type) - overall_type = type; + type = get_plane_info_update_type(u); + elevate_update_type(&overall_type, type); type = get_scaling_info_update_type(u); - if (overall_type < type) - overall_type = type; + elevate_update_type(&overall_type, type); + + if (u->in_transfer_func) + update_flags->bits.in_transfer_func = 1; - if (u->in_transfer_func || - u->hdr_static_metadata) { - if (overall_type < UPDATE_TYPE_MED) - overall_type = UPDATE_TYPE_MED; + if (u->input_csc_color_matrix) + update_flags->bits.input_csc_change = 1; + + if (update_flags->bits.in_transfer_func + || update_flags->bits.input_csc_change) { + type = UPDATE_TYPE_MED; + elevate_update_type(&overall_type, type); } return overall_type; } -enum surface_update_type dc_check_update_surfaces_for_stream( +static enum surface_update_type check_update_surfaces_for_stream( struct dc *dc, struct dc_surface_update *updates, int surface_count, @@ -1250,18 +1115,38 @@ enum surface_update_type dc_check_update_surfaces_for_stream( for (i = 0 ; i < surface_count; i++) { enum surface_update_type type = - det_surface_update(dc, &updates[i], i); + det_surface_update(dc, &updates[i]); if (type == UPDATE_TYPE_FULL) return type; - if (overall_type < type) - overall_type = type; + elevate_update_type(&overall_type, type); } return overall_type; } +enum surface_update_type dc_check_update_surfaces_for_stream( + struct dc *dc, + struct dc_surface_update *updates, + int surface_count, + struct dc_stream_update *stream_update, + const struct dc_stream_status *stream_status) +{ + int i; + enum surface_update_type type; + + for (i = 0; i < surface_count; i++) + updates[i].surface->update_flags.raw = 0; + + type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); + if (type == UPDATE_TYPE_FULL) + for (i = 0; i < surface_count; i++) + updates[i].surface->update_flags.bits.full_update = 1; + + return type; +} + static struct dc_stream_status *stream_get_status( struct dc_state *ctx, struct dc_stream_state *stream) @@ -1293,9 +1178,7 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FULL) { dc->hwss.set_bandwidth(dc, context, false); context_clock_trace(dc, context); - } - if (update_type > UPDATE_TYPE_FAST) { for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1312,103 +1195,58 @@ static void commit_planes_for_stream(struct dc *dc, return; } - /* Lock pipes for provided surfaces, or all active if full update*/ - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *plane_state = srf_updates[i].surface; - - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) - continue; - if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) - continue; - - dc->hwss.pipe_control_lock( - dc, - pipe_ctx, - true); - } - if (update_type == UPDATE_TYPE_FULL) - break; - } - /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) + if (update_type == UPDATE_TYPE_FAST || !pipe_ctx->plane_state) continue; - if (!pipe_ctx->top_pipe && pipe_ctx->stream) { - struct dc_stream_status *stream_status = stream_get_status(context, pipe_ctx->stream); + if (!pipe_ctx->top_pipe && + pipe_ctx->stream && + pipe_ctx->stream == stream) { + struct dc_stream_status *stream_status = + stream_get_status(context, pipe_ctx->stream); dc->hwss.apply_ctx_for_surface( dc, pipe_ctx->stream, stream_status->plane_count, context); } } - if (update_type > UPDATE_TYPE_FAST) + if (update_type == UPDATE_TYPE_FULL) context_timing_trace(dc, &context->res_ctx); /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; - if (update_type == UPDATE_TYPE_MED) - dc->hwss.apply_ctx_for_surface( - dc, stream, surface_count, context); - for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->plane_state != plane_state) + if (pipe_ctx->stream != stream) continue; - if (srf_updates[i].flip_addr) - dc->hwss.update_plane_addr(dc, pipe_ctx); - - if (update_type == UPDATE_TYPE_FAST) + if (pipe_ctx->plane_state != plane_state) continue; - /* work around to program degamma regs for split pipe after set mode. */ - if (srf_updates[i].in_transfer_func || (pipe_ctx->top_pipe && - pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state)) - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - - if (stream_update != NULL && - stream_update->out_transfer_func != NULL) { - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); - } - - if (srf_updates[i].hdr_static_metadata) { - resource_build_info_frame(pipe_ctx); - dc->hwss.update_info_frame(pipe_ctx); - } + if (update_type == UPDATE_TYPE_FAST && srf_updates[i].flip_addr) + dc->hwss.update_plane_addr(dc, pipe_ctx); } } - /* Unlock pipes */ - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + if (stream && stream_update && update_type > UPDATE_TYPE_FAST) + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - for (j = 0; j < surface_count; j++) { - if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != pipe_ctx->plane_state) + if (pipe_ctx->stream != stream) continue; - if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) - continue; - - dc->hwss.pipe_control_lock( - dc, - pipe_ctx, - false); - break; + if (stream_update->hdr_static_metadata) { + resource_build_info_frame(pipe_ctx); + dc->hwss.update_info_frame(pipe_ctx); + } } - } } void dc_commit_updates_for_stream(struct dc *dc, @@ -1480,10 +1318,7 @@ void dc_commit_updates_for_stream(struct dc *dc, stream_update, update_type, context); - - if (update_type >= UPDATE_TYPE_FULL) - dc_post_update_surfaces_to_stream(dc); - + /*update current_State*/ if (dc->current_state != context) { struct dc_state *old = dc->current_state; @@ -1492,6 +1327,9 @@ void dc_commit_updates_for_stream(struct dc *dc, dc_release_state(old); } + /*let's use current_state to update watermark etc*/ + if (update_type >= UPDATE_TYPE_FULL) + dc_post_update_surfaces_to_stream(dc); return; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 6acee5426e4b..2e509382935f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -137,6 +137,7 @@ void pre_surface_trace( "plane_state->tiling_info.gfx8.pipe_config = %d;\n" "plane_state->tiling_info.gfx8.array_mode = %d;\n" "plane_state->color_space = %d;\n" + "plane_state->input_tf = %d;\n" "plane_state->dcc.enable = %d;\n" "plane_state->format = %d;\n" "plane_state->rotation = %d;\n" @@ -144,6 +145,7 @@ void pre_surface_trace( plane_state->tiling_info.gfx8.pipe_config, plane_state->tiling_info.gfx8.array_mode, plane_state->color_space, + plane_state->input_tf, plane_state->dcc.enable, plane_state->format, plane_state->rotation, @@ -184,6 +186,7 @@ void update_surface_trace( if (update->plane_info) { SURFACE_TRACE( "plane_info->color_space = %d;\n" + "plane_info->input_tf = %d;\n" "plane_info->format = %d;\n" "plane_info->plane_size.grph.surface_pitch = %d;\n" "plane_info->plane_size.grph.surface_size.height = %d;\n" @@ -192,6 +195,7 @@ void update_surface_trace( "plane_info->plane_size.grph.surface_size.y = %d;\n" "plane_info->rotation = %d;\n", update->plane_info->color_space, + update->plane_info->input_tf, update->plane_info->format, update->plane_info->plane_size.grph.surface_pitch, update->plane_info->plane_size.grph.surface_size.height, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index e27ed4a45265..7b0e43c0685c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1798,7 +1798,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) else dp_disable_link_phy_mst(link, signal); } else - link->link_enc->funcs->disable_output(link->link_enc, signal, link); + link->link_enc->funcs->disable_output(link->link_enc, signal); } bool dp_active_dongle_validate_timing( @@ -1869,7 +1869,7 @@ enum dc_status dc_link_validate_mode_timing( const struct dc_crtc_timing *timing) { uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk; - struct dc_dongle_caps *dongle_caps = &link->link_status.dpcd_caps->dongle_caps; + struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps; /* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index e6bf05d76a94..00528b214a9f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -220,8 +220,7 @@ static void dpcd_set_lt_pattern_and_lane_settings( size_in_bytes); dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, - "%s:\n %x VS set = %x PE set = %x \ - max VS Reached = %x max PE Reached = %x\n", + "%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", __func__, DP_TRAINING_LANE0_SET, dpcd_lane[0].bits.VOLTAGE_SWING_SET, @@ -558,8 +557,7 @@ static void dpcd_set_lane_settings( */ dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, - "%s\n %x VS set = %x PE set = %x \ - max VS Reached = %x max PE Reached = %x\n", + "%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n", __func__, DP_TRAINING_LANE0_SET, dpcd_lane[0].bits.VOLTAGE_SWING_SET, @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence( if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) { ASSERT(0); dm_logger_write(link->ctx->logger, LOG_ERROR, - "%s: Link Training Error, could not \ - get CR after %d tries. \ - Possibly voltage swing issue", __func__, + "%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue", + __func__, LINK_TRAINING_MAX_CR_RETRY); } @@ -2127,7 +2124,7 @@ static void get_active_converter_info( union dwnstream_port_caps_byte3_hdmi hdmi_caps = {.raw = det_caps[3] }; - union dwnstream_port_caps_byte1 + union dwnstream_port_caps_byte2 hdmi_color_caps = {.raw = det_caps[2] }; link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk = det_caps[1] * 25000; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 9a33b471270a..f2902569be2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -89,7 +89,7 @@ void dp_enable_link_phy( if (dc_is_dp_sst_signal(signal)) { if (signal == SIGNAL_TYPE_EDP) { - link->dc->hwss.edp_power_control(link->link_enc, true); + link->dc->hwss.edp_power_control(link, true); link_enc->funcs->enable_dp_output( link_enc, link_settings, @@ -140,10 +140,10 @@ void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) if (signal == SIGNAL_TYPE_EDP) { link->dc->hwss.edp_backlight_control(link, false); edp_receiver_ready_T9(link); - link->link_enc->funcs->disable_output(link->link_enc, signal, link); - link->dc->hwss.edp_power_control(link->link_enc, false); + link->link_enc->funcs->disable_output(link->link_enc, signal); + link->dc->hwss.edp_power_control(link, false); } else - link->link_enc->funcs->disable_output(link->link_enc, signal, link); + link->link_enc->funcs->disable_output(link->link_enc, signal); /* Clear current link setting.*/ memset(&link->cur_link_settings, 0, @@ -286,8 +286,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, link->link_enc->funcs->disable_output( link->link_enc, - SIGNAL_TYPE_DISPLAY_PORT, - link); + SIGNAL_TYPE_DISPLAY_PORT); /* Clear current link setting. */ memset(&link->cur_link_settings, 0, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b7422d3b71ef..9c5e879f18b3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -426,15 +426,8 @@ static enum pixel_format convert_pixel_format_to_dalsurface( static void rect_swap_helper(struct rect *rect) { - uint32_t temp = 0; - - temp = rect->height; - rect->height = rect->width; - rect->width = temp; - - temp = rect->x; - rect->x = rect->y; - rect->y = temp; + swap(rect->height, rect->width); + swap(rect->x, rect->y); } static void calculate_viewport(struct pipe_ctx *pipe_ctx) @@ -2319,20 +2312,13 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_plane_state *plane_state, struct dc_stream_state *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; - struct dc_hdr_static_metadata hdr_metadata; uint32_t data; - if (!plane_state) - return; - - hdr_metadata = plane_state->hdr_static_ctx; - - if (!hdr_metadata.hdr_supported) + if (!stream->hdr_static_metadata.hdr_supported) return; if (dc_is_hdmi_signal(signal)) { @@ -2352,55 +2338,55 @@ static void set_hdr_static_info_packet( i = 2; } - data = hdr_metadata.is_hdr; + data = stream->hdr_static_metadata.is_hdr; info_packet->sb[i++] = data ? 0x02 : 0x00; info_packet->sb[i++] = 0x00; - data = hdr_metadata.chromaticity_green_x / 2; + data = stream->hdr_static_metadata.chromaticity_green_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_green_y / 2; + data = stream->hdr_static_metadata.chromaticity_green_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_blue_x / 2; + data = stream->hdr_static_metadata.chromaticity_blue_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_blue_y / 2; + data = stream->hdr_static_metadata.chromaticity_blue_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_red_x / 2; + data = stream->hdr_static_metadata.chromaticity_red_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_red_y / 2; + data = stream->hdr_static_metadata.chromaticity_red_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_white_point_x / 2; + data = stream->hdr_static_metadata.chromaticity_white_point_x / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.chromaticity_white_point_y / 2; + data = stream->hdr_static_metadata.chromaticity_white_point_y / 2; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.max_luminance; + data = stream->hdr_static_metadata.max_luminance; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.min_luminance; + data = stream->hdr_static_metadata.min_luminance; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.maximum_content_light_level; + data = stream->hdr_static_metadata.maximum_content_light_level; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; - data = hdr_metadata.maximum_frame_average_light_level; + data = stream->hdr_static_metadata.maximum_frame_average_light_level; info_packet->sb[i++] = data & 0xFF; info_packet->sb[i++] = (data & 0xFF00) >> 8; @@ -2551,16 +2537,14 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); - set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->plane_state, pipe_ctx->stream); + set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(&info->vsc, pipe_ctx->stream); set_spd_info_packet(&info->spd, pipe_ctx->stream); - set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->plane_state, pipe_ctx->stream); + set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream); } patch_gamut_packet_checksum(&info->gamut); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index e230cc44a0a7..375fb457e223 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -36,16 +36,13 @@ #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 static void update_stream_signal(struct dc_stream_state *stream) { - if (stream->output_signal == SIGNAL_TYPE_NONE) { - struct dc_sink *dc_sink = stream->sink; - if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) - stream->signal = stream->sink->link->connector_signal; - else - stream->signal = dc_sink->sink_signal; - } else { - stream->signal = stream->output_signal; - } + struct dc_sink *dc_sink = stream->sink; + + if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) + stream->signal = stream->sink->link->connector_signal; + else + stream->signal = dc_sink->sink_signal; if (dc_is_dvi_signal(stream->signal)) { if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9d8f4a55c74e..c99ed85ba9a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -38,7 +38,7 @@ #include "inc/compressor.h" #include "dml/display_mode_lib.h" -#define DC_VER "3.1.07" +#define DC_VER "3.1.20" #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -58,8 +58,10 @@ struct dc_caps { uint32_t i2c_speed_in_khz; unsigned int max_cursor_size; unsigned int max_video_width; + int linear_pitch_alignment; bool dcc_const_color; bool dynamic_audio; + bool is_apu; }; struct dc_dcc_surface_param { @@ -97,69 +99,53 @@ struct dc_static_screen_events { bool overlay_update; }; + +/* Surface update type is used by dc_update_surfaces_and_stream + * The update type is determined at the very beginning of the function based + * on parameters passed in and decides how much programming (or updating) is + * going to be done during the call. + * + * UPDATE_TYPE_FAST is used for really fast updates that do not require much + * logical calculations or hardware register programming. This update MUST be + * ISR safe on windows. Currently fast update will only be used to flip surface + * address. + * + * UPDATE_TYPE_MED is used for slower updates which require significant hw + * re-programming however do not affect bandwidth consumption or clock + * requirements. At present, this is the level at which front end updates + * that do not require us to run bw_calcs happen. These are in/out transfer func + * updates, viewport offset changes, recout size changes and pixel depth changes. + * This update can be done at ISR, but we want to minimize how often this happens. + * + * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our + * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front + * end related. Any time viewport dimensions, recout dimensions, scaling ratios or + * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do + * a full update. This cannot be done at ISR level and should be a rare event. + * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting + * underscan we don't expect to see this call at all. + */ + +enum surface_update_type { + UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ + UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ + UPDATE_TYPE_FULL, /* may need to shuffle resources */ +}; + /* Forward declaration*/ struct dc; struct dc_plane_state; struct dc_state; + struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output); }; -struct dc_stream_state_funcs { - bool (*adjust_vmin_vmax)(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - int vmin, - int vmax); - bool (*get_crtc_position)(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - unsigned int *v_pos, - unsigned int *nom_v_pos); - - bool (*set_gamut_remap)(struct dc *dc, - const struct dc_stream_state *stream); - - bool (*program_csc_matrix)(struct dc *dc, - struct dc_stream_state *stream); - - void (*set_static_screen_events)(struct dc *dc, - struct dc_stream_state **stream, - int num_streams, - const struct dc_static_screen_events *events); - - void (*set_dither_option)(struct dc_stream_state *stream, - enum dc_dither_option option); - - void (*set_dpms)(struct dc *dc, - struct dc_stream_state *stream, - bool dpms_off); -}; - struct link_training_settings; -struct dc_link_funcs { - void (*set_drive_settings)(struct dc *dc, - struct link_training_settings *lt_settings, - const struct dc_link *link); - void (*perform_link_training)(struct dc *dc, - struct dc_link_settings *link_setting, - bool skip_video_pattern); - void (*set_preferred_link_settings)(struct dc *dc, - struct dc_link_settings *link_setting, - struct dc_link *link); - void (*enable_hpd)(const struct dc_link *link); - void (*disable_hpd)(const struct dc_link *link); - void (*set_test_pattern)( - struct dc_link *link, - enum dp_test_pattern test_pattern, - const struct link_training_settings *p_link_settings, - const unsigned char *p_custom_pattern, - unsigned int cust_pattern_size); -}; /* Structure to hold configuration flags set by dm at dc creation. */ struct dc_config { @@ -232,8 +218,6 @@ struct dce_hwseq; struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; - struct dc_stream_state_funcs stream_funcs; - struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; @@ -333,24 +317,6 @@ enum color_transfer_func { transfer_func_gamma_26 }; -enum color_color_space { - color_space_unsupported, - color_space_srgb, - color_space_bt601, - color_space_bt709, - color_space_xv_ycc_bt601, - color_space_xv_ycc_bt709, - color_space_xr_rgb, - color_space_bt2020, - color_space_adobe, - color_space_dci_p3, - color_space_sc_rgb_ms_ref, - color_space_display_native, - color_space_app_ctrl, - color_space_dolby_vision, - color_space_custom_coordinates -}; - struct dc_hdr_static_metadata { /* display chromaticities and white point in units of 0.00001 */ unsigned int chromaticity_green_x; @@ -415,6 +381,33 @@ struct dc_plane_status { bool is_right_eye; }; +union surface_update_flags { + + struct { + /* Medium updates */ + uint32_t color_space_change:1; + uint32_t input_tf_change:1; + uint32_t horizontal_mirror_change:1; + uint32_t per_pixel_alpha_change:1; + uint32_t rotation_change:1; + uint32_t swizzle_change:1; + uint32_t scaling_change:1; + uint32_t position_change:1; + uint32_t in_transfer_func:1; + uint32_t input_csc_change:1; + + /* Full updates */ + uint32_t new_plane:1; + uint32_t bpp_change:1; + uint32_t bandwidth_change:1; + uint32_t clock_change:1; + uint32_t stereo_format_change:1; + uint32_t full_update:1; + } bits; + + uint32_t raw; +}; + struct dc_plane_state { struct dc_plane_address address; struct scaling_taps scaling_quality; @@ -426,18 +419,19 @@ struct dc_plane_state { union dc_tiling_info tiling_info; struct dc_plane_dcc_param dcc; - struct dc_hdr_static_metadata hdr_static_ctx; struct dc_gamma *gamma_correction; struct dc_transfer_func *in_transfer_func; + struct dc_bias_and_scale *bias_and_scale; + struct csc_transform input_csc_color_matrix; + struct fixed31_32 coeff_reduction_factor; - // sourceContentAttribute cache - bool is_source_input_valid; - struct dc_hdr_static_metadata source_input_mastering_info; - enum color_color_space source_input_color_space; - enum color_transfer_func source_input_tf; + // TODO: No longer used, remove + struct dc_hdr_static_metadata hdr_static_ctx; enum dc_color_space color_space; + enum color_transfer_func input_tf; + enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; @@ -447,6 +441,7 @@ struct dc_plane_state { bool flip_immediate; bool horizontal_mirror; + union surface_update_flags update_flags; /* private to DC core */ struct dc_plane_status status; struct dc_context *ctx; @@ -463,10 +458,12 @@ struct dc_plane_info { enum surface_pixel_format format; enum dc_rotation_angle rotation; enum plane_stereo_format stereo_format; - enum dc_color_space color_space; /*todo: wrong place, fits in scaling info*/ + enum dc_color_space color_space; + enum color_transfer_func input_tf; bool horizontal_mirror; bool visible; bool per_pixel_alpha; + bool input_csc_enabled; }; struct dc_scaling_info { @@ -483,13 +480,18 @@ struct dc_surface_update { struct dc_flip_addrs *flip_addr; struct dc_plane_info *plane_info; struct dc_scaling_info *scaling_info; + /* following updates require alloc/sleep/spin that is not isr safe, * null means no updates */ /* gamma TO BE REMOVED */ struct dc_gamma *gamma; + enum color_transfer_func color_input_tf; + enum color_transfer_func color_output_tf; struct dc_transfer_func *in_transfer_func; - struct dc_hdr_static_metadata *hdr_static_metadata; + + struct csc_transform *input_csc_color_matrix; + struct fixed31_32 *coeff_reduction_factor; }; /* @@ -524,197 +526,7 @@ struct dc_flip_addrs { bool dc_post_update_surfaces_to_stream( struct dc *dc); -/* Surface update type is used by dc_update_surfaces_and_stream - * The update type is determined at the very beginning of the function based - * on parameters passed in and decides how much programming (or updating) is - * going to be done during the call. - * - * UPDATE_TYPE_FAST is used for really fast updates that do not require much - * logical calculations or hardware register programming. This update MUST be - * ISR safe on windows. Currently fast update will only be used to flip surface - * address. - * - * UPDATE_TYPE_MED is used for slower updates which require significant hw - * re-programming however do not affect bandwidth consumption or clock - * requirements. At present, this is the level at which front end updates - * that do not require us to run bw_calcs happen. These are in/out transfer func - * updates, viewport offset changes, recout size changes and pixel depth changes. - * This update can be done at ISR, but we want to minimize how often this happens. - * - * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our - * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front - * end related. Any time viewport dimensions, recout dimensions, scaling ratios or - * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do - * a full update. This cannot be done at ISR level and should be a rare event. - * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting - * underscan we don't expect to see this call at all. - */ - -enum surface_update_type { - UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ - UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ - UPDATE_TYPE_FULL, /* may need to shuffle resources */ -}; - -/******************************************************************************* - * Stream Interfaces - ******************************************************************************/ - -struct dc_stream_status { - int primary_otg_inst; - int stream_enc_inst; - int plane_count; - struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; - - /* - * link this stream passes through - */ - struct dc_link *link; -}; - -struct dc_stream_state { - struct dc_sink *sink; - struct dc_crtc_timing timing; - - struct rect src; /* composition area */ - struct rect dst; /* stream addressable area */ - - struct audio_info audio_info; - - struct freesync_context freesync_ctx; - - struct dc_transfer_func *out_transfer_func; - struct colorspace_transform gamut_remap_matrix; - struct csc_transform csc_color_matrix; - - enum signal_type output_signal; - - enum dc_color_space output_color_space; - enum dc_dither_option dither_option; - - enum view_3d_format view_format; - - bool ignore_msa_timing_param; - /* TODO: custom INFO packets */ - /* TODO: ABM info (DMCU) */ - /* TODO: PSR info */ - /* TODO: CEA VIC */ - - /* from core_stream struct */ - struct dc_context *ctx; - - /* used by DCP and FMT */ - struct bit_depth_reduction_params bit_depth_params; - struct clamping_and_pixel_encoding_params clamping; - - int phy_pix_clk; - enum signal_type signal; - bool dpms_off; - - struct dc_stream_status status; - - struct dc_cursor_attributes cursor_attributes; - - /* from stream struct */ - struct kref refcount; -}; - -struct dc_stream_update { - struct rect src; - struct rect dst; - struct dc_transfer_func *out_transfer_func; -}; - -bool dc_is_stream_unchanged( - struct dc_stream_state *old_stream, struct dc_stream_state *stream); -bool dc_is_stream_scaling_unchanged( - struct dc_stream_state *old_stream, struct dc_stream_state *stream); - -/* - * Set up surface attributes and associate to a stream - * The surfaces parameter is an absolute set of all surface active for the stream. - * If no surfaces are provided, the stream will be blanked; no memory read. - * Any flip related attribute changes must be done through this interface. - * - * After this call: - * Surfaces attributes are programmed and configured to be composed into stream. - * This does not trigger a flip. No surface address is programmed. - */ - -bool dc_commit_planes_to_stream( - struct dc *dc, - struct dc_plane_state **plane_states, - uint8_t new_plane_count, - struct dc_stream_state *dc_stream, - struct dc_state *state); - -void dc_commit_updates_for_stream(struct dc *dc, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_state *stream, - struct dc_stream_update *stream_update, - struct dc_plane_state **plane_states, - struct dc_state *state); -/* - * Log the current stream state. - */ -void dc_stream_log( - const struct dc_stream_state *stream, - struct dal_logger *dc_logger, - enum dc_log_type log_type); - -uint8_t dc_get_current_stream_count(struct dc *dc); -struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); - -/* - * Return the current frame counter. - */ -uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); - -/* TODO: Return parsed values rather than direct register read - * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) - * being refactored properly to be dce-specific - */ -bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, - uint32_t *v_blank_start, - uint32_t *v_blank_end, - uint32_t *h_position, - uint32_t *v_position); - -enum dc_status dc_add_stream_to_ctx( - struct dc *dc, - struct dc_state *new_ctx, - struct dc_stream_state *stream); - -enum dc_status dc_remove_stream_from_ctx( - struct dc *dc, - struct dc_state *new_ctx, - struct dc_stream_state *stream); - - -bool dc_add_plane_to_context( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_plane_state *plane_state, - struct dc_state *context); - -bool dc_remove_plane_from_context( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_plane_state *plane_state, - struct dc_state *context); - -bool dc_rem_all_planes_for_stream( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_state *context); - -bool dc_add_all_planes_for_stream( - const struct dc *dc, - struct dc_stream_state *stream, - struct dc_plane_state * const *plane_states, - int plane_count, - struct dc_state *context); +#include "dc_stream.h" /* * Structure to store surface/stream associations for validation @@ -725,22 +537,12 @@ struct dc_validation_set { uint8_t plane_count; }; -enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); - enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); enum dc_status dc_validate_global_state( struct dc *dc, struct dc_state *new_ctx); -/* - * This function takes a stream and checks if it is guaranteed to be supported. - * Guaranteed means that MAX_COFUNC similar streams are supported. - * - * After this call: - * No hardware is programmed for call. Only validation is done. - */ - void dc_resource_state_construct( const struct dc *dc, @@ -767,42 +569,6 @@ void dc_resource_state_destruct(struct dc_state *context); */ bool dc_commit_state(struct dc *dc, struct dc_state *context); -/* - * Set up streams and links associated to drive sinks - * The streams parameter is an absolute set of all active streams. - * - * After this call: - * Phy, Encoder, Timing Generator are programmed and enabled. - * New streams are enabled with blank stream; no memory read. - */ -/* - * Enable stereo when commit_streams is not required, - * for example, frame alternate. - */ -bool dc_enable_stereo( - struct dc *dc, - struct dc_state *context, - struct dc_stream_state *streams[], - uint8_t stream_count); - -/** - * Create a new default stream for the requested sink - */ -struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); - -void dc_stream_retain(struct dc_stream_state *dc_stream); -void dc_stream_release(struct dc_stream_state *dc_stream); - -struct dc_stream_status *dc_stream_get_status( - struct dc_stream_state *dc_stream); - -enum surface_update_type dc_check_update_surfaces_for_stream( - struct dc *dc, - struct dc_surface_update *updates, - int surface_count, - struct dc_stream_update *stream_update, - const struct dc_stream_status *stream_status); - struct dc_state *dc_create_state(void); void dc_retain_state(struct dc_state *context); @@ -835,171 +601,7 @@ struct dpcd_caps { bool dpcd_display_control_capable; }; -struct dc_link_status { - struct dpcd_caps *dpcd_caps; -}; - -/* DP MST stream allocation (payload bandwidth number) */ -struct link_mst_stream_allocation { - /* DIG front */ - const struct stream_encoder *stream_enc; - /* associate DRM payload table with DC stream encoder */ - uint8_t vcp_id; - /* number of slots required for the DP stream in transport packet */ - uint8_t slot_count; -}; - -/* DP MST stream allocation table */ -struct link_mst_stream_allocation_table { - /* number of DP video streams */ - int stream_count; - /* array of stream allocations */ - struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; -}; - -/* - * A link contains one or more sinks and their connected status. - * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. - */ -struct dc_link { - struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; - unsigned int sink_count; - struct dc_sink *local_sink; - unsigned int link_index; - enum dc_connection_type type; - enum signal_type connector_signal; - enum dc_irq_source irq_source_hpd; - enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ - /* caps is the same as reported_link_cap. link_traing use - * reported_link_cap. Will clean up. TODO - */ - struct dc_link_settings reported_link_cap; - struct dc_link_settings verified_link_cap; - struct dc_link_settings cur_link_settings; - struct dc_lane_settings cur_lane_setting; - struct dc_link_settings preferred_link_setting; - - uint8_t ddc_hw_inst; - - uint8_t hpd_src; - - uint8_t link_enc_hw_inst; - - bool test_pattern_enabled; - union compliance_test_state compliance_test_state; - - void *priv; - - struct ddc_service *ddc; - - bool aux_mode; - - /* Private to DC core */ - - const struct dc *dc; - - struct dc_context *ctx; - - struct link_encoder *link_enc; - struct graphics_object_id link_id; - union ddi_channel_mapping ddi_channel_mapping; - struct connector_device_tag_info device_tag; - struct dpcd_caps dpcd_caps; - unsigned short chip_caps; - unsigned int dpcd_sink_count; - enum edp_revision edp_revision; - bool psr_enabled; - - /* MST record stream using this link */ - struct link_flags { - bool dp_keep_receiver_powered; - } wa_flags; - struct link_mst_stream_allocation_table mst_stream_alloc_table; - - struct dc_link_status link_status; - -}; - -const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); - -/* - * Return an enumerated dc_link. dc_link order is constant and determined at - * boot time. They cannot be created or destroyed. - * Use dc_get_caps() to get number of links. - */ -static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) -{ - return dc->links[link_index]; -} - -/* Set backlight level of an embedded panel (eDP, LVDS). */ -bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream_state *stream); - -bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait); - -bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); - -bool dc_link_setup_psr(struct dc_link *dc_link, - const struct dc_stream_state *stream, struct psr_config *psr_config, - struct psr_context *psr_context); - -/* Request DC to detect if there is a Panel connected. - * boot - If this call is during initial boot. - * Return false for any type of detection failure or MST detection - * true otherwise. True meaning further action is required (status update - * and OS notification). - */ -enum dc_detect_reason { - DETECT_REASON_BOOT, - DETECT_REASON_HPD, - DETECT_REASON_HPDRX, -}; - -bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason); - -/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). - * Return: - * true - Downstream port status changed. DM should call DC to do the - * detection. - * false - no change in Downstream port status. No further action required - * from DM. */ -bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, - union hpd_irq_data *hpd_irq_dpcd_data); - -struct dc_sink_init_data; - -struct dc_sink *dc_link_add_remote_sink( - struct dc_link *dc_link, - const uint8_t *edid, - int len, - struct dc_sink_init_data *init_data); - -void dc_link_remove_remote_sink( - struct dc_link *link, - struct dc_sink *sink); - -/* Used by diagnostics for virtual link at the moment */ - -void dc_link_dp_set_drive_settings( - struct dc_link *link, - struct link_training_settings *lt_settings); - -enum link_training_result dc_link_dp_perform_link_training( - struct dc_link *link, - const struct dc_link_settings *link_setting, - bool skip_video_pattern); - -void dc_link_dp_enable_hpd(const struct dc_link *link); - -void dc_link_dp_disable_hpd(const struct dc_link *link); - -bool dc_link_dp_set_test_pattern( - struct dc_link *link, - enum dp_test_pattern test_pattern, - const struct link_training_settings *p_link_settings, - const unsigned char *p_custom_pattern, - unsigned int cust_pattern_size); +#include "dc_link.h" /******************************************************************************* * Sink Interfaces - A sink corresponds to a display output device @@ -1037,6 +639,7 @@ struct dc_sink { /* private to dc_sink.c */ struct kref refcount; + }; void dc_sink_retain(struct dc_sink *sink); @@ -1051,18 +654,6 @@ struct dc_sink_init_data { struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); -/******************************************************************************* - * Cursor interfaces - To manages the cursor within a stream - ******************************************************************************/ -/* TODO: Deprecated once we switch to dc_set_cursor_position */ -bool dc_stream_set_cursor_attributes( - struct dc_stream_state *stream, - const struct dc_cursor_attributes *attributes); - -bool dc_stream_set_cursor_position( - struct dc_stream_state *stream, - const struct dc_cursor_position *position); - /* Newer interfaces */ struct dc_cursor { struct dc_plane_address address; @@ -1090,14 +681,4 @@ void dc_set_power_state( enum dc_acpi_cm_power_state power_state); void dc_resume(struct dc *dc); -/* - * DPCD access interfaces - */ - -bool dc_submit_i2c( - struct dc *dc, - uint32_t link_index, - struct i2c_command *cmd); - - #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 77e2de69cca3..2726b02e006b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -255,7 +255,7 @@ enum dpcd_downstream_port_detailed_type { DOWN_STREAM_DETAILED_DP_PLUS_PLUS }; -union dwnstream_port_caps_byte1 { +union dwnstream_port_caps_byte2 { struct { uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; uint8_t RESERVED:6; @@ -298,6 +298,32 @@ union dwnstream_port_caps_byte3_hdmi { /*4-byte structure for detailed capabilities of a down-stream port (DP-to-TMDS converter).*/ +union dwnstream_portxcaps { + struct { + union dwnstream_port_caps_byte0 byte0; + unsigned char max_TMDS_clock; //byte1 + union dwnstream_port_caps_byte2 byte2; + + union { + union dwnstream_port_caps_byte3_dvi byteDVI; + union dwnstream_port_caps_byte3_hdmi byteHDMI; + } byte3; + } bytes; + + unsigned char raw[4]; +}; + +union downstream_port { + struct { + unsigned char present:1; + unsigned char type:2; + unsigned char format_conv:1; + unsigned char detailed_caps:1; + unsigned char reserved:3; + } bits; + unsigned char raw; +}; + union sink_status { struct { diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 0d84b2a1ccfd..c584252669fd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -156,8 +156,13 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, field_value = get_reg_field_value_ex(reg_val, mask, shift); - if (field_value == condition_value) + if (field_value == condition_value) { + if (i * delay_between_poll_us > 1000) + dm_output_to_console("REG_WAIT taking a while: %dms in %s line:%d\n", + delay_between_poll_us * i / 1000, + func_name, line); return reg_val; + } } dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n", diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 1a9f57fb0838..587c0bb3d4ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -492,15 +492,24 @@ struct dc_cursor_attributes { enum dc_color_space { COLOR_SPACE_UNKNOWN, COLOR_SPACE_SRGB, + COLOR_SPACE_XR_RGB, COLOR_SPACE_SRGB_LIMITED, + COLOR_SPACE_MSREF_SCRGB, COLOR_SPACE_YCBCR601, COLOR_SPACE_YCBCR709, + COLOR_SPACE_XV_YCC_709, + COLOR_SPACE_XV_YCC_601, COLOR_SPACE_YCBCR601_LIMITED, COLOR_SPACE_YCBCR709_LIMITED, COLOR_SPACE_2020_RGB_FULLRANGE, COLOR_SPACE_2020_RGB_LIMITEDRANGE, COLOR_SPACE_2020_YCBCR, COLOR_SPACE_ADOBERGB, + COLOR_SPACE_DCIP3, + COLOR_SPACE_DISPLAYNATIVE, + COLOR_SPACE_DOLBYVISION, + COLOR_SPACE_APPCTRL, + COLOR_SPACE_CUSTOMPOINTS, }; enum dc_dither_option { @@ -664,6 +673,22 @@ enum dc_timing_3d_format { TIMING_3D_FORMAT_MAX, }; +enum trigger_delay { + TRIGGER_DELAY_NEXT_PIXEL = 0, + TRIGGER_DELAY_NEXT_LINE, +}; + +enum crtc_event { + CRTC_EVENT_VSYNC_RISING = 0, + CRTC_EVENT_VSYNC_FALLING +}; + +struct crtc_trigger_info { + bool enabled; + struct dc_stream_state *event_source; + enum crtc_event event; + enum trigger_delay delay; +}; struct dc_crtc_timing { diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h new file mode 100644 index 000000000000..f11a734da1db --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h @@ -0,0 +1,207 @@ +/* + * Copyright 2012-14 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_LINK_H_ +#define DC_LINK_H_ + +#include "dc_types.h" +#include "grph_object_defs.h" + +struct dc_link_status { + struct dpcd_caps *dpcd_caps; +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct link_mst_stream_allocation { + /* DIG front */ + const struct stream_encoder *stream_enc; + /* associate DRM payload table with DC stream encoder */ + uint8_t vcp_id; + /* number of slots required for the DP stream in transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct link_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; +}; + +/* + * A link contains one or more sinks and their connected status. + * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. + */ +struct dc_link { + struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; + unsigned int sink_count; + struct dc_sink *local_sink; + unsigned int link_index; + enum dc_connection_type type; + enum signal_type connector_signal; + enum dc_irq_source irq_source_hpd; + enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ + /* caps is the same as reported_link_cap. link_traing use + * reported_link_cap. Will clean up. TODO + */ + struct dc_link_settings reported_link_cap; + struct dc_link_settings verified_link_cap; + struct dc_link_settings cur_link_settings; + struct dc_lane_settings cur_lane_setting; + struct dc_link_settings preferred_link_setting; + + uint8_t ddc_hw_inst; + + uint8_t hpd_src; + + uint8_t link_enc_hw_inst; + + bool test_pattern_enabled; + union compliance_test_state compliance_test_state; + + void *priv; + + struct ddc_service *ddc; + + bool aux_mode; + + /* Private to DC core */ + + const struct dc *dc; + + struct dc_context *ctx; + + struct link_encoder *link_enc; + struct graphics_object_id link_id; + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + struct dpcd_caps dpcd_caps; + unsigned short chip_caps; + unsigned int dpcd_sink_count; + enum edp_revision edp_revision; + bool psr_enabled; + + /* MST record stream using this link */ + struct link_flags { + bool dp_keep_receiver_powered; + } wa_flags; + struct link_mst_stream_allocation_table mst_stream_alloc_table; + + struct dc_link_status link_status; + +}; + +const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link); + +/* + * Return an enumerated dc_link. dc_link order is constant and determined at + * boot time. They cannot be created or destroyed. + * Use dc_get_caps() to get number of links. + */ +static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) +{ + return dc->links[link_index]; +} + +/* Set backlight level of an embedded panel (eDP, LVDS). */ +bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, + uint32_t frame_ramp, const struct dc_stream_state *stream); + +bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait); + +bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); + +bool dc_link_setup_psr(struct dc_link *dc_link, + const struct dc_stream_state *stream, struct psr_config *psr_config, + struct psr_context *psr_context); + +/* Request DC to detect if there is a Panel connected. + * boot - If this call is during initial boot. + * Return false for any type of detection failure or MST detection + * true otherwise. True meaning further action is required (status update + * and OS notification). + */ +enum dc_detect_reason { + DETECT_REASON_BOOT, + DETECT_REASON_HPD, + DETECT_REASON_HPDRX, +}; + +bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason); + +/* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). + * Return: + * true - Downstream port status changed. DM should call DC to do the + * detection. + * false - no change in Downstream port status. No further action required + * from DM. */ +bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data); + +struct dc_sink_init_data; + +struct dc_sink *dc_link_add_remote_sink( + struct dc_link *dc_link, + const uint8_t *edid, + int len, + struct dc_sink_init_data *init_data); + +void dc_link_remove_remote_sink( + struct dc_link *link, + struct dc_sink *sink); + +/* Used by diagnostics for virtual link at the moment */ + +void dc_link_dp_set_drive_settings( + struct dc_link *link, + struct link_training_settings *lt_settings); + +enum link_training_result dc_link_dp_perform_link_training( + struct dc_link *link, + const struct dc_link_settings *link_setting, + bool skip_video_pattern); + +void dc_link_dp_enable_hpd(const struct dc_link *link); + +void dc_link_dp_disable_hpd(const struct dc_link *link); + +bool dc_link_dp_set_test_pattern( + struct dc_link *link, + enum dp_test_pattern test_pattern, + const struct link_training_settings *p_link_settings, + const unsigned char *p_custom_pattern, + unsigned int cust_pattern_size); + +/* + * DPCD access interfaces + */ + +bool dc_submit_i2c( + struct dc *dc, + uint32_t link_index, + struct i2c_command *cmd); + +#endif /* DC_LINK_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h new file mode 100644 index 000000000000..fed0e5ea9625 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -0,0 +1,292 @@ +/* + * Copyright 2012-14 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef DC_STREAM_H_ +#define DC_STREAM_H_ + +#include "dc_types.h" +#include "grph_object_defs.h" + +/******************************************************************************* + * Stream Interfaces + ******************************************************************************/ + +struct dc_stream_status { + int primary_otg_inst; + int stream_enc_inst; + int plane_count; + struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; + + /* + * link this stream passes through + */ + struct dc_link *link; +}; + +struct dc_stream_state { + struct dc_sink *sink; + struct dc_crtc_timing timing; + + struct rect src; /* composition area */ + struct rect dst; /* stream addressable area */ + + struct audio_info audio_info; + + struct freesync_context freesync_ctx; + + struct dc_hdr_static_metadata hdr_static_metadata; + struct dc_transfer_func *out_transfer_func; + struct colorspace_transform gamut_remap_matrix; + struct csc_transform csc_color_matrix; + + enum dc_color_space output_color_space; + enum dc_dither_option dither_option; + + enum view_3d_format view_format; + + bool ignore_msa_timing_param; + /* TODO: custom INFO packets */ + /* TODO: ABM info (DMCU) */ + /* TODO: PSR info */ + /* TODO: CEA VIC */ + + /* from core_stream struct */ + struct dc_context *ctx; + + /* used by DCP and FMT */ + struct bit_depth_reduction_params bit_depth_params; + struct clamping_and_pixel_encoding_params clamping; + + int phy_pix_clk; + enum signal_type signal; + bool dpms_off; + + struct dc_stream_status status; + + struct dc_cursor_attributes cursor_attributes; + + /* from stream struct */ + struct kref refcount; + + struct crtc_trigger_info triggered_crtc_reset; + + /* Computed state bits */ + bool mode_changed : 1; + +}; + +struct dc_stream_update { + struct rect src; + struct rect dst; + struct dc_transfer_func *out_transfer_func; + struct dc_hdr_static_metadata *hdr_static_metadata; +}; + +bool dc_is_stream_unchanged( + struct dc_stream_state *old_stream, struct dc_stream_state *stream); +bool dc_is_stream_scaling_unchanged( + struct dc_stream_state *old_stream, struct dc_stream_state *stream); + +/* + * Set up surface attributes and associate to a stream + * The surfaces parameter is an absolute set of all surface active for the stream. + * If no surfaces are provided, the stream will be blanked; no memory read. + * Any flip related attribute changes must be done through this interface. + * + * After this call: + * Surfaces attributes are programmed and configured to be composed into stream. + * This does not trigger a flip. No surface address is programmed. + */ + +bool dc_commit_planes_to_stream( + struct dc *dc, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, + struct dc_stream_state *dc_stream, + struct dc_state *state); + +void dc_commit_updates_for_stream(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_plane_state **plane_states, + struct dc_state *state); +/* + * Log the current stream state. + */ +void dc_stream_log( + const struct dc_stream_state *stream, + struct dal_logger *dc_logger, + enum dc_log_type log_type); + +uint8_t dc_get_current_stream_count(struct dc *dc); +struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i); + +/* + * Return the current frame counter. + */ +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); + +/* TODO: Return parsed values rather than direct register read + * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) + * being refactored properly to be dce-specific + */ +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); + +enum dc_status dc_add_stream_to_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *stream); + +enum dc_status dc_remove_stream_from_ctx( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *stream); + + +bool dc_add_plane_to_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct dc_state *context); + +bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct dc_state *context); + +bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_state *context); + +bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, + struct dc_state *context); + +enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); + +/* + * This function takes a stream and checks if it is guaranteed to be supported. + * Guaranteed means that MAX_COFUNC similar streams are supported. + * + * After this call: + * No hardware is programmed for call. Only validation is done. + */ + +/* + * Set up streams and links associated to drive sinks + * The streams parameter is an absolute set of all active streams. + * + * After this call: + * Phy, Encoder, Timing Generator are programmed and enabled. + * New streams are enabled with blank stream; no memory read. + */ +/* + * Enable stereo when commit_streams is not required, + * for example, frame alternate. + */ +bool dc_enable_stereo( + struct dc *dc, + struct dc_state *context, + struct dc_stream_state *streams[], + uint8_t stream_count); + + +enum surface_update_type dc_check_update_surfaces_for_stream( + struct dc *dc, + struct dc_surface_update *updates, + int surface_count, + struct dc_stream_update *stream_update, + const struct dc_stream_status *stream_status); + +/** + * Create a new default stream for the requested sink + */ +struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); + +void dc_stream_retain(struct dc_stream_state *dc_stream); +void dc_stream_release(struct dc_stream_state *dc_stream); + +struct dc_stream_status *dc_stream_get_status( + struct dc_stream_state *dc_stream); + +/******************************************************************************* + * Cursor interfaces - To manages the cursor within a stream + ******************************************************************************/ +/* TODO: Deprecated once we switch to dc_set_cursor_position */ +bool dc_stream_set_cursor_attributes( + struct dc_stream_state *stream, + const struct dc_cursor_attributes *attributes); + +bool dc_stream_set_cursor_position( + struct dc_stream_state *stream, + const struct dc_cursor_position *position); + +bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + int vmin, + int vmax); + +bool dc_stream_get_crtc_position(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + unsigned int *v_pos, + unsigned int *nom_v_pos); + +void dc_stream_set_static_screen_events(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + const struct dc_static_screen_events *events); + + +bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + int vmin, + int vmax); + +bool dc_stream_get_crtc_position(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + unsigned int *v_pos, + unsigned int *nom_v_pos); + +void dc_stream_set_static_screen_events(struct dc *dc, + struct dc_stream_state **stream, + int num_streams, + const struct dc_static_screen_events *events); + +#endif /* DC_STREAM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index a8698e399111..9291a60126ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -638,11 +638,6 @@ struct colorspace_transform { bool enable_remap; }; -struct csc_transform { - uint16_t matrix[12]; - bool enable_adjustment; -}; - enum i2c_mot_mode { I2C_MOT_UNDEF, I2C_MOT_TRUE, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 0e0336c5af4e..3fe8e697483f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -51,16 +51,6 @@ #define MCP_DISABLE_ABM_IMMEDIATELY 255 -struct abm_backlight_registers { - unsigned int BL_PWM_CNTL; - unsigned int BL_PWM_CNTL2; - unsigned int BL_PWM_PERIOD_CNTL; - unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; -}; - -/* registers setting needs to be save and restored used at InitBacklight */ -static struct abm_backlight_registers stored_backlight_registers = {0}; - static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce) { @@ -347,16 +337,16 @@ static bool dce_abm_init_backlight(struct abm *abm) */ REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); if (value == 0 || value == 1) { - if (stored_backlight_registers.BL_PWM_CNTL != 0) { + if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) { REG_WRITE(BL_PWM_CNTL, - stored_backlight_registers.BL_PWM_CNTL); + abm->stored_backlight_registers.BL_PWM_CNTL); REG_WRITE(BL_PWM_CNTL2, - stored_backlight_registers.BL_PWM_CNTL2); + abm->stored_backlight_registers.BL_PWM_CNTL2); REG_WRITE(BL_PWM_PERIOD_CNTL, - stored_backlight_registers.BL_PWM_PERIOD_CNTL); + abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL); REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, - stored_backlight_registers. + abm->stored_backlight_registers. LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); } else { /* TODO: Note: This should not really happen since VBIOS @@ -366,15 +356,15 @@ static bool dce_abm_init_backlight(struct abm *abm) REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); } } else { - stored_backlight_registers.BL_PWM_CNTL = + abm->stored_backlight_registers.BL_PWM_CNTL = REG_READ(BL_PWM_CNTL); - stored_backlight_registers.BL_PWM_CNTL2 = + abm->stored_backlight_registers.BL_PWM_CNTL2 = REG_READ(BL_PWM_CNTL2); - stored_backlight_registers.BL_PWM_PERIOD_CNTL = + abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL = REG_READ(BL_PWM_PERIOD_CNTL); REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, - &stored_backlight_registers. + &abm->stored_backlight_registers. LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); } @@ -450,6 +440,10 @@ static void dce_abm_construct( base->ctx = ctx; base->funcs = &dce_funcs; + base->stored_backlight_registers.BL_PWM_CNTL = 0; + base->stored_backlight_registers.BL_PWM_CNTL2 = 0; + base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; + base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; abm_dce->regs = regs; abm_dce->abm_shift = abm_shift; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index fd77df573b61..a6de99db0444 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -49,8 +49,16 @@ #define PSR_EXIT 0x21 #define PSR_SET 0x23 #define PSR_SET_WAITLOOP 0x31 +#define MCP_INIT_DMCU 0x88 +#define MCP_INIT_IRAM 0x89 +#define MCP_DMCU_VERSION 0x90 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L -unsigned int cached_wait_loop_number = 0; + +static bool dce_dmcu_init(struct dmcu *dmcu) +{ + // Do nothing + return true; +} bool dce_dmcu_load_iram(struct dmcu *dmcu, unsigned int start_offset, @@ -84,7 +92,7 @@ static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); - uint32_t psrStateOffset = 0xf0; + uint32_t psr_state_offset = 0xf0; /* Enable write access to IRAM */ REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); @@ -92,7 +100,7 @@ static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ - REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); + REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ *psr_state = REG_READ(DMCU_IRAM_RD_DATA); @@ -261,7 +269,7 @@ static void dce_psr_wait_loop( { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; - if (cached_wait_loop_number == wait_loop_number) + if (dmcu->cached_wait_loop_number == wait_loop_number) return; /* waitDMCUReadyForCmd */ @@ -269,7 +277,7 @@ static void dce_psr_wait_loop( masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; - cached_wait_loop_number = wait_loop_number; + dmcu->cached_wait_loop_number = wait_loop_number; dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); /* setDMCUParam_Cmd */ @@ -279,14 +287,136 @@ static void dce_psr_wait_loop( REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } -static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number) +static void dce_get_psr_wait_loop( + struct dmcu *dmcu, unsigned int *psr_wait_loop_number) { - *psr_wait_loop_number = cached_wait_loop_number; + *psr_wait_loop_number = dmcu->cached_wait_loop_number; return; } #if defined(CONFIG_DRM_AMD_DC_DCN1_0) -bool dcn10_dmcu_load_iram(struct dmcu *dmcu, +static void dcn10_get_dmcu_state(struct dmcu *dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + uint32_t dmcu_state_offset = 0xf6; + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_RD_ADDR_AUTO_INC, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ + REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset); + + /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ + dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_RD_ADDR_AUTO_INC, 0); +} + +static void dcn10_get_dmcu_version(struct dmcu *dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + uint32_t dmcu_version_offset = 0xf1; + + /* Clear scratch */ + REG_WRITE(DC_DMCU_SCRATCH, 0); + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_RD_ADDR_AUTO_INC, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + /* Write address to IRAM_RD_ADDR and read from DATA register */ + REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset); + dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA); + dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) | + REG_READ(DMCU_IRAM_RD_DATA)); + dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA); + dmcu->dmcu_version.day = REG_READ(DMCU_IRAM_RD_DATA); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_RD_ADDR_AUTO_INC, 0); + + /* Send MCP command message to DMCU to get version reply from FW. + * We expect this version should match the one in IRAM, otherwise + * something is wrong with DMCU and we should fail and disable UC. + */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Set command to get DMCU version from microcontroller */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + MCP_DMCU_VERSION); + + /* Notify microcontroller of new command */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Ensure command has been executed before continuing */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Somehow version does not match, so fail and return version 0 */ + if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH)) + dmcu->dmcu_version.interface_version = 0; +} + +static bool dcn10_dmcu_init(struct dmcu *dmcu) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + + /* DMCU FW should populate the scratch register if running */ + if (REG_READ(DC_DMCU_SCRATCH) == 0) + return false; + + /* Check state is uninitialized */ + dcn10_get_dmcu_state(dmcu); + + /* If microcontroller is already initialized, do nothing */ + if (dmcu->dmcu_state == DMCU_RUNNING) + return true; + + /* Retrieve and cache the DMCU firmware version. */ + dcn10_get_dmcu_version(dmcu); + + /* Check interface version to confirm firmware is loaded and running */ + if (dmcu->dmcu_version.interface_version == 0) + return false; + + /* Wait until microcontroller is ready to process interrupt */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Set initialized ramping boundary value */ + REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); + + /* Set command to initialize microcontroller */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + MCP_INIT_DMCU); + + /* Notify microcontroller of new command */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Ensure command has been executed before continuing */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + // Check state is initialized + dcn10_get_dmcu_state(dmcu); + + // If microcontroller is not in running state, fail + if (dmcu->dmcu_state != DMCU_RUNNING) + return false; + + return true; +} + +static bool dcn10_dmcu_load_iram(struct dmcu *dmcu, unsigned int start_offset, const char *src, unsigned int bytes) @@ -294,7 +424,9 @@ bool dcn10_dmcu_load_iram(struct dmcu *dmcu, struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); unsigned int count = 0; - REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1); + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return false; /* Enable write access to IRAM */ REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, @@ -313,6 +445,19 @@ bool dcn10_dmcu_load_iram(struct dmcu *dmcu, IRAM_HOST_ACCESS_EN, 0, IRAM_WR_ADDR_AUTO_INC, 0); + /* Wait until microcontroller is ready to process interrupt */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + + /* Set command to signal IRAM is loaded and to initialize IRAM */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + MCP_INIT_IRAM); + + /* Notify microcontroller of new command */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Ensure command has been executed before continuing */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); + return true; } @@ -320,7 +465,11 @@ static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); - uint32_t psrStateOffset = 0xf0; + uint32_t psr_state_offset = 0xf0; + + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; /* Enable write access to IRAM */ REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); @@ -328,7 +477,7 @@ static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ - REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); + REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset); /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ *psr_state = REG_READ(DMCU_IRAM_RD_DATA); @@ -348,6 +497,10 @@ static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) unsigned int retryCount; uint32_t psr_state = 0; + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + /* waitDMCUReadyForCmd */ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, dmcu_wait_reg_ready_interval, @@ -399,6 +552,10 @@ static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, union dce_dmcu_psr_config_data_reg2 masterCmdData2; union dce_dmcu_psr_config_data_reg3 masterCmdData3; + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, psr_context->psrExitLinkTrainingRequired); @@ -505,13 +662,18 @@ static void dcn10_psr_wait_loop( { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* If microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != DMCU_RUNNING) + return; + if (wait_loop_number != 0) { /* waitDMCUReadyForCmd */ REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); masterCmdData1.u32 = 0; masterCmdData1.bits.wait_loop = wait_loop_number; - cached_wait_loop_number = wait_loop_number; + dmcu->cached_wait_loop_number = wait_loop_number; dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); /* setDMCUParam_Cmd */ @@ -522,15 +684,17 @@ static void dcn10_psr_wait_loop( } } -static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number) +static void dcn10_get_psr_wait_loop( + struct dmcu *dmcu, unsigned int *psr_wait_loop_number) { - *psr_wait_loop_number = cached_wait_loop_number; + *psr_wait_loop_number = dmcu->cached_wait_loop_number; return; } #endif static const struct dmcu_funcs dce_funcs = { + .dmcu_init = dce_dmcu_init, .load_iram = dce_dmcu_load_iram, .set_psr_enable = dce_dmcu_set_psr_enable, .setup_psr = dce_dmcu_setup_psr, @@ -541,6 +705,7 @@ static const struct dmcu_funcs dce_funcs = { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) static const struct dmcu_funcs dcn10_funcs = { + .dmcu_init = dcn10_dmcu_init, .load_iram = dcn10_dmcu_load_iram, .set_psr_enable = dcn10_dmcu_set_psr_enable, .setup_psr = dcn10_dmcu_setup_psr, @@ -561,6 +726,7 @@ static void dce_dmcu_construct( base->ctx = ctx; base->funcs = &dce_funcs; + base->cached_wait_loop_number = 0; dmcu_dce->regs = regs; dmcu_dce->dmcu_shift = dmcu_shift; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h index b85f53c2f6f8..4c25e2dd28f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h @@ -31,6 +31,7 @@ #define DMCU_COMMON_REG_LIST_DCE_BASE() \ SR(DMCU_CTRL), \ + SR(DMCU_STATUS), \ SR(DMCU_RAM_ACCESS_CTRL), \ SR(DMCU_IRAM_WR_CTRL), \ SR(DMCU_IRAM_WR_DATA), \ @@ -42,7 +43,8 @@ SR(DMCU_IRAM_RD_CTRL), \ SR(DMCU_IRAM_RD_DATA), \ SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ - SR(SMU_INTERRUPT_CONTROL) + SR(SMU_INTERRUPT_CONTROL), \ + SR(DC_DMCU_SCRATCH) #define DMCU_DCE110_COMMON_REG_LIST() \ DMCU_COMMON_REG_LIST_DCE_BASE(), \ @@ -58,10 +60,14 @@ #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ DMCU_SF(DMCU_CTRL, \ DMCU_ENABLE, mask_sh), \ + DMCU_SF(DMCU_STATUS, \ + UC_IN_STOP_MODE, mask_sh), \ DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ IRAM_HOST_ACCESS_EN, mask_sh), \ DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ IRAM_WR_ADDR_AUTO_INC, mask_sh), \ + DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ + IRAM_RD_ADDR_AUTO_INC, mask_sh), \ DMCU_SF(MASTER_COMM_CMD_REG, \ MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ @@ -89,7 +95,9 @@ type DMCU_IRAM_MEM_PWR_STATE; \ type IRAM_HOST_ACCESS_EN; \ type IRAM_WR_ADDR_AUTO_INC; \ + type IRAM_RD_ADDR_AUTO_INC; \ type DMCU_ENABLE; \ + type UC_IN_STOP_MODE; \ type MASTER_COMM_CMD_REG_BYTE0; \ type MASTER_COMM_INTERRUPT; \ type DPHY_RX_FAST_TRAINING_CAPABLE; \ @@ -112,6 +120,7 @@ struct dce_dmcu_mask { struct dce_dmcu_registers { uint32_t DMCU_CTRL; + uint32_t DMCU_STATUS; uint32_t DMCU_RAM_ACCESS_CTRL; uint32_t DCI_MEM_PWR_STATUS; uint32_t DMU_MEM_PWR_CNTL; @@ -127,6 +136,7 @@ struct dce_dmcu_registers { uint32_t DMCU_IRAM_RD_DATA; uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; uint32_t SMU_INTERRUPT_CONTROL; + uint32_t DC_DMCU_SCRATCH; }; struct dce_dmcu { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 52506155e361..3b0db253ac22 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -140,10 +140,6 @@ BL_REG_LIST() #define HWSEQ_DCN_REG_LIST()\ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \ - SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \ SRII(DCHUBP_CNTL, HUBP, 0), \ SRII(DCHUBP_CNTL, HUBP, 1), \ SRII(DCHUBP_CNTL, HUBP, 2), \ @@ -264,7 +260,6 @@ struct dce_hwseq_registers { uint32_t DCHUB_AGP_BOT; uint32_t DCHUB_AGP_TOP; - uint32_t OTG_GLOBAL_SYNC_STATUS[4]; uint32_t DCHUBP_CNTL[4]; uint32_t HUBP_CLK_CNTL[4]; uint32_t DPP_CONTROL[4]; @@ -438,8 +433,6 @@ struct dce_hwseq_registers { #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ - HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \ - HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \ HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \ HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \ HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ @@ -536,8 +529,6 @@ struct dce_hwseq_registers { type LVTMA_PWRSEQ_TARGET_STATE_R; #define HWSEQ_DCN_REG_FIELD_LIST(type) \ - type VUPDATE_NO_LOCK_EVENT_CLEAR; \ - type VUPDATE_NO_LOCK_EVENT_OCCURRED; \ type HUBP_VTG_SEL; \ type HUBP_CLOCK_ENABLE; \ type DPP_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index d618fdd0cc82..d737e911971b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -135,36 +135,34 @@ static void dce_ipp_cursor_set_attributes( } -static void dce_ipp_program_prescale( - struct input_pixel_processor *ipp, - struct ipp_prescale_params *params) +static void dce_ipp_program_prescale(struct input_pixel_processor *ipp, + struct ipp_prescale_params *params) { struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); /* set to bypass mode first before change */ REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, - 1); + GRPH_PRESCALE_BYPASS, 1); REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, - GRPH_PRESCALE_SCALE_R, params->scale, - GRPH_PRESCALE_BIAS_R, params->bias); + GRPH_PRESCALE_SCALE_R, params->scale, + GRPH_PRESCALE_BIAS_R, params->bias); REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, - GRPH_PRESCALE_SCALE_G, params->scale, - GRPH_PRESCALE_BIAS_G, params->bias); + GRPH_PRESCALE_SCALE_G, params->scale, + GRPH_PRESCALE_BIAS_G, params->bias); REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, - GRPH_PRESCALE_SCALE_B, params->scale, - GRPH_PRESCALE_BIAS_B, params->bias); + GRPH_PRESCALE_SCALE_B, params->scale, + GRPH_PRESCALE_BIAS_B, params->bias); if (params->mode != IPP_PRESCALE_MODE_BYPASS) { REG_UPDATE(PRESCALE_GRPH_CONTROL, - GRPH_PRESCALE_BYPASS, 0); + GRPH_PRESCALE_BYPASS, 0); /* If prescale is in use, then legacy lut should be bypassed */ REG_UPDATE(INPUT_GAMMA_CONTROL, - GRPH_INPUT_GAMMA_MODE, 1); + GRPH_INPUT_GAMMA_MODE, 1); } } @@ -223,13 +221,12 @@ static void dce_ipp_set_degamma( struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp); uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0; - ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || - mode == IPP_DEGAMMA_MODE_HW_sRGB); + ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB); REG_SET_3(DEGAMMA_CONTROL, 0, - GRPH_DEGAMMA_MODE, degamma_type, - CURSOR_DEGAMMA_MODE, degamma_type, - CURSOR2_DEGAMMA_MODE, degamma_type); + GRPH_DEGAMMA_MODE, degamma_type, + CURSOR_DEGAMMA_MODE, degamma_type, + CURSOR2_DEGAMMA_MODE, degamma_type); } static const struct ipp_funcs dce_ipp_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index fe88852b4774..bad70c6b3aad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -845,8 +845,6 @@ void dce110_link_encoder_hw_init( ASSERT(result == BP_RESULT_OK); - } else if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - ctx->dc->hwss.edp_power_control(enc, true); } aux_initialize(enc110); @@ -1033,8 +1031,7 @@ void dce110_link_encoder_enable_dp_mst_output( */ void dce110_link_encoder_disable_output( struct link_encoder *enc, - enum signal_type signal, - struct dc_link *link) + enum signal_type signal) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); struct dc_context *ctx = enc110->base.ctx; @@ -1045,8 +1042,6 @@ void dce110_link_encoder_disable_output( /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ return; } - if (enc110->base.connector.id == CONNECTOR_ID_EDP) - ctx->dc->hwss.edp_backlight_control(link, false); /* Power-down RX and disable GPU PHY should be paired. * Disabling PHY without powering down RX may cause * symbol lock loss, on which we will get DP Sink interrupt. */ @@ -1078,19 +1073,20 @@ void dce110_link_encoder_disable_output( if (dc_is_dp_signal(signal)) link_encoder_disable(enc110); - if (enc110->base.connector.id == CONNECTOR_ID_EDP) { - /* power down eDP panel */ - /* TODO: Power control cause regression, we should implement - * it properly, for now just comment it. - * - * link_encoder_edp_wait_for_hpd_ready( - link_enc, - link_enc->connector, - false); - - * link_encoder_edp_power_control( - link_enc, false); */ - } + /* + * TODO: Power control cause regression, we should implement + * it properly, for now just comment it. + */ +// if (enc110->base.connector.id == CONNECTOR_ID_EDP) { +// /* power down eDP panel */ +// link_encoder_edp_wait_for_hpd_ready( +// enc, +// enc->connector, +// false); +// +// link_encoder_edp_power_control( +// enc, false); +// } } void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 494067dedd03..8ca9afe47a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -228,9 +228,8 @@ void dce110_link_encoder_enable_dp_mst_output( /* disable PHY output */ void dce110_link_encoder_disable_output( - struct link_encoder *link_enc, - enum signal_type signal, - struct dc_link *link); + struct link_encoder *enc, + enum signal_type signal); /* set DP lane settings */ void dce110_link_encoder_dp_set_lane_settings( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index e42b6eb1c1f0..83bae207371d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -300,6 +300,8 @@ static void dce110_stream_encoder_dp_set_stream_attribute( uint32_t h_back_porch; uint8_t synchronous_clock = 0; /* asynchronous mode */ uint8_t colorimetry_bpc; + uint8_t dynamic_range_rgb = 0; /*full range*/ + uint8_t dynamic_range_ycbcr = 1; /*bt709*/ #endif struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); @@ -380,11 +382,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( } /* set dynamic range and YCbCr range */ - if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) - REG_UPDATE_2( - DP_PIXEL_FORMAT, - DP_DYN_RANGE, 0, - DP_YCBCR_RANGE, 0); + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) switch (crtc_timing->display_color_depth) { @@ -413,37 +411,57 @@ static void dce110_stream_encoder_dp_set_stream_attribute( case COLOR_SPACE_SRGB: misc0 = misc0 | 0x0; misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_rgb = 0; /*full range*/ break; case COLOR_SPACE_SRGB_LIMITED: misc0 = misc0 | 0x8; /* bit3=1 */ misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_rgb = 1; /*limited range*/ break; case COLOR_SPACE_YCBCR601: + case COLOR_SPACE_YCBCR601_LIMITED: misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_ycbcr = 0; /*bt601*/ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ break; case COLOR_SPACE_YCBCR709: + case COLOR_SPACE_YCBCR709_LIMITED: misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ misc1 = misc1 & ~0x80; /* bit7 = 0*/ + dynamic_range_ycbcr = 1; /*bt709*/ if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ break; - case COLOR_SPACE_2020_RGB_FULLRANGE: case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + dynamic_range_rgb = 1; /*limited range*/ + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_XR_RGB: + case COLOR_SPACE_MSREF_SCRGB: case COLOR_SPACE_ADOBERGB: + case COLOR_SPACE_DCIP3: + case COLOR_SPACE_XV_YCC_709: + case COLOR_SPACE_XV_YCC_601: + case COLOR_SPACE_DISPLAYNATIVE: + case COLOR_SPACE_DOLBYVISION: + case COLOR_SPACE_APPCTRL: + case COLOR_SPACE_CUSTOMPOINTS: case COLOR_SPACE_UNKNOWN: - case COLOR_SPACE_YCBCR601_LIMITED: - case COLOR_SPACE_YCBCR709_LIMITED: /* do nothing */ break; } + if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) + REG_UPDATE_2( + DP_PIXEL_FORMAT, + DP_DYN_RANGE, dynamic_range_rgb, + DP_YCBCR_RANGE, dynamic_range_ycbcr); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (REG(DP_MSA_COLORIMETRY)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index ae32af31eff1..0f662e6ee9bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -1177,207 +1177,160 @@ void dce110_opp_set_csc_default( default_adjust->out_color_space); } -static void program_pwl( - struct dce_transform *xfm_dce, - const struct pwl_params *params) +static void program_pwl(struct dce_transform *xfm_dce, + const struct pwl_params *params) { - uint32_t value; int retval; + uint8_t max_tries = 10; + uint8_t counter = 0; + uint32_t i = 0; + const struct pwl_result_data *rgb = params->rgb_resulted; - { - uint8_t max_tries = 10; - uint8_t counter = 0; + /* Power on LUT memory */ + if (REG(DCFE_MEM_PWR_CTRL)) + REG_UPDATE(DCFE_MEM_PWR_CTRL, + DCP_REGAMMA_MEM_PWR_DIS, 1); + else + REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - /* Power on LUT memory */ - if (REG(DCFE_MEM_PWR_CTRL)) - REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 1); - else - REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 1); - - while (counter < max_tries) { - if (REG(DCFE_MEM_PWR_STATUS)) { - value = REG_READ(DCFE_MEM_PWR_STATUS); - REG_GET(DCFE_MEM_PWR_STATUS, - DCP_REGAMMA_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } else { - value = REG_READ(DCFE_MEM_LIGHT_SLEEP_CNTL); - REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_MEM_PWR_STATE, - &retval); - - if (retval == 0) - break; - ++counter; - } + while (counter < max_tries) { + if (REG(DCFE_MEM_PWR_STATUS)) { + REG_GET(DCFE_MEM_PWR_STATUS, + DCP_REGAMMA_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; + } else { + REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, + REGAMMA_LUT_MEM_PWR_STATE, + &retval); + + if (retval == 0) + break; + ++counter; } + } - if (counter == max_tries) { - dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, + if (counter == max_tries) { + dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING, "%s: regamma lut was not powered on " "in a timely manner," " programming still proceeds\n", __func__); - } } REG_UPDATE(REGAMMA_LUT_WRITE_EN_MASK, - REGAMMA_LUT_WRITE_EN_MASK, 7); + REGAMMA_LUT_WRITE_EN_MASK, 7); REG_WRITE(REGAMMA_LUT_INDEX, 0); /* Program REGAMMA_LUT_DATA */ - { - uint32_t i = 0; - const struct pwl_result_data *rgb = params->rgb_resulted; - - while (i != params->hw_points_num) { + while (i != params->hw_points_num) { - REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); - REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg); + REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg); - ++rgb; - ++i; - } + ++rgb; + ++i; } /* we are done with DCP LUT memory; re-enable low power mode */ if (REG(DCFE_MEM_PWR_CTRL)) REG_UPDATE(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, 0); + DCP_REGAMMA_MEM_PWR_DIS, 0); else REG_UPDATE(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); + REGAMMA_LUT_LIGHT_SLEEP_DIS, 0); } -static void regamma_config_regions_and_segments( - struct dce_transform *xfm_dce, - const struct pwl_params *params) +static void regamma_config_regions_and_segments(struct dce_transform *xfm_dce, + const struct pwl_params *params) { const struct gamma_curve *curve; - { - REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, - REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - } - { - REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, - REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); + REG_SET_2(REGAMMA_CNTLA_START_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_START, params->arr_points[0].custom_float_x, + REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, 0); - } - { - REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, - REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - } - { - REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, - REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, - REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[2].custom_float_slope); - } + REG_SET(REGAMMA_CNTLA_SLOPE_CNTL, 0, + REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, params->arr_points[0].custom_float_slope); - curve = params->arr_curve_points; + REG_SET(REGAMMA_CNTLA_END_CNTL1, 0, + REGAMMA_CNTLA_EXP_REGION_END, params->arr_points[1].custom_float_x); - { - REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } + REG_SET_2(REGAMMA_CNTLA_END_CNTL2, 0, + REGAMMA_CNTLA_EXP_REGION_END_BASE, params->arr_points[1].custom_float_y, + REGAMMA_CNTLA_EXP_REGION_END_SLOPE, params->arr_points[1].custom_float_slope); - curve += 2; - - { - REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } + curve = params->arr_curve_points; + REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } - + REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - - } + REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + curve += 2; + REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); curve += 2; - { - REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, - REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, - REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, - REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, - REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); - } + REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, + REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); } -void dce110_opp_program_regamma_pwl( - struct transform *xfm, - const struct pwl_params *params) +void dce110_opp_program_regamma_pwl(struct transform *xfm, + const struct pwl_params *params) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); @@ -1388,47 +1341,42 @@ void dce110_opp_program_regamma_pwl( program_pwl(xfm_dce, params); } -void dce110_opp_power_on_regamma_lut( - struct transform *xfm, - bool power_on) +void dce110_opp_power_on_regamma_lut(struct transform *xfm, + bool power_on) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); if (REG(DCFE_MEM_PWR_CTRL)) REG_UPDATE_2(DCFE_MEM_PWR_CTRL, - DCP_REGAMMA_MEM_PWR_DIS, power_on, - DCP_LUT_MEM_PWR_DIS, power_on); + DCP_REGAMMA_MEM_PWR_DIS, power_on, + DCP_LUT_MEM_PWR_DIS, power_on); else REG_UPDATE_2(DCFE_MEM_LIGHT_SLEEP_CNTL, - REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, - DCP_LUT_LIGHT_SLEEP_DIS, power_on); + REGAMMA_LUT_LIGHT_SLEEP_DIS, power_on, + DCP_LUT_LIGHT_SLEEP_DIS, power_on); } void dce110_opp_set_regamma_mode(struct transform *xfm, - enum opp_regamma mode) + enum opp_regamma mode) { struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm); REG_SET(REGAMMA_CONTROL, 0, - GRPH_REGAMMA_MODE, mode); + GRPH_REGAMMA_MODE, mode); } static const struct transform_funcs dce_transform_funcs = { .transform_reset = dce_transform_reset, - .transform_set_scaler = - dce_transform_set_scaler, - .transform_set_gamut_remap = - dce_transform_set_gamut_remap, + .transform_set_scaler = dce_transform_set_scaler, + .transform_set_gamut_remap = dce_transform_set_gamut_remap, .opp_set_csc_adjustment = dce110_opp_set_csc_adjustment, .opp_set_csc_default = dce110_opp_set_csc_default, .opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut, .opp_program_regamma_pwl = dce110_opp_program_regamma_pwl, .opp_set_regamma_mode = dce110_opp_set_regamma_mode, - .transform_set_pixel_storage_depth = - dce_transform_set_pixel_storage_depth, - .transform_get_optimal_number_of_taps = - dce_transform_get_optimal_number_of_taps + .transform_set_pixel_storage_depth = dce_transform_set_pixel_storage_depth, + .transform_get_optimal_number_of_taps = dce_transform_get_optimal_number_of_taps }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index e7a694835e3e..469af0587604 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -148,5 +148,7 @@ void dce100_hw_sequencer_construct(struct dc *dc) dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.set_bandwidth = dce100_set_bandwidth; + dc->hwss.pplib_apply_display_requirements = + dce100_pplib_apply_display_requirements; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 07ff8d2faf3f..e650bdcd9423 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -257,9 +257,9 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, } } -static bool dce110_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) +static bool +dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; const struct dc_transfer_func *tf = NULL; @@ -280,25 +280,19 @@ static bool dce110_set_input_transfer_func( if (tf == NULL) { /* Default case if no input transfer function specified */ - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_sRGB); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); } else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_sRGB); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_HW_xvYCC); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - ipp->funcs->ipp_set_degamma(ipp, - IPP_DEGAMMA_MODE_BYPASS); + ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: - result = false; - break; default: result = false; break; @@ -313,10 +307,9 @@ static bool dce110_set_input_transfer_func( return result; } -static bool convert_to_custom_float( - struct pwl_result_data *rgb_resulted, - struct curve_points *arr_points, - uint32_t hw_points_num) +static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, + struct curve_points *arr_points, + uint32_t hw_points_num) { struct custom_float_format fmt; @@ -328,26 +321,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 12; fmt.sign = true; - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -355,26 +342,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 10; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[2].slope, - &fmt, - &arr_points[2].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[2].slope, &fmt, + &arr_points[2].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -383,50 +364,38 @@ static bool convert_to_custom_float( fmt.sign = true; while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { BREAK_TO_DEBUGGER(); return false; } @@ -438,8 +407,9 @@ static bool convert_to_custom_float( return true; } -static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params) +static bool +dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, + struct pwl_params *regamma_params) { struct curve_points *arr_points; struct pwl_result_data *rgb_resulted; @@ -454,8 +424,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t segment_start, segment_end; uint32_t i, j, k, seg_distr[16], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL || - output_tf->type == TF_TYPE_BYPASS) + if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; arr_points = regamma_params->arr_points; @@ -534,19 +503,14 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func /* last point */ start_index = (segment_end + 25) * 32; - rgb_resulted[hw_points - 1].red = - output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = - output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = - output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); + dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); - arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); + dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -555,9 +519,8 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, + arr_points[0].x); y_r = rgb_resulted[hw_points - 1].red; y_g = rgb_resulted[hw_points - 1].green; @@ -569,24 +532,18 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); arr_points[1].y = y3_max; - arr_points[2].y = y3_max; arr_points[1].slope = dal_fixed31_32_zero; - arr_points[2].slope = dal_fixed31_32_zero; if (output_tf->tf == TRANSFER_FUNCTION_PQ) { /* for PQ, we want to have a straight line from last HW X point, * and the slope to be such that we hit 1.0 at 10000 nits. */ - const struct fixed31_32 end_value = - dal_fixed31_32_from_int(125); + const struct fixed31_32 end_value = dal_fixed31_32_from_int(125); arr_points[1].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); + dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), + dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; @@ -594,18 +551,15 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func i = 1; for (k = 0; k < 16 && i < 16; k++) { if (seg_distr[k] != -1) { - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k]. - offset + (1 << seg_distr[k]); + regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); } i++; } if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; @@ -620,15 +574,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) rgb_plus_1->blue = rgb->blue; - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); ++rgb_plus_1; ++rgb; @@ -640,9 +588,9 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func return true; } -static bool dce110_set_output_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream) +static bool +dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->plane_res.xfm; @@ -650,13 +598,11 @@ static bool dce110_set_output_transfer_func( xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && - stream->out_transfer_func->type == - TF_TYPE_PREDEFINED && - stream->out_transfer_func->tf == - TRANSFER_FUNCTION_SRGB) { + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); - } else if (dce110_translate_regamma_to_hw_format( - stream->out_transfer_func, &xfm->regamma_params)) { + } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, + &xfm->regamma_params)) { xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { @@ -814,11 +760,11 @@ static enum bp_result link_transmitter_control( * eDP only. */ void hwss_edp_wait_for_hpd_ready( - struct link_encoder *enc, - bool power_up) + struct dc_link *link, + bool power_up) { - struct dc_context *ctx = enc->ctx; - struct graphics_object_id connector = enc->connector; + struct dc_context *ctx = link->ctx; + struct graphics_object_id connector = link->link_enc->connector; struct gpio *hpd; bool edp_hpd_high = false; uint32_t time_elapsed = 0; @@ -882,16 +828,16 @@ void hwss_edp_wait_for_hpd_ready( } void hwss_edp_power_control( - struct link_encoder *enc, - bool power_up) + struct dc_link *link, + bool power_up) { - struct dc_context *ctx = enc->ctx; + struct dc_context *ctx = link->ctx; struct dce_hwseq *hwseq = ctx->dc->hwseq; struct bp_transmitter_control cntl = { 0 }; enum bp_result bp_result; - if (dal_graphics_object_id_get_connector_id(enc->connector) + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); return; @@ -907,11 +853,11 @@ void hwss_edp_power_control( cntl.action = power_up ? TRANSMITTER_CONTROL_POWER_ON : TRANSMITTER_CONTROL_POWER_OFF; - cntl.transmitter = enc->transmitter; - cntl.connector_obj_id = enc->connector; + cntl.transmitter = link->link_enc->transmitter; + cntl.connector_obj_id = link->link_enc->connector; cntl.coherent = false; cntl.lanes_number = LANE_COUNT_FOUR; - cntl.hpd_sel = enc->hpd_source; + cntl.hpd_sel = link->link_enc->hpd_source; bp_result = link_transmitter_control(ctx->dc_bios, &cntl); @@ -925,7 +871,7 @@ void hwss_edp_power_control( __func__, (power_up ? "On":"Off")); } - hwss_edp_wait_for_hpd_ready(enc, true); + hwss_edp_wait_for_hpd_ready(link, true); } /*todo: cloned in stream enc, fix*/ @@ -934,14 +880,14 @@ void hwss_edp_power_control( * eDP only. Control the backlight of the eDP panel */ void hwss_edp_backlight_control( - struct dc_link *link, - bool enable) + struct dc_link *link, + bool enable) { - struct dce_hwseq *hws = link->dc->hwseq; - struct dc_context *ctx = link->dc->ctx; + struct dc_context *ctx = link->ctx; + struct dce_hwseq *hws = ctx->dc->hwseq; struct bp_transmitter_control cntl = { 0 }; - if (dal_graphics_object_id_get_connector_id(link->link_id) + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); return; @@ -982,7 +928,7 @@ void hwss_edp_backlight_control( * Enable it in the future if necessary. */ /* dc_service_sleep_in_milliseconds(50); */ - link_transmitter_control(link->dc->ctx->dc_bios, &cntl); + link_transmitter_control(ctx->dc_bios, &cntl); } void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) @@ -1396,12 +1342,14 @@ static void power_down_encoders(struct dc *dc) if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) dp_receiver_power_ctrl(dc->links[i], false); - if (connector_id == CONNECTOR_ID_EDP) + if (connector_id == CONNECTOR_ID_EDP) { signal = SIGNAL_TYPE_EDP; + hwss_edp_backlight_control(dc->links[i], false); + } } dc->links[i]->link_enc->funcs->disable_output( - dc->links[i]->link_enc, signal, dc->links[i]); + dc->links[i]->link_enc, signal); } } @@ -1462,7 +1410,9 @@ static void disable_vga_and_power_gate_all_controllers( enable_display_pipe_clock_gating(ctx, true); - dc->hwss.power_down_front_end(dc, i); + dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; + dc->hwss.disable_plane(dc, + &dc->current_state->res_ctx.pipe_ctx[i]); } } @@ -1888,7 +1838,7 @@ static void dce110_reset_hw_ctx_wrap( if (old_clk) old_clk->funcs->cs_power_down(old_clk); - dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); + dc->hwss.disable_plane(dc, pipe_ctx_old); pipe_ctx_old->stream = NULL; } @@ -2113,8 +2063,8 @@ enum dc_status dce110_apply_ctx_to_hw( context, dc); - if (dc->hwss.power_on_front_end) - dc->hwss.power_on_front_end(dc, pipe_ctx, context); + if (dc->hwss.enable_plane) + dc->hwss.enable_plane(dc, pipe_ctx, context); if (DC_OK != status) return status; @@ -2279,8 +2229,7 @@ static void set_plane_config( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment - == true) { + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = pipe_ctx->stream->output_color_space; @@ -2458,20 +2407,16 @@ static void dce110_enable_timing_synchronization( for (i = 1 /* skip the master */; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( - grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group); - - + grouped_pipes[i]->stream_res.tg, + gsl_params.gsl_group); for (i = 1 /* skip the master */; i < group_size; i++) { DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); - /* Regardless of success of the wait above, remove the reset or - * the driver will start timing out on Display requests. */ - DC_SYNC_INFO("GSL: disabling trigger-reset.\n"); - grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg); + grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( + grouped_pipes[i]->stream_res.tg); } - /* GSL Vblank synchronization is a one time sync mechanism, assumption * is that the sync'ed displays will not drift out of sync over time*/ DC_SYNC_INFO("GSL: Restoring register states.\n"); @@ -2481,6 +2426,39 @@ static void dce110_enable_timing_synchronization( DC_SYNC_INFO("GSL: Set-up complete.\n"); } +static void dce110_enable_per_frame_crtc_position_reset( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + struct dcp_gsl_params gsl_params = { 0 }; + int i; + + gsl_params.gsl_group = 0; + gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst; + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( + grouped_pipes[i]->stream_res.tg, &gsl_params); + + DC_SYNC_INFO("GSL: enabling trigger-reset\n"); + + for (i = 1; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( + grouped_pipes[i]->stream_res.tg, + gsl_params.gsl_master, + &grouped_pipes[i]->stream->triggered_crtc_reset); + + DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); + for (i = 1; i < group_size; i++) + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); + + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); + +} + static void init_hw(struct dc *dc) { int i; @@ -2513,6 +2491,10 @@ static void init_hw(struct dc *dc) * required signal (which may be different from the * default signal on connector). */ struct dc_link *link = dc->links[i]; + + if (link->link_enc->connector.id == CONNECTOR_ID_EDP) + dc->hwss.edp_power_control(link, true); + link->link_enc->funcs->hw_init(link->link_enc); } @@ -2567,6 +2549,10 @@ void dce110_fill_display_configs( ASSERT(pipe_ctx != NULL); + /* only notify active stream */ + if (stream->dpms_off) + continue; + num_cfgs++; cfg->signal = pipe_ctx->stream->signal; cfg->pipe_idx = pipe_ctx->pipe_idx; @@ -2722,8 +2708,7 @@ static void dce110_program_front_end_for_pipe( struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; - struct pipe_ctx *cur_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; unsigned int i; memset(&tbl_entry, 0, sizeof(tbl_entry)); @@ -2816,10 +2801,8 @@ static void dce110_program_front_end_for_pipe( /* Moved programming gamma from dc to hwss */ if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } dm_logger_write(dc->ctx->logger, LOG_SURFACE, @@ -2866,16 +2849,19 @@ static void dce110_apply_ctx_for_surface( int num_planes, struct dc_state *context) { - int i, be_idx; + int i; if (num_planes == 0) return; - be_idx = -1; for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; - break; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (stream == pipe_ctx->stream) { + if (!pipe_ctx->top_pipe && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, true); } } @@ -2895,13 +2881,28 @@ static void dce110_apply_ctx_for_surface( context->stream_count); dce110_program_front_end_for_pipe(dc, pipe_ctx); + + dc->hwss.update_plane_addr(dc, pipe_ctx); + program_surface_visibility(dc, pipe_ctx); } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if ((stream == pipe_ctx->stream) && + (!pipe_ctx->top_pipe) && + (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) + dc->hwss.pipe_control_lock(dc, pipe_ctx, false); + } } -static void dce110_power_down_fe(struct dc *dc, int fe_idx) +static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; + /* Do not power down fe when stream is active on dce*/ if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) return; @@ -2961,13 +2962,14 @@ static const struct hw_sequencer_funcs dce110_funcs = { .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dce110_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .enable_stream = dce110_enable_stream, .disable_stream = dce110_disable_stream, .unblank_stream = dce110_unblank_stream, .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, .enable_display_power_gating = dce110_enable_display_power_gating, - .power_down_front_end = dce110_power_down_fe, + .disable_plane = dce110_power_down_fe, .pipe_control_lock = dce_pipe_control_lock, .set_bandwidth = dce110_set_bandwidth, .set_drr = set_drr, @@ -2980,6 +2982,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .pplib_apply_display_requirements = pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control, }; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index 4d72bb99be93..2dd6ac637572 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -70,8 +70,8 @@ uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); void hwss_edp_power_control( - struct link_encoder *enc, - bool power_up); + struct dc_link *link, + bool power_up); void hwss_edp_backlight_control( struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c index a06c6024deb4..7bab8c6d2a73 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c @@ -237,26 +237,14 @@ static void program_size_and_rotation( if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270) { - uint32_t swap; - swap = local_size.video.luma_size.x; - local_size.video.luma_size.x = - local_size.video.luma_size.y; - local_size.video.luma_size.y = swap; - - swap = local_size.video.luma_size.width; - local_size.video.luma_size.width = - local_size.video.luma_size.height; - local_size.video.luma_size.height = swap; - - swap = local_size.video.chroma_size.x; - local_size.video.chroma_size.x = - local_size.video.chroma_size.y; - local_size.video.chroma_size.y = swap; - - swap = local_size.video.chroma_size.width; - local_size.video.chroma_size.width = - local_size.video.chroma_size.height; - local_size.video.chroma_size.height = swap; + swap(local_size.video.luma_size.x, + local_size.video.luma_size.y); + swap(local_size.video.luma_size.width, + local_size.video.luma_size.height); + swap(local_size.video.chroma_size.x, + local_size.video.chroma_size.y); + swap(local_size.video.chroma_size.width, + local_size.video.chroma_size.height); } value = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c index e98ed3058ea2..9b65b77e8823 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c @@ -175,7 +175,7 @@ static void regamma_config_regions_and_segments( value = 0; set_reg_field_value( value, - params->arr_points[2].custom_float_slope, + params->arr_points[1].custom_float_slope, GAMMA_CORR_CNTLA_END_CNTL2, GAMMA_CORR_CNTLA_EXP_REGION_END_BASE); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 61adb8174ce0..5228ee78f7e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1156,6 +1156,7 @@ static bool construct( dc->caps.max_downscale_ratio = 150; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 4befce6cd87a..25ca72139e5f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -1224,26 +1224,46 @@ void dce110_timing_generator_setup_global_swap_lock( /* This pipe will belong to GSL Group zero. */ set_reg_field_value(value, - 1, - DCP_GSL_CONTROL, - DCP_GSL0_EN); + 1, + DCP_GSL_CONTROL, + DCP_GSL0_EN); set_reg_field_value(value, - gsl_params->gsl_master == tg->inst, - DCP_GSL_CONTROL, - DCP_GSL_MASTER_EN); + gsl_params->gsl_master == tg->inst, + DCP_GSL_CONTROL, + DCP_GSL_MASTER_EN); set_reg_field_value(value, - HFLIP_READY_DELAY, - DCP_GSL_CONTROL, - DCP_GSL_HSYNC_FLIP_FORCE_DELAY); + HFLIP_READY_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_FORCE_DELAY); /* Keep signal low (pending high) during 6 lines. * Also defines minimum interval before re-checking signal. */ set_reg_field_value(value, - HFLIP_CHECK_DELAY, - DCP_GSL_CONTROL, - DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + HFLIP_CHECK_DELAY, + DCP_GSL_CONTROL, + DCP_GSL_HSYNC_FLIP_CHECK_DELAY); + + dm_write_reg(tg->ctx, CRTC_REG(mmDCP_GSL_CONTROL), value); + value = 0; + + set_reg_field_value(value, + gsl_params->gsl_master, + DCIO_GSL0_CNTL, + DCIO_GSL0_VSYNC_SEL); + + set_reg_field_value(value, + 0, + DCIO_GSL0_CNTL, + DCIO_GSL0_TIMING_SYNC_SEL); + + set_reg_field_value(value, + 0, + DCIO_GSL0_CNTL, + DCIO_GSL0_GLOBAL_UNLOCK_SEL); + + dm_write_reg(tg->ctx, CRTC_REG(mmDCIO_GSL0_CNTL), value); { @@ -1253,38 +1273,38 @@ void dce110_timing_generator_setup_global_swap_lock( CRTC_REG(mmCRTC_V_TOTAL)); set_reg_field_value(value, - 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ - DCP_GSL_CONTROL, - DCP_GSL_SYNC_SOURCE); + 0,/* DCP_GSL_PURPOSE_SURFACE_FLIP */ + DCP_GSL_CONTROL, + DCP_GSL_SYNC_SOURCE); /* Checkpoint relative to end of frame */ check_point = get_reg_field_value(value_crtc_vtotal, - CRTC_V_TOTAL, - CRTC_V_TOTAL); + CRTC_V_TOTAL, + CRTC_V_TOTAL); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_GSL_WINDOW), 0); } set_reg_field_value(value, - 1, - DCP_GSL_CONTROL, - DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); + 1, + DCP_GSL_CONTROL, + DCP_GSL_DELAY_SURFACE_UPDATE_PENDING); dm_write_reg(tg->ctx, address, value); /********************************************************************/ address = CRTC_REG(mmCRTC_GSL_CONTROL); - value = 0; + value = dm_read_reg(tg->ctx, address); set_reg_field_value(value, - check_point - FLIP_READY_BACK_LOOKUP, - CRTC_GSL_CONTROL, - CRTC_GSL_CHECK_LINE_NUM); + check_point - FLIP_READY_BACK_LOOKUP, + CRTC_GSL_CONTROL, + CRTC_GSL_CHECK_LINE_NUM); set_reg_field_value(value, - VFLIP_READY_DELAY, - CRTC_GSL_CONTROL, - CRTC_GSL_FORCE_DELAY); + VFLIP_READY_DELAY, + CRTC_GSL_CONTROL, + CRTC_GSL_FORCE_DELAY); dm_write_reg(tg->ctx, address, value); } @@ -1555,6 +1575,138 @@ void dce110_timing_generator_enable_reset_trigger( dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); } +void dce110_timing_generator_enable_crtc_reset( + struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp) +{ + uint32_t value = 0; + uint32_t rising_edge = 0; + uint32_t falling_edge = 0; + struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); + + /* Setup trigger edge */ + switch (crtc_tp->event) { + case CRTC_EVENT_VSYNC_RISING: + rising_edge = 1; + break; + + case CRTC_EVENT_VSYNC_FALLING: + falling_edge = 1; + break; + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); + + set_reg_field_value(value, + source_tg_inst, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); + + set_reg_field_value(value, + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); + + set_reg_field_value(value, + rising_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_RISING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + falling_edge, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); + + /**************************************************************/ + + switch (crtc_tp->delay) { + case TRIGGER_DELAY_NEXT_LINE: + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 0, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 0, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 2, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + break; + + case TRIGGER_DELAY_NEXT_PIXEL: + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 0, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value); + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); + + set_reg_field_value(value, + 2, /* force H count to H_TOTAL and V count to V_TOTAL */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); + + set_reg_field_value(value, + 1, /* TriggerB - we never use TriggerA */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_TRIG_SEL); + + set_reg_field_value(value, + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + break; + } + + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE)); + + set_reg_field_value(value, + 2, + CRTC_MASTER_UPDATE_MODE, + MASTER_UPDATE_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); +} void dce110_timing_generator_disable_reset_trigger( struct timing_generator *tg) { @@ -1564,34 +1716,48 @@ void dce110_timing_generator_disable_reset_trigger( value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); set_reg_field_value(value, - 0, /* force counter now mode is disabled */ - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_MODE); + 0, /* force counter now mode is disabled */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_MODE); set_reg_field_value(value, - 1, /* clear trigger status */ - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_CLEAR); + 1, /* clear trigger status */ + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_CLEAR); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL), value); + value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + + set_reg_field_value(value, + 1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR); + + set_reg_field_value(value, + 0, + CRTC_VERT_SYNC_CONTROL, + CRTC_AUTO_FORCE_VSYNC_MODE); + + dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_VERT_SYNC_CONTROL), value); + /********************************************************************/ value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL)); set_reg_field_value(value, - TRIGGER_SOURCE_SELECT_LOGIC_ZERO, - CRTC_TRIGB_CNTL, - CRTC_TRIGB_SOURCE_SELECT); + TRIGGER_SOURCE_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_SOURCE_SELECT); set_reg_field_value(value, - TRIGGER_POLARITY_SELECT_LOGIC_ZERO, - CRTC_TRIGB_CNTL, - CRTC_TRIGB_POLARITY_SELECT); + TRIGGER_POLARITY_SELECT_LOGIC_ZERO, + CRTC_TRIGB_CNTL, + CRTC_TRIGB_POLARITY_SELECT); set_reg_field_value(value, - 1, /* clear trigger status */ - CRTC_TRIGB_CNTL, - CRTC_TRIGB_CLEAR); + 1, /* clear trigger status */ + CRTC_TRIGB_CNTL, + CRTC_TRIGB_CLEAR); dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_TRIGB_CNTL), value); } @@ -1611,10 +1777,16 @@ bool dce110_timing_generator_did_triggered_reset_occur( struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); uint32_t value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_FORCE_COUNT_NOW_CNTL)); - - return get_reg_field_value(value, - CRTC_FORCE_COUNT_NOW_CNTL, - CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; + uint32_t value1 = dm_read_reg(tg->ctx, + CRTC_REG(mmCRTC_VERT_SYNC_CONTROL)); + bool force = get_reg_field_value(value, + CRTC_FORCE_COUNT_NOW_CNTL, + CRTC_FORCE_COUNT_NOW_OCCURRED) != 0; + bool vert_sync = get_reg_field_value(value1, + CRTC_VERT_SYNC_CONTROL, + CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED) != 0; + + return (force || vert_sync); } /** @@ -1928,6 +2100,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = { .setup_global_swap_lock = dce110_timing_generator_setup_global_swap_lock, .enable_reset_trigger = dce110_timing_generator_enable_reset_trigger, + .enable_crtc_reset = dce110_timing_generator_enable_crtc_reset, .disable_reset_trigger = dce110_timing_generator_disable_reset_trigger, .tear_down_global_swap_lock = dce110_timing_generator_tear_down_global_swap_lock, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 82737dea6984..232747c7c60b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -174,6 +174,12 @@ void dce110_timing_generator_setup_global_swap_lock( void dce110_timing_generator_tear_down_global_swap_lock( struct timing_generator *tg); +/* Reset crtc position on master VSync */ +void dce110_timing_generator_enable_crtc_reset( + struct timing_generator *tg, + int source, + struct crtc_trigger_info *crtc_tp); + /* Reset slave controllers on master VSync */ void dce110_timing_generator_enable_reset_trigger( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c index 1a0b54d6034e..75d029742f96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c @@ -31,9 +31,9 @@ #include "dce110/dce110_hw_sequencer.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" #include "reg_helper.h" #define CTX \ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 5c48c22d9d98..57cd67359567 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -54,10 +54,10 @@ #include "dce/dce_abm.h" #include "dce/dce_dmcu.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" -#include "vega10/NBIO/nbio_6_1_offset.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" +#include "nbio/nbio_6_1_offset.h" #include "reg_helper.h" #include "dce100/dce100_resource.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 2502182d5e82..0aa60e5727e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -25,9 +25,9 @@ #include "dm_services.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" #include "dc_types.h" #include "dc_bios_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 9c18efd3446f..8f2bd56f3461 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -957,6 +957,7 @@ static bool dce81_construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * @@ -1121,6 +1122,7 @@ static bool dce83_construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; + dc->caps.is_apu = true; /************************************************* * Create resources * diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index ebeb88283a14..a6ca1f97f748 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -4,7 +4,8 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \ dcn10_hubp.o dcn10_mpc.o \ - dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o + dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \ + dcn10_hubbub.o AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 74e7c82bdc76..8df3945370cf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -178,37 +178,17 @@ void dpp_reset(struct dpp *dpp_base) dpp->filter_h = NULL; dpp->filter_v = NULL; - /* set boundary mode to 0 */ - REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0); + memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); + memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); } static void dpp1_cm_set_regamma_pwl( - struct dpp *dpp_base, const struct pwl_params *params) -{ - struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - - dpp1_cm_power_on_regamma_lut(dpp_base, true); - dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); - - if (dpp->is_write_to_ram_a_safe) - dpp1_cm_program_regamma_luta_settings(dpp_base, params); - else - dpp1_cm_program_regamma_lutb_settings(dpp_base, params); - - dpp1_cm_program_regamma_lut( - dpp_base, params->rgb_resulted, params->hw_points_num); -} - -static void dpp1_cm_set_regamma_mode( - struct dpp *dpp_base, - enum opp_regamma mode) + struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); uint32_t re_mode = 0; - uint32_t obuf_bypass = 0; /* need for pipe split */ - uint32_t obuf_hupscale = 0; switch (mode) { case OPP_REGAMMA_BYPASS: @@ -221,17 +201,29 @@ static void dpp1_cm_set_regamma_mode( re_mode = 2; break; case OPP_REGAMMA_USER: + re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; + if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) + break; + + dpp1_cm_power_on_regamma_lut(dpp_base, true); + dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); + + if (dpp->is_write_to_ram_a_safe) + dpp1_cm_program_regamma_luta_settings(dpp_base, params); + else + dpp1_cm_program_regamma_lutb_settings(dpp_base, params); + + dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, + params->hw_points_num); + dpp->pwl_data = *params; + re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; break; default: break; } - REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); - REG_UPDATE_2(OBUF_CONTROL, - OBUF_BYPASS, obuf_bypass, - OBUF_H_2X_UPSCALE_EN, obuf_hupscale); } static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ @@ -264,8 +256,10 @@ static void dpp1_set_degamma_format_float( void dpp1_cnv_setup ( struct dpp *dpp_base, - enum surface_pixel_format input_format, - enum expansion_mode mode) + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space) { uint32_t pixel_format; uint32_t alpha_en; @@ -275,8 +269,10 @@ void dpp1_cnv_setup ( bool is_float; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); bool force_disable_cursor = false; + struct out_csc_color_matrix tbl_entry; + int i = 0; - dpp1_setup_format_flags(input_format, &fmt); + dpp1_setup_format_flags(format, &fmt); alpha_en = 1; pixel_format = 0; color_space = COLOR_SPACE_SRGB; @@ -306,7 +302,7 @@ void dpp1_cnv_setup ( dpp1_set_degamma_format_float(dpp_base, is_float); - switch (input_format) { + switch (format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: pixel_format = 1; break; @@ -362,7 +358,23 @@ void dpp1_cnv_setup ( CNVC_SURFACE_PIXEL_FORMAT, pixel_format); REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); - dpp1_program_input_csc(dpp_base, color_space, select); + // if input adjustments exist, program icsc with those values + + if (input_csc_color_matrix.enable_adjustment + == true) { + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; + + tbl_entry.color_space = input_color_space; + + if (color_space >= COLOR_SPACE_YCBCR601) + select = INPUT_CSC_SELECT_ICSC; + else + select = INPUT_CSC_SELECT_BYPASS; + + dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); + } else + dpp1_program_input_csc(dpp_base, color_space, select, NULL); if (force_disable_cursor) { REG_UPDATE(CURSOR_CONTROL, @@ -426,20 +438,20 @@ static const struct dpp_funcs dcn10_dpp_funcs = { .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, .dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, - .opp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, - .opp_set_csc_default = dpp1_cm_set_output_csc_default, - .opp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, - .opp_program_regamma_lut = dpp1_cm_program_regamma_lut, - .opp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, - .opp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, - .opp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, - .opp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, - .opp_set_regamma_mode = dpp1_cm_set_regamma_mode, - .ipp_set_degamma = dpp1_set_degamma, - .ipp_program_input_lut = dpp1_program_input_lut, - .ipp_program_degamma_pwl = dpp1_set_degamma_pwl, - .ipp_setup = dpp1_cnv_setup, - .ipp_full_bypass = dpp1_full_bypass, + .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, + .dpp_set_csc_default = dpp1_cm_set_output_csc_default, + .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, + .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut, + .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, + .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, + .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, + .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, + .dpp_program_bias_and_scale = dpp1_program_bias_and_scale, + .dpp_set_degamma = dpp1_set_degamma, + .dpp_program_input_lut = dpp1_program_input_lut, + .dpp_program_degamma_pwl = dpp1_set_degamma_pwl, + .dpp_setup = dpp1_cnv_setup, + .dpp_full_bypass = dpp1_full_bypass, .set_cursor_attributes = dpp1_set_cursor_attributes, .set_cursor_position = dpp1_set_cursor_position, }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h index a9782b1aba47..ad71fb50f8a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h @@ -54,7 +54,6 @@ SRI(LB_MEMORY_CTRL, DSCL, id), \ SRI(DSCL_AUTOCAL, DSCL, id), \ SRI(SCL_BLACK_OFFSET, DSCL, id), \ - SRI(DSCL_CONTROL, DSCL, id), \ SRI(SCL_TAP_CONTROL, DSCL, id), \ SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ @@ -72,7 +71,6 @@ SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \ SRI(RECOUT_START, DSCL, id), \ SRI(RECOUT_SIZE, DSCL, id), \ - SRI(OBUF_CONTROL, DSCL, id), \ SRI(CM_ICSC_CONTROL, CM, id), \ SRI(CM_ICSC_C11_C12, CM, id), \ SRI(CM_ICSC_C33_C34, CM, id), \ @@ -127,6 +125,9 @@ SRI(CM_OCSC_CONTROL, CM, id), \ SRI(CM_OCSC_C11_C12, CM, id), \ SRI(CM_OCSC_C33_C34, CM, id), \ + SRI(CM_BNS_VALUES_R, CM, id), \ + SRI(CM_BNS_VALUES_G, CM, id), \ + SRI(CM_BNS_VALUES_B, CM, id), \ SRI(CM_MEM_PWR_CTRL, CM, id), \ SRI(CM_RGAM_LUT_DATA, CM, id), \ SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\ @@ -191,7 +192,6 @@ TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\ TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\ - TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ @@ -235,7 +235,6 @@ TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ - TF_SF(DSCL0_OBUF_CONTROL, OBUF_BYPASS, mask_sh), \ TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \ TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \ TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \ @@ -329,6 +328,12 @@ TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \ TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \ + TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \ TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \ TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \ TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \ @@ -387,7 +392,6 @@ TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \ TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \ TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \ - TF_SF(DSCL0_OBUF_CONTROL, OBUF_H_2X_UPSCALE_EN, mask_sh), \ TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \ TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \ TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \ @@ -431,7 +435,6 @@ type AUTOCAL_PIPE_ID; \ type SCL_BLACK_OFFSET_RGB_Y; \ type SCL_BLACK_OFFSET_CBCR; \ - type SCL_BOUNDARY_MODE; \ type SCL_V_NUM_TAPS; \ type SCL_H_NUM_TAPS; \ type SCL_V_NUM_TAPS_C; \ @@ -552,8 +555,6 @@ type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ type CM_RGAM_LUT_MODE; \ type CM_CMOUT_ROUND_TRUNC_MODE; \ - type OBUF_BYPASS; \ - type OBUF_H_2X_UPSCALE_EN; \ type CM_BLNDGAM_LUT_MODE; \ type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \ type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ @@ -913,6 +914,12 @@ type CM_ICSC_C12; \ type CM_ICSC_C33; \ type CM_ICSC_C34; \ + type CM_BNS_BIAS_R; \ + type CM_BNS_BIAS_G; \ + type CM_BNS_BIAS_B; \ + type CM_BNS_SCALE_R; \ + type CM_BNS_SCALE_G; \ + type CM_BNS_SCALE_B; \ type CM_DGAM_RAMB_EXP_REGION_START_B; \ type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \ type CM_DGAM_RAMB_EXP_REGION_START_G; \ @@ -1023,7 +1030,6 @@ struct dcn_dpp_registers { uint32_t LB_MEMORY_CTRL; uint32_t DSCL_AUTOCAL; uint32_t SCL_BLACK_OFFSET; - uint32_t DSCL_CONTROL; uint32_t SCL_TAP_CONTROL; uint32_t SCL_COEF_RAM_TAP_SELECT; uint32_t SCL_COEF_RAM_TAP_DATA; @@ -1085,7 +1091,6 @@ struct dcn_dpp_registers { uint32_t CM_RGAM_RAMA_REGION_32_33; uint32_t CM_RGAM_CONTROL; uint32_t CM_CMOUT_CONTROL; - uint32_t OBUF_CONTROL; uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; uint32_t CM_BLNDGAM_CONTROL; uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; @@ -1206,6 +1211,9 @@ struct dcn_dpp_registers { uint32_t CM_ICSC_CONTROL; uint32_t CM_ICSC_C11_C12; uint32_t CM_ICSC_C33_C34; + uint32_t CM_BNS_VALUES_R; + uint32_t CM_BNS_VALUES_G; + uint32_t CM_BNS_VALUES_B; uint32_t CM_DGAM_RAMB_START_CNTL_B; uint32_t CM_DGAM_RAMB_START_CNTL_G; uint32_t CM_DGAM_RAMB_START_CNTL_R; @@ -1266,6 +1274,8 @@ struct dcn10_dpp { int lb_memory_size; int lb_bits_per_entry; bool is_write_to_ram_a_safe; + struct scaler_data scl_data; + struct pwl_params pwl_data; }; enum dcn10_input_csc_select { @@ -1310,7 +1320,12 @@ void dpp1_power_on_degamma_lut( void dpp1_program_input_csc( struct dpp *dpp_base, enum dc_color_space color_space, - enum dcn10_input_csc_select select); + enum dcn10_input_csc_select select, + const struct out_csc_color_matrix *tbl_entry); + +void dpp1_program_bias_and_scale( + struct dpp *dpp_base, + struct dc_bias_and_scale *params); void dpp1_program_input_lut( struct dpp *dpp_base, @@ -1360,7 +1375,7 @@ void dpp1_cm_set_output_csc_adjustment( void dpp1_cm_set_output_csc_default( struct dpp *dpp_base, - const struct default_adjustment *default_adjust); + enum dc_color_space colorspace); void dpp1_cm_set_gamut_remap( struct dpp *dpp, @@ -1372,8 +1387,10 @@ void dpp1_dscl_set_scaler_manual_scale( void dpp1_cnv_setup ( struct dpp *dpp_base, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); void dpp1_full_bypass(struct dpp *dpp_base); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c index 40627c244bf5..4c90043e7b8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c @@ -117,8 +117,6 @@ static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = { 0x2568, 0x43ee, 0xdbb2} } }; - - static void program_gamut_remap( struct dcn10_dpp *dpp, const uint16_t *regval, @@ -223,70 +221,6 @@ void dpp1_cm_set_gamut_remap( } } -void dpp1_cm_set_output_csc_default( - struct dpp *dpp_base, - const struct default_adjustment *default_adjust) -{ - - struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); - uint32_t ocsc_mode = 0; - - if (default_adjust != NULL) { - switch (default_adjust->out_color_space) { - case COLOR_SPACE_SRGB: - case COLOR_SPACE_2020_RGB_FULLRANGE: - ocsc_mode = 0; - break; - case COLOR_SPACE_SRGB_LIMITED: - case COLOR_SPACE_2020_RGB_LIMITEDRANGE: - ocsc_mode = 1; - break; - case COLOR_SPACE_YCBCR601: - case COLOR_SPACE_YCBCR601_LIMITED: - ocsc_mode = 2; - break; - case COLOR_SPACE_YCBCR709: - case COLOR_SPACE_YCBCR709_LIMITED: - case COLOR_SPACE_2020_YCBCR: - ocsc_mode = 3; - break; - case COLOR_SPACE_UNKNOWN: - default: - break; - } - } - - REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); - -} - -static void dpp1_cm_get_reg_field( - struct dcn10_dpp *dpp, - struct xfer_func_reg *reg) -{ - reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; - reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; - reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; - reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; - - reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; - reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; - reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; - reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; - reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; - reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; - reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; - reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; - reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; - reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; - reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; - reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; -} - static void dpp1_cm_program_color_matrix( struct dcn10_dpp *dpp, const struct out_csc_color_matrix *tbl_entry) @@ -328,6 +262,57 @@ static void dpp1_cm_program_color_matrix( } } +void dpp1_cm_set_output_csc_default( + struct dpp *dpp_base, + enum dc_color_space colorspace) +{ + + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + struct out_csc_color_matrix tbl_entry; + int i, j; + int arr_size = sizeof(output_csc_matrix) / sizeof(struct output_csc_matrix); + uint32_t ocsc_mode = 4; + + tbl_entry.color_space = colorspace; + + for (i = 0; i < arr_size; i++) + if (output_csc_matrix[i].color_space == colorspace) { + for (j = 0; j < 12; j++) + tbl_entry.regval[j] = output_csc_matrix[i].regval[j]; + break; + } + + REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); + dpp1_cm_program_color_matrix(dpp, &tbl_entry); +} + +static void dpp1_cm_get_reg_field( + struct dcn10_dpp *dpp, + struct xfer_func_reg *reg) +{ + reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; + reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; + reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; + reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; + reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; + reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; + reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; + + reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; + reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; + reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; + reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; + reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; + reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; + reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; + reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; + reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; + reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B; + reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; + reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; +} + void dpp1_cm_set_output_csc_adjustment( struct dpp *dpp_base, const struct out_csc_color_matrix *tbl_entry) @@ -367,34 +352,31 @@ void dpp1_cm_set_output_csc_adjustment( dpp1_cm_program_color_matrix(dpp, tbl_entry); } -void dpp1_cm_power_on_regamma_lut( - struct dpp *dpp_base, - bool power_on) +void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, + bool power_on) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + REG_SET(CM_MEM_PWR_CTRL, 0, - RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); + RGAM_MEM_PWR_FORCE, power_on == true ? 0:1); } -void dpp1_cm_program_regamma_lut( - struct dpp *dpp_base, - const struct pwl_result_data *rgb, - uint32_t num) +void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, + const struct pwl_result_data *rgb, + uint32_t num) { uint32_t i; struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + for (i = 0 ; i < num; i++) { REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); - REG_SET(CM_RGAM_LUT_DATA, 0, - CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); + REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg); } @@ -473,7 +455,8 @@ void dpp1_cm_program_regamma_lutb_settings( void dpp1_program_input_csc( struct dpp *dpp_base, enum dc_color_space color_space, - enum dcn10_input_csc_select select) + enum dcn10_input_csc_select select, + const struct out_csc_color_matrix *tbl_entry) { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); int i; @@ -487,15 +470,19 @@ void dpp1_program_input_csc( return; } - for (i = 0; i < arr_size; i++) - if (dcn10_input_csc_matrix[i].color_space == color_space) { - regval = dcn10_input_csc_matrix[i].regval; - break; + if (tbl_entry == NULL) { + for (i = 0; i < arr_size; i++) + if (dcn10_input_csc_matrix[i].color_space == color_space) { + regval = dcn10_input_csc_matrix[i].regval; + break; + } + + if (regval == NULL) { + BREAK_TO_DEBUGGER(); + return; } - - if (regval == NULL) { - BREAK_TO_DEBUGGER(); - return; + } else { + regval = tbl_entry->regval; } if (select == INPUT_CSC_SELECT_COMA) @@ -530,6 +517,27 @@ void dpp1_program_input_csc( } } +//keep here for now, decide multi dce support later +void dpp1_program_bias_and_scale( + struct dpp *dpp_base, + struct dc_bias_and_scale *params) +{ + struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); + + REG_SET_2(CM_BNS_VALUES_R, 0, + CM_BNS_SCALE_R, params->scale_red, + CM_BNS_BIAS_R, params->bias_red); + + REG_SET_2(CM_BNS_VALUES_G, 0, + CM_BNS_SCALE_G, params->scale_green, + CM_BNS_BIAS_G, params->bias_green); + + REG_SET_2(CM_BNS_VALUES_B, 0, + CM_BNS_SCALE_B, params->scale_blue, + CM_BNS_BIAS_B, params->bias_blue); + +} + /*program de gamma RAM B*/ void dpp1_program_degamma_lutb_settings( struct dpp *dpp_base, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index cbad36410b32..3eb824debf43 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -648,6 +648,13 @@ void dpp1_dscl_set_scaler_manual_scale( bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN && scl_data->format <= PIXEL_FORMAT_VIDEO_END; + if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) + return; + + PERF_TRACE(); + + dpp->scl_data = *scl_data; + /* Recout */ dpp1_dscl_set_recout(dpp, &scl_data->recout); @@ -699,4 +706,5 @@ void dpp1_dscl_set_scaler_manual_scale( SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); + PERF_TRACE(); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c new file mode 100644 index 000000000000..eb8317187f30 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -0,0 +1,516 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services.h" +#include "dcn10_hubp.h" +#include "dcn10_hubbub.h" +#include "reg_helper.h" + +#define CTX \ + hubbub->ctx +#define REG(reg)\ + hubbub->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hubbub->shifts->field_name, hubbub->masks->field_name + +void hubbub1_wm_read_state(struct hubbub *hubbub, + struct dcn_hubbub_wm *wm) +{ + struct dcn_hubbub_wm_set *s; + + memset(wm, 0, sizeof(struct dcn_hubbub_wm)); + + s = &wm->sets[0]; + s->wm_set = 0; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); + } + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); + + s = &wm->sets[1]; + s->wm_set = 1; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); + } + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); + + s = &wm->sets[2]; + s->wm_set = 2; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); + } + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); + + s = &wm->sets[3]; + s->wm_set = 3; + s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); + s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { + s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); + s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); + } + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); +} + +bool hubbub1_verify_allow_pstate_change_high( + struct hubbub *hubbub) +{ + /* pstate latency is ~20us so if we wait over 40us and pstate allow + * still not asserted, we are probably stuck and going to hang + * + * TODO: Figure out why it takes ~100us on linux + * pstate takes around ~100us on linux. Unknown currently as to + * why it takes that long on linux + */ + static unsigned int pstate_wait_timeout_us = 200; + static unsigned int pstate_wait_expected_timeout_us = 40; + static unsigned int max_sampled_pstate_wait_us; /* data collection */ + static bool forced_pstate_allow; /* help with revert wa */ + + unsigned int debug_index = 0x7; + unsigned int debug_data; + unsigned int i; + + if (forced_pstate_allow) { + /* we hacked to force pstate allow to prevent hang last time + * we verify_allow_pstate_change_high. so disable force + * here so we can check status + */ + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0); + forced_pstate_allow = false; + } + + /* description "3-0: Pipe0 cursor0 QOS + * 7-4: Pipe1 cursor0 QOS + * 11-8: Pipe2 cursor0 QOS + * 15-12: Pipe3 cursor0 QOS + * 16: Pipe0 Plane0 Allow Pstate Change + * 17: Pipe1 Plane0 Allow Pstate Change + * 18: Pipe2 Plane0 Allow Pstate Change + * 19: Pipe3 Plane0 Allow Pstate Change + * 20: Pipe0 Plane1 Allow Pstate Change + * 21: Pipe1 Plane1 Allow Pstate Change + * 22: Pipe2 Plane1 Allow Pstate Change + * 23: Pipe3 Plane1 Allow Pstate Change + * 24: Pipe0 cursor0 Allow Pstate Change + * 25: Pipe1 cursor0 Allow Pstate Change + * 26: Pipe2 cursor0 Allow Pstate Change + * 27: Pipe3 cursor0 Allow Pstate Change + * 28: WB0 Allow Pstate Change + * 29: WB1 Allow Pstate Change + * 30: Arbiter's allow_pstate_change + * 31: SOC pstate change request + */ + + REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index); + + for (i = 0; i < pstate_wait_timeout_us; i++) { + debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); + + if (debug_data & (1 << 30)) { + + if (i > pstate_wait_expected_timeout_us) + dm_logger_write(hubbub->ctx->logger, LOG_WARNING, + "pstate took longer than expected ~%dus\n", + i); + + return true; + } + if (max_sampled_pstate_wait_us < i) + max_sampled_pstate_wait_us = i; + + udelay(1); + } + + /* force pstate allow to prevent system hang + * and break to debugger to investigate + */ + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1, + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); + forced_pstate_allow = true; + + dm_logger_write(hubbub->ctx->logger, LOG_WARNING, + "pstate TEST_DEBUG_DATA: 0x%X\n", + debug_data); + + return false; +} + +static uint32_t convert_and_clamp( + uint32_t wm_ns, + uint32_t refclk_mhz, + uint32_t clamp_value) +{ + uint32_t ret_val = 0; + ret_val = wm_ns * refclk_mhz; + ret_val /= 1000; + + if (ret_val > clamp_value) + ret_val = clamp_value; + + return ret_val; +} + + +void hubbub1_program_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz) +{ + uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0; + /* + * Need to clamp to max of the register values (i.e. no wrap) + * for dcn1, all wm registers are 21-bit wide + */ + uint32_t prog_wm_value; + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0); + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); + + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.urgent_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.pte_meta_urgent_ns, prog_wm_value); + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + prog_wm_value = convert_and_clamp( + watermarks->a.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); + + + /* clock state B */ + prog_wm_value = convert_and_clamp( + watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.pte_meta_urgent_ns, prog_wm_value); + + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_B calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + prog_wm_value = convert_and_clamp( + watermarks->b.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" + "HW register value = 0x%x\n", + watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); + + /* clock state C */ + prog_wm_value = convert_and_clamp( + watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.urgent_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.pte_meta_urgent_ns, prog_wm_value); + + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_C calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + prog_wm_value = convert_and_clamp( + watermarks->c.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" + "HW register value = 0x%x\n", + watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); + + /* clock state D */ + prog_wm_value = convert_and_clamp( + watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.urgent_ns, prog_wm_value); + + prog_wm_value = convert_and_clamp( + watermarks->d.pte_meta_urgent_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.pte_meta_urgent_ns, prog_wm_value); + + + if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_ENTER_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.cstate_exit_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "SR_EXIT_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n", + watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); + } + + + prog_wm_value = convert_and_clamp( + watermarks->d.cstate_pstate.pstate_change_ns, + refclk_mhz, 0x1fffff); + REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); + dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS, + "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" + "HW register value = 0x%x\n\n", + watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); + + REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); + + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); + +#if 0 + REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); +#endif +} + +void hubbub1_update_dchub( + struct hubbub *hubbub, + struct dchub_init_data *dh_data) +{ + /* TODO: port code from dal2 */ + switch (dh_data->fb_mode) { + case FRAME_BUFFER_MODE_ZFB_ONLY: + /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ + REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, + SDPIF_FB_TOP, 0); + + REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, + SDPIF_FB_BASE, 0x0FFFF); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + + dh_data->zfb_size_in_byte - 1) >> 22); + break; + case FRAME_BUFFER_MODE_LOCAL_ONLY: + /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, + SDPIF_AGP_BASE, 0); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, + SDPIF_AGP_BOT, 0X03FFFF); + + REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, + SDPIF_AGP_TOP, 0); + break; + default: + break; + } + + dh_data->dchub_initialzied = true; + dh_data->dchub_info_valid = false; +} + +void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) +{ + uint32_t watermark_change_req; + + REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req); + + if (watermark_change_req) + watermark_change_req = 0; + else + watermark_change_req = 1; + + REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, + DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); +} + +static const struct hubbub_funcs hubbub1_funcs = { + .update_dchub = hubbub1_update_dchub +}; + +void hubbub1_construct(struct hubbub *hubbub, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask) +{ + hubbub->ctx = ctx; + + hubbub->funcs = &hubbub1_funcs; + + hubbub->regs = hubbub_regs; + hubbub->shifts = hubbub_shift; + hubbub->masks = hubbub_mask; + +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h new file mode 100644 index 000000000000..d5c97844312f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -0,0 +1,214 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBBUB_DCN10_H__ +#define __DC_HUBBUB_DCN10_H__ + +#include "core_types.h" + +#define HUBHUB_REG_LIST_DCN()\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\ + SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ + SR(DCHUBBUB_ARB_SAT_LEVEL),\ + SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_TEST_DEBUG_INDEX), \ + SR(DCHUBBUB_TEST_DEBUG_DATA) + +#define HUBBUB_SR_WATERMARK_REG_LIST()\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D) + +#define HUBBUB_REG_LIST_DCN10(id)\ + HUBHUB_REG_LIST_DCN(), \ + HUBBUB_SR_WATERMARK_REG_LIST(), \ + SR(DCHUBBUB_SDPIF_FB_TOP),\ + SR(DCHUBBUB_SDPIF_FB_BASE),\ + SR(DCHUBBUB_SDPIF_FB_OFFSET),\ + SR(DCHUBBUB_SDPIF_AGP_BASE),\ + SR(DCHUBBUB_SDPIF_AGP_BOT),\ + SR(DCHUBBUB_SDPIF_AGP_TOP) + +struct dcn_hubbub_registers { + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C; + uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D; + uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D; + uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D; + uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL; + uint32_t DCHUBBUB_ARB_SAT_LEVEL; + uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND; + uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; + uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL; + uint32_t DCHUBBUB_TEST_DEBUG_INDEX; + uint32_t DCHUBBUB_TEST_DEBUG_DATA; + uint32_t DCHUBBUB_SDPIF_FB_TOP; + uint32_t DCHUBBUB_SDPIF_FB_BASE; + uint32_t DCHUBBUB_SDPIF_FB_OFFSET; + uint32_t DCHUBBUB_SDPIF_AGP_BASE; + uint32_t DCHUBBUB_SDPIF_AGP_BOT; + uint32_t DCHUBBUB_SDPIF_AGP_TOP; + uint32_t DCHUBBUB_CRC_CTRL; +}; + +/* set field name */ +#define HUBBUB_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + + +#define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh) + +#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\ + HUBBUB_MASK_SH_LIST_DCN(mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh) + +#define DCN_HUBBUB_REG_FIELD_LIST(type) \ + type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ + type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\ + type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\ + type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\ + type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\ + type DCHUBBUB_ARB_SAT_LEVEL;\ + type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\ + type DCHUBBUB_GLOBAL_TIMER_REFDIV;\ + type SDPIF_FB_TOP;\ + type SDPIF_FB_BASE;\ + type SDPIF_FB_OFFSET;\ + type SDPIF_AGP_BASE;\ + type SDPIF_AGP_BOT;\ + type SDPIF_AGP_TOP + + +struct dcn_hubbub_shift { + DCN_HUBBUB_REG_FIELD_LIST(uint8_t); +}; + +struct dcn_hubbub_mask { + DCN_HUBBUB_REG_FIELD_LIST(uint32_t); +}; + +struct dc; + +struct dcn_hubbub_wm_set { + uint32_t wm_set; + uint32_t data_urgent; + uint32_t pte_meta_urgent; + uint32_t sr_enter; + uint32_t sr_exit; + uint32_t dram_clk_chanage; +}; + +struct dcn_hubbub_wm { + struct dcn_hubbub_wm_set sets[4]; +}; + +struct hubbub_funcs { + void (*update_dchub)( + struct hubbub *hubbub, + struct dchub_init_data *dh_data); +}; + +struct hubbub { + const struct hubbub_funcs *funcs; + struct dc_context *ctx; + const struct dcn_hubbub_registers *regs; + const struct dcn_hubbub_shift *shifts; + const struct dcn_hubbub_mask *masks; +}; + +void hubbub1_update_dchub( + struct hubbub *hubbub, + struct dchub_init_data *dh_data); + +bool hubbub1_verify_allow_pstate_change_high( + struct hubbub *hubbub); + +void hubbub1_program_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz); + +void hubbub1_toggle_watermark_change_req( + struct hubbub *hubbub); + +void hubbub1_wm_read_state(struct hubbub *hubbub, + struct dcn_hubbub_wm *wm); + +void hubbub1_construct(struct hubbub *hubbub, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index b13dee64e0ce..584e82cc5df3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -29,14 +29,14 @@ #include "dcn10_hubp.h" #define REG(reg)\ - hubp1->mi_regs->reg + hubp1->hubp_regs->reg #define CTX \ hubp1->base.ctx #undef FN #define FN(reg_name, field_name) \ - hubp1->mi_shift->field_name, hubp1->mi_mask->field_name + hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name void hubp1_set_blank(struct hubp *hubp, bool blank) { @@ -56,6 +56,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) } } +static void hubp1_disconnect(struct hubp *hubp) +{ + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + + REG_UPDATE(DCHUBP_CNTL, + HUBP_TTU_DISABLE, 1); +} + static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank) { struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); @@ -933,6 +941,7 @@ static struct hubp_funcs dcn10_hubp_funcs = { .set_hubp_blank_en = hubp1_set_hubp_blank_en, .set_cursor_attributes = hubp1_cursor_set_attributes, .set_cursor_position = hubp1_cursor_set_position, + .hubp_disconnect = hubp1_disconnect, }; /*****************************************/ @@ -943,15 +952,15 @@ void dcn10_hubp_construct( struct dcn10_hubp *hubp1, struct dc_context *ctx, uint32_t inst, - const struct dcn_mi_registers *mi_regs, - const struct dcn_mi_shift *mi_shift, - const struct dcn_mi_mask *mi_mask) + const struct dcn_mi_registers *hubp_regs, + const struct dcn_mi_shift *hubp_shift, + const struct dcn_mi_mask *hubp_mask) { hubp1->base.funcs = &dcn10_hubp_funcs; hubp1->base.ctx = ctx; - hubp1->mi_regs = mi_regs; - hubp1->mi_shift = mi_shift; - hubp1->mi_mask = mi_mask; + hubp1->hubp_regs = hubp_regs; + hubp1->hubp_shift = hubp_shift; + hubp1->hubp_mask = hubp_mask; hubp1->base.inst = inst; hubp1->base.opp_id = 0xf; hubp1->base.mpcc_id = 0xf; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h index 66db453c801b..a7834dd50716 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h @@ -30,7 +30,7 @@ #define TO_DCN10_HUBP(hubp)\ container_of(hubp, struct dcn10_hubp, base) -#define MI_REG_LIST_DCN(id)\ +#define HUBP_REG_LIST_DCN(id)\ SRI(DCHUBP_CNTL, HUBP, id),\ SRI(HUBPREQ_DEBUG_DB, HUBP, id),\ SRI(DCSURF_ADDR_CONFIG, HUBP, id),\ @@ -98,8 +98,8 @@ SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) -#define MI_REG_LIST_DCN10(id)\ - MI_REG_LIST_DCN(id),\ +#define HUBP_REG_LIST_DCN10(id)\ + HUBP_REG_LIST_DCN(id),\ SRI(PREFETCH_SETTINS, HUBPREQ, id),\ SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\ SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\ @@ -235,169 +235,170 @@ struct dcn_mi_registers { uint32_t CURSOR_DST_OFFSET; }; -#define MI_SF(reg_name, field_name, post_fix)\ +#define HUBP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix -#define MI_MASK_SH_LIST_DCN(mask_sh)\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ - MI_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ - MI_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ - MI_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ - MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ - MI_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ - MI_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ - MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ - MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ - MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ - MI_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ - MI_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ - MI_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ - MI_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ - MI_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ - MI_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ - MI_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ - MI_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ - MI_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ - MI_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ - MI_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ - MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ - MI_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) - -#define MI_MASK_SH_LIST_DCN10(mask_sh)\ - MI_MASK_SH_LIST_DCN(mask_sh),\ - MI_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ - MI_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ - MI_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ - MI_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ - MI_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ - MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ - MI_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ - MI_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ - MI_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ - MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ - MI_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ - MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ - MI_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ - MI_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) - -#define DCN_MI_REG_FIELD_LIST(type) \ +#define HUBP_MASK_SH_LIST_DCN(mask_sh)\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_SE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_RB_PER_SE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ + HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\ + HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\ + HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\ + HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\ + HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) + +#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ + HUBP_MASK_SH_LIST_DCN(mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\ + HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\ + HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\ + HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\ + HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_DST_Y_OFFSET, mask_sh), \ + HUBP_SF(HUBPREQ0_CURSOR_SETTINS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ + HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh) + + +#define DCN_HUBP_REG_FIELD_LIST(type) \ type HUBP_BLANK_EN;\ type HUBP_TTU_DISABLE;\ type HUBP_NO_OUTSTANDING_REQ;\ @@ -577,18 +578,18 @@ struct dcn_mi_registers { type OUTPUT_FP struct dcn_mi_shift { - DCN_MI_REG_FIELD_LIST(uint8_t); + DCN_HUBP_REG_FIELD_LIST(uint8_t); }; struct dcn_mi_mask { - DCN_MI_REG_FIELD_LIST(uint32_t); + DCN_HUBP_REG_FIELD_LIST(uint32_t); }; struct dcn10_hubp { struct hubp base; - const struct dcn_mi_registers *mi_regs; - const struct dcn_mi_shift *mi_shift; - const struct dcn_mi_mask *mi_mask; + const struct dcn_mi_registers *hubp_regs; + const struct dcn_mi_shift *hubp_shift; + const struct dcn_mi_mask *hubp_mask; }; void hubp1_program_surface_config( @@ -656,9 +657,9 @@ void dcn10_hubp_construct( struct dcn10_hubp *hubp1, struct dc_context *ctx, uint32_t inst, - const struct dcn_mi_registers *mi_regs, - const struct dcn_mi_shift *mi_shift, - const struct dcn_mi_mask *mi_mask); + const struct dcn_mi_registers *hubp_regs, + const struct dcn_mi_shift *hubp_shift, + const struct dcn_mi_mask *hubp_mask); struct dcn_hubp_state { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 961ad5c3b454..8e2ddbc2129c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -31,6 +31,7 @@ #include "dce110/dce110_hw_sequencer.h" #include "dce/dce_hwseq.h" #include "abm.h" +#include "dmcu.h" #include "dcn10/dcn10_timing_generator.h" #include "dcn10/dcn10_dpp.h" #include "dcn10/dcn10_mpc.h" @@ -41,6 +42,7 @@ #include "reg_helper.h" #include "custom_float.h" #include "dcn10_hubp.h" +#include "dcn10_hubbub.h" #define CTX \ hws->ctx @@ -51,18 +53,8 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -static void log_mpc_crc(struct dc *dc) -{ - struct dc_context *dc_ctx = dc->ctx; - struct dce_hwseq *hws = dc->hwseq; - - if (REG(MPC_CRC_RESULT_GB)) - DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", - REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); - if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) - DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", - REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); -} +#define DTN_INFO_MICRO_SEC(ref_cycle) \ + print_microsec(dc_ctx, ref_cycle) void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle) { @@ -75,67 +67,27 @@ void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle) us_x10 % frac); } -#define DTN_INFO_MICRO_SEC(ref_cycle) \ - print_microsec(dc_ctx, ref_cycle) -struct dcn_hubbub_wm_set { - uint32_t wm_set; - uint32_t data_urgent; - uint32_t pte_meta_urgent; - uint32_t sr_enter; - uint32_t sr_exit; - uint32_t dram_clk_chanage; -}; +static void log_mpc_crc(struct dc *dc) +{ + struct dc_context *dc_ctx = dc->ctx; + struct dce_hwseq *hws = dc->hwseq; -struct dcn_hubbub_wm { - struct dcn_hubbub_wm_set sets[4]; -}; + if (REG(MPC_CRC_RESULT_GB)) + DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n", + REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR)); + if (REG(DPP_TOP0_DPP_CRC_VAL_B_A)) + DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n", + REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G)); +} -static void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, - struct dcn_hubbub_wm *wm) -{ - struct dcn_hubbub_wm_set *s; - - s = &wm->sets[0]; - s->wm_set = 0; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); - - s = &wm->sets[1]; - s->wm_set = 1; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); - - s = &wm->sets[2]; - s->wm_set = 2; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); - - s = &wm->sets[3]; - s->wm_set = 3; - s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); - s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); - s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); - s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); - s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); -} - -static void dcn10_log_hubbub_state(struct dc *dc) +void dcn10_log_hubbub_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct dcn_hubbub_wm wm; int i; - dcn10_hubbub_wm_read_state(dc->hwseq, &wm); + hubbub1_wm_read_state(dc->res_pool->hubbub, &wm); DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t " "sr_enter \t sr_exit \t dram_clk_change \n"); @@ -156,7 +108,7 @@ static void dcn10_log_hubbub_state(struct dc *dc) DTN_INFO("\n"); } -static void dcn10_log_hw_state(struct dc *dc) +void dcn10_log_hw_state(struct dc *dc) { struct dc_context *dc_ctx = dc->ctx; struct resource_pool *pool = dc->res_pool; @@ -240,97 +192,6 @@ static void dcn10_log_hw_state(struct dc *dc) DTN_INFO_END(); } -static void verify_allow_pstate_change_high( - struct dce_hwseq *hws) -{ - /* pstate latency is ~20us so if we wait over 40us and pstate allow - * still not asserted, we are probably stuck and going to hang - * - * TODO: Figure out why it takes ~100us on linux - * pstate takes around ~100us on linux. Unknown currently as to - * why it takes that long on linux - */ - static unsigned int pstate_wait_timeout_us = 200; - static unsigned int pstate_wait_expected_timeout_us = 40; - static unsigned int max_sampled_pstate_wait_us; /* data collection */ - static bool forced_pstate_allow; /* help with revert wa */ - static bool should_log_hw_state; /* prevent hw state log by default */ - - unsigned int debug_index = 0x7; - unsigned int debug_data; - unsigned int i; - - if (forced_pstate_allow) { - /* we hacked to force pstate allow to prevent hang last time - * we verify_allow_pstate_change_high. so disable force - * here so we can check status - */ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 0); - forced_pstate_allow = false; - } - - /* description "3-0: Pipe0 cursor0 QOS - * 7-4: Pipe1 cursor0 QOS - * 11-8: Pipe2 cursor0 QOS - * 15-12: Pipe3 cursor0 QOS - * 16: Pipe0 Plane0 Allow Pstate Change - * 17: Pipe1 Plane0 Allow Pstate Change - * 18: Pipe2 Plane0 Allow Pstate Change - * 19: Pipe3 Plane0 Allow Pstate Change - * 20: Pipe0 Plane1 Allow Pstate Change - * 21: Pipe1 Plane1 Allow Pstate Change - * 22: Pipe2 Plane1 Allow Pstate Change - * 23: Pipe3 Plane1 Allow Pstate Change - * 24: Pipe0 cursor0 Allow Pstate Change - * 25: Pipe1 cursor0 Allow Pstate Change - * 26: Pipe2 cursor0 Allow Pstate Change - * 27: Pipe3 cursor0 Allow Pstate Change - * 28: WB0 Allow Pstate Change - * 29: WB1 Allow Pstate Change - * 30: Arbiter's allow_pstate_change - * 31: SOC pstate change request - */ - - REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index); - - for (i = 0; i < pstate_wait_timeout_us; i++) { - debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA); - - if (debug_data & (1 << 30)) { - - if (i > pstate_wait_expected_timeout_us) - dm_logger_write(hws->ctx->logger, LOG_WARNING, - "pstate took longer than expected ~%dus\n", - i); - - return; - } - if (max_sampled_pstate_wait_us < i) - max_sampled_pstate_wait_us = i; - - udelay(1); - } - - /* force pstate allow to prevent system hang - * and break to debugger to investigate - */ - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, 1, - DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); - forced_pstate_allow = true; - - if (should_log_hw_state) { - dcn10_log_hw_state(hws->ctx->dc); - } - - dm_logger_write(hws->ctx->logger, LOG_WARNING, - "pstate TEST_DEBUG_DATA: 0x%X\n", - debug_data); - BREAK_TO_DEBUGGER(); -} - static void enable_dppclk( struct dce_hwseq *hws, uint8_t plane_id, @@ -432,312 +293,6 @@ static void dpp_pg_control( } } -static uint32_t convert_and_clamp( - uint32_t wm_ns, - uint32_t refclk_mhz, - uint32_t clamp_value) -{ - uint32_t ret_val = 0; - ret_val = wm_ns * refclk_mhz; - ret_val /= 1000; - - if (ret_val > clamp_value) - ret_val = clamp_value; - - return ret_val; -} - -static void program_watermarks( - struct dce_hwseq *hws, - struct dcn_watermark_set *watermarks, - unsigned int refclk_mhz) -{ - uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0; - /* - * Need to clamp to max of the register values (i.e. no wrap) - * for dcn1, all wm registers are 21-bit wide - */ - uint32_t prog_wm_value; - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0); - - /* Repeat for water mark set A, B, C and D. */ - /* clock state A */ - prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value); - - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.urgent_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.pte_meta_urgent_ns, prog_wm_value); - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - prog_wm_value = convert_and_clamp( - watermarks->a.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value); - - - /* clock state B */ - prog_wm_value = convert_and_clamp( - watermarks->b.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.pte_meta_urgent_ns, prog_wm_value); - - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_B calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - prog_wm_value = convert_and_clamp( - watermarks->b.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n" - "HW register value = 0x%x\n", - watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value); - - /* clock state C */ - prog_wm_value = convert_and_clamp( - watermarks->c.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.urgent_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.pte_meta_urgent_ns, prog_wm_value); - - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_C calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - prog_wm_value = convert_and_clamp( - watermarks->c.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n" - "HW register value = 0x%x\n", - watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value); - - /* clock state D */ - prog_wm_value = convert_and_clamp( - watermarks->d.urgent_ns, refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.urgent_ns, prog_wm_value); - - prog_wm_value = convert_and_clamp( - watermarks->d.pte_meta_urgent_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "PTE_META_URGENCY_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.pte_meta_urgent_ns, prog_wm_value); - - - if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_ENTER_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value); - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.cstate_exit_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "SR_EXIT_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n", - watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value); - } - - - prog_wm_value = convert_and_clamp( - watermarks->d.cstate_pstate.pstate_change_ns, - refclk_mhz, 0x1fffff); - REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value); - dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS, - "DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n" - "HW register value = 0x%x\n\n", - watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value); - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); - - REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL, - DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); - REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, - DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); - - REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, - DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); - -#if 0 - REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1); -#endif -} - - -static void dcn10_update_dchub( - struct dce_hwseq *hws, - struct dchub_init_data *dh_data) -{ - /* TODO: port code from dal2 */ - switch (dh_data->fb_mode) { - case FRAME_BUFFER_MODE_ZFB_ONLY: - /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ - REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, - SDPIF_FB_TOP, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, - SDPIF_FB_BASE, 0x0FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + - dh_data->zfb_size_in_byte - 1) >> 22); - break; - case FRAME_BUFFER_MODE_LOCAL_ONLY: - /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, - SDPIF_AGP_BASE, 0); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, - SDPIF_AGP_BOT, 0X03FFFF); - - REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, - SDPIF_AGP_TOP, 0); - break; - default: - break; - } - - dh_data->dchub_initialzied = true; - dh_data->dchub_info_valid = false; -} - static void hubp_pg_control( struct dce_hwseq *hws, unsigned int hubp_inst, @@ -808,11 +363,8 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; - int pwr_status = 0; - REG_GET(DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, &pwr_status); - /* Don't need to blank if hubp is power gated*/ - if (pwr_status == 2) + if (!hws->wa_state.DEGVIDCN10_253_applied) return; hubp->funcs->set_blank(hubp, true); @@ -823,16 +375,29 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) hubp_pg_control(hws, 0, false); REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); + + hws->wa_state.DEGVIDCN10_253_applied = false; } static void apply_DEGVIDCN10_253_wa(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; struct hubp *hubp = dc->res_pool->hubps[0]; + int i; if (dc->debug.disable_stutter) return; + if (!hws->wa.DEGVIDCN10_253) + return; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!dc->res_pool->hubps[i]->power_gated) + return; + } + + /* all pipe power gated, apply work around to enable stutter. */ + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); @@ -841,6 +406,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) IP_REQUEST_EN, 0); hubp->funcs->set_hubp_blank_en(hubp, false); + hws->wa_state.DEGVIDCN10_253_applied = true; } static void bios_golden_init(struct dc *dc) @@ -859,87 +425,6 @@ static void bios_golden_init(struct dc *dc) } } -static void dcn10_init_hw(struct dc *dc) -{ - int i; - struct abm *abm = dc->res_pool->abm; - struct dce_hwseq *hws = dc->hwseq; - - if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { - REG_WRITE(REFCLK_CNTL, 0); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - if (!dc->debug.disable_clock_gate) { - /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - - REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); - } - - enable_power_gating_plane(dc->hwseq, true); - return; - } - /* end of FPGA. Below if real ASIC */ - - bios_golden_init(dc); - - disable_vga(dc->hwseq); - - for (i = 0; i < dc->link_count; i++) { - /* Power up AND update implementation according to the - * required signal (which may be different from the - * default signal on connector). - */ - struct dc_link *link = dc->links[i]; - - link->link_enc->funcs->hw_init(link->link_enc); - } - - for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct dpp *dpp = dc->res_pool->dpps[i]; - struct timing_generator *tg = dc->res_pool->timing_generators[i]; - - dpp->funcs->dpp_reset(dpp); - dc->res_pool->mpc->funcs->remove( - dc->res_pool->mpc, &(dc->res_pool->opps[i]->mpc_tree), - dc->res_pool->opps[i]->inst, i); - - /* Blank controller using driver code instead of - * command table. - */ - tg->funcs->set_blank(tg, true); - hwss_wait_for_blank_complete(tg); - } - - for (i = 0; i < dc->res_pool->audio_count; i++) { - struct audio *audio = dc->res_pool->audios[i]; - - audio->funcs->hw_init(audio); - } - - if (abm != NULL) { - abm->funcs->init_backlight(abm); - abm->funcs->abm_init(abm); - } - - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - if (!dc->debug.disable_clock_gate) { - /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - - REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); - } - - enable_power_gating_plane(dc->hwseq, true); -} - static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, struct dc_state *context, @@ -952,7 +437,6 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( false:true; bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY; - /* by upper caller loop, pipe0 is parent pipe and be called first. * back end is set up by for pipe0. Other children pipe share back end * with pipe 0. No program is needed. @@ -1070,10 +554,23 @@ static void reset_back_end_for_pipe( pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); } +static void dcn10_verify_allow_pstate_change_high(struct dc *dc) +{ + static bool should_log_hw_state; /* prevent hw state log by default */ + + if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { + if (should_log_hw_state) { + dcn10_log_hw_state(dc); + } + + BREAK_TO_DEBUGGER(); + } +} + /* trigger HW to start disconnect plane from stream on the next vsync */ -static void plane_atomic_disconnect(struct dc *dc, - int fe_idx) +static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; struct hubp *hubp = dc->res_pool->hubps[fe_idx]; struct mpc *mpc = dc->res_pool->mpc; int opp_id, z_idx; @@ -1096,57 +593,23 @@ static void plane_atomic_disconnect(struct dc *dc, if (opp_id == dc->res_pool->pipe_count) return; - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - hubp->funcs->dcc_control(hubp, false, false); - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), - dc->res_pool->opps[opp_id]->inst, fe_idx); -} - -/* disable HW used by plane. - * note: cannot disable until disconnect is complete */ -static void plane_atomic_disable(struct dc *dc, - int fe_idx) -{ - struct dce_hwseq *hws = dc->hwseq; - struct hubp *hubp = dc->res_pool->hubps[fe_idx]; - struct mpc *mpc = dc->res_pool->mpc; - int opp_id = hubp->opp_id; + dc->res_pool->opps[opp_id]->inst, fe_idx); - if (opp_id == 0xf) - return; - - mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); - dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false; - /*dm_logger_write(dc->ctx->logger, LOG_ERROR, - "[debug_mpo: atomic disable finished on mpcc %d]\n", - fe_idx);*/ - - hubp->funcs->set_blank(hubp, true); + if (hubp->funcs->hubp_disconnect) + hubp->funcs->hubp_disconnect(hubp); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - REG_UPDATE(HUBP_CLK_CNTL[fe_idx], - HUBP_CLOCK_ENABLE, 0); - REG_UPDATE(DPP_CONTROL[fe_idx], - DPP_CLOCK_ENABLE, 0); - - if (dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) - REG_UPDATE(OPP_PIPE_CONTROL[opp_id], - OPP_PIPE_CLOCK_EN, 0); + dcn10_verify_allow_pstate_change_high(dc); - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + pipe_ctx->stream = NULL; + memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); + memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); + pipe_ctx->top_pipe = NULL; + pipe_ctx->bottom_pipe = NULL; + pipe_ctx->plane_state = NULL; } -/* - * kill power to plane hw - * note: cannot power down until plane is disable - */ static void plane_atomic_power_down(struct dc *dc, int fe_idx) { struct dce_hwseq *hws = dc->hwseq; @@ -1162,125 +625,197 @@ static void plane_atomic_power_down(struct dc *dc, int fe_idx) IP_REQUEST_EN, 0); dm_logger_write(dc->ctx->logger, LOG_DEBUG, "Power gated front end %d\n", fe_idx); - - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); } } - -static void reset_front_end( - struct dc *dc, - int fe_idx) +/* disable HW used by plane. + * note: cannot disable until disconnect is complete + */ +static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { + int fe_idx = pipe_ctx->pipe_idx; struct dce_hwseq *hws = dc->hwseq; - struct timing_generator *tg; - int opp_id = dc->res_pool->hubps[fe_idx]->opp_id; + struct hubp *hubp = dc->res_pool->hubps[fe_idx]; + struct mpc *mpc = dc->res_pool->mpc; + int opp_id = hubp->opp_id; + struct output_pixel_processor *opp; - /*Already reset*/ - if (opp_id == 0xf) - return; + if (opp_id != 0xf) { + mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id); + opp = dc->res_pool->opps[hubp->opp_id]; + opp->mpcc_disconnect_pending[hubp->mpcc_id] = false; + hubp->funcs->set_blank(hubp, true); + } - tg = dc->res_pool->timing_generators[opp_id]; - tg->funcs->lock(tg); + REG_UPDATE(HUBP_CLK_CNTL[fe_idx], + HUBP_CLOCK_ENABLE, 0); + REG_UPDATE(DPP_CONTROL[fe_idx], + DPP_CLOCK_ENABLE, 0); - plane_atomic_disconnect(dc, fe_idx); + if (opp_id != 0xf && dc->res_pool->opps[opp_id]->mpc_tree.num_pipes == 0) + REG_UPDATE(OPP_PIPE_CONTROL[opp_id], + OPP_PIPE_CLOCK_EN, 0); - REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], VUPDATE_NO_LOCK_EVENT_CLEAR, 1); - tg->funcs->unlock(tg); + hubp->power_gated = true; - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(hws); + plane_atomic_power_down(dc, fe_idx); +} - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], - VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, - 1, 100000); +static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + if (dc->res_pool->hubps[pipe_ctx->pipe_idx]->power_gated) + return; - plane_atomic_disable(dc, fe_idx); + plane_atomic_disable(dc, pipe_ctx); + + apply_DEGVIDCN10_253_wa(dc); dm_logger_write(dc->ctx->logger, LOG_DC, - "Reset front end %d\n", - fe_idx); + "Power down front end %d\n", + pipe_ctx->pipe_idx); } -static void dcn10_power_down_fe(struct dc *dc, int fe_idx) +static void dcn10_init_hw(struct dc *dc) { + int i; + struct abm *abm = dc->res_pool->abm; + struct dmcu *dmcu = dc->res_pool->dmcu; struct dce_hwseq *hws = dc->hwseq; - struct dpp *dpp = dc->res_pool->dpps[fe_idx]; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct dc_state *context = dc->current_state; - reset_front_end(dc, fe_idx); + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { + REG_WRITE(REFCLK_CNTL, 0); + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); + REG_WRITE(DIO_MEM_PWR_CTRL, 0); - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 1); - dpp_pg_control(hws, fe_idx, false); - hubp_pg_control(hws, fe_idx, false); - dpp->funcs->dpp_reset(dpp); - REG_SET(DC_IP_REQUEST_CNTL, 0, - IP_REQUEST_EN, 0); - dm_logger_write(dc->ctx->logger, LOG_DEBUG, - "Power gated front end %d\n", fe_idx); + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); -} + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); -static void reset_hw_ctx_wrap( - struct dc *dc, - struct dc_state *context) -{ - int i; + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + + enable_power_gating_plane(dc->hwseq, true); + return; + } + /* end of FPGA. Below if real ASIC */ + + if (!dcb->funcs->is_accelerated_mode(dcb)) { + bios_golden_init(dc); + disable_vga(dc->hwseq); + } + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). + */ + struct dc_link *link = dc->links[i]; + + if (link->link_enc->connector.id == CONNECTOR_ID_EDP) + dc->hwss.edp_power_control(link, true); + + link->link_enc->funcs->hw_init(link->link_enc); + } - /* Reset Front End*/ - /* Lock*/ for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; + struct timing_generator *tg = dc->res_pool->timing_generators[i]; - if (cur_pipe_ctx->stream) + if (tg->funcs->is_tg_enabled(tg)) tg->funcs->lock(tg); } - /* Disconnect*/ - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *pipe_ctx_old = - &dc->current_state->res_ctx.pipe_ctx[i]; - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (!pipe_ctx->stream || - !pipe_ctx->plane_state || - pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + /* Blank controller using driver code instead of + * command table. + */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; - plane_atomic_disconnect(dc, i); + if (tg->funcs->is_tg_enabled(tg)) { + tg->funcs->set_blank(tg, true); + hwss_wait_for_blank_complete(tg); } } - /* Unlock*/ - for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; - if (cur_pipe_ctx->stream) + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct output_pixel_processor *opp = dc->res_pool->opps[i]; + struct mpc_tree_cfg *mpc_tree = &opp->mpc_tree; + struct hubp *hubp = dc->res_pool->hubps[i]; + + mpc_tree->dpp[0] = i; + mpc_tree->mpcc[0] = i; + mpc_tree->num_pipes = 1; + + pipe_ctx->stream_res.tg = tg; + pipe_ctx->pipe_idx = i; + + pipe_ctx->plane_res.hubp = hubp; + hubp->mpcc_id = i; + hubp->opp_id = dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i); + hubp->power_gated = false; + + plane_atomic_disconnect(dc, pipe_ctx); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + + if (tg->funcs->is_tg_enabled(tg)) tg->funcs->unlock(tg); } - /* Disable and Powerdown*/ - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *pipe_ctx_old = - &dc->current_state->res_ctx.pipe_ctx[i]; + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - /*if (!pipe_ctx_old->stream) - continue;*/ + dcn10_disable_plane(dc, pipe_ctx); - if (pipe_ctx->stream && pipe_ctx->plane_state - && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - continue; + pipe_ctx->stream_res.tg = NULL; + pipe_ctx->plane_res.hubp = NULL; + + tg->funcs->tg_init(tg); + } + + for (i = 0; i < dc->res_pool->audio_count; i++) { + struct audio *audio = dc->res_pool->audios[i]; + + audio->funcs->hw_init(audio); + } + + if (abm != NULL) { + abm->funcs->init_backlight(abm); + abm->funcs->abm_init(abm); + } + + if (dmcu != NULL) + dmcu->funcs->dmcu_init(dmcu); + + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - plane_atomic_disable(dc, i); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - if (!pipe_ctx->stream || !pipe_ctx->plane_state) - plane_atomic_power_down(dc, i); + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } + enable_power_gating_plane(dc->hwseq, true); +} + +static void reset_hw_ctx_wrap( + struct dc *dc, + struct dc_state *context) +{ + int i; + /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = @@ -1298,7 +833,6 @@ static void reset_hw_ctx_wrap( struct clock_source *old_clk = pipe_ctx_old->clock_source; reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); - if (old_clk) old_clk->funcs->cs_power_down(old_clk); } @@ -1332,21 +866,7 @@ static bool patch_address_for_sbs_tb_stereo( return false; } -static void toggle_watermark_change_req(struct dce_hwseq *hws) -{ - uint32_t watermark_change_req; - - REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, &watermark_change_req); - if (watermark_change_req) - watermark_change_req = 0; - else - watermark_change_req = 1; - - REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, - DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req); -} static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { @@ -1366,8 +886,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; } -static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) +static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { struct dpp *dpp_base = pipe_ctx->plane_res.dpp; const struct dc_transfer_func *tf = NULL; @@ -1380,34 +900,28 @@ static bool dcn10_set_input_transfer_func( tf = plane_state->in_transfer_func; if (plane_state->gamma_correction && dce_use_lut(plane_state)) - dpp_base->funcs->ipp_program_input_lut(dpp_base, - plane_state->gamma_correction); + dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); if (tf == NULL) - dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); else if (tf->type == TF_TYPE_PREDEFINED) { switch (tf->tf) { case TRANSFER_FUNCTION_SRGB: - dpp_base->funcs->ipp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_HW_sRGB); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); break; case TRANSFER_FUNCTION_BT709: - dpp_base->funcs->ipp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_HW_xvYCC); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); break; case TRANSFER_FUNCTION_LINEAR: - dpp_base->funcs->ipp_set_degamma(dpp_base, - IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); break; case TRANSFER_FUNCTION_PQ: - result = false; - break; default: result = false; break; } } else if (tf->type == TF_TYPE_BYPASS) { - dpp_base->funcs->ipp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); + dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); } else { /*TF_TYPE_DISTRIBUTED_POINTS*/ result = false; @@ -1431,26 +945,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 12; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[0].x, - &fmt, - &arr_points[0].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[0].x, &fmt, + &arr_points[0].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].offset, - &fmt, - &arr_points[0].custom_float_offset)) { + if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, + &arr_points[0].custom_float_offset)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[0].slope, - &fmt, - &arr_points[0].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, + &arr_points[0].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -1458,26 +966,20 @@ static bool convert_to_custom_float( fmt.mantissa_bits = 10; fmt.sign = false; - if (!convert_to_custom_float_format( - arr_points[1].x, - &fmt, - &arr_points[1].custom_float_x)) { + if (!convert_to_custom_float_format(arr_points[1].x, &fmt, + &arr_points[1].custom_float_x)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].y, - &fmt, - &arr_points[1].custom_float_y)) { + if (!convert_to_custom_float_format(arr_points[1].y, &fmt, + &arr_points[1].custom_float_y)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - arr_points[1].slope, - &fmt, - &arr_points[1].custom_float_slope)) { + if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, + &arr_points[1].custom_float_slope)) { BREAK_TO_DEBUGGER(); return false; } @@ -1486,50 +988,38 @@ static bool convert_to_custom_float( fmt.sign = true; while (i != hw_points_num) { - if (!convert_to_custom_float_format( - rgb->red, - &fmt, - &rgb->red_reg)) { + if (!convert_to_custom_float_format(rgb->red, &fmt, + &rgb->red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->green, - &fmt, - &rgb->green_reg)) { + if (!convert_to_custom_float_format(rgb->green, &fmt, + &rgb->green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->blue, - &fmt, - &rgb->blue_reg)) { + if (!convert_to_custom_float_format(rgb->blue, &fmt, + &rgb->blue_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_red, - &fmt, - &rgb->delta_red_reg)) { + if (!convert_to_custom_float_format(rgb->delta_red, &fmt, + &rgb->delta_red_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_green, - &fmt, - &rgb->delta_green_reg)) { + if (!convert_to_custom_float_format(rgb->delta_green, &fmt, + &rgb->delta_green_reg)) { BREAK_TO_DEBUGGER(); return false; } - if (!convert_to_custom_float_format( - rgb->delta_blue, - &fmt, - &rgb->delta_blue_reg)) { + if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, + &rgb->delta_blue_reg)) { BREAK_TO_DEBUGGER(); return false; } @@ -1544,8 +1034,9 @@ static bool convert_to_custom_float( #define MAX_LOW_POINT 25 #define NUMBER_SEGMENTS 32 -static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func - *output_tf, struct pwl_params *regamma_params) +static bool +dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, + struct pwl_params *regamma_params) { struct curve_points *arr_points; struct pwl_result_data *rgb_resulted; @@ -1561,10 +1052,11 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func int32_t i; uint32_t j, k, seg_distr[MAX_REGIONS_NUMBER], increment, start_index, hw_points; - if (output_tf == NULL || regamma_params == NULL || - output_tf->type == TF_TYPE_BYPASS) + if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) return false; + PERF_TRACE(); + arr_points = regamma_params->arr_points; rgb_resulted = regamma_params->rgb_resulted; hw_points = 0; @@ -1625,19 +1117,14 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func /* last point */ start_index = (segment_end + MAX_LOW_POINT) * NUMBER_SEGMENTS; - rgb_resulted[hw_points - 1].red = - output_tf->tf_pts.red[start_index]; - rgb_resulted[hw_points - 1].green = - output_tf->tf_pts.green[start_index]; - rgb_resulted[hw_points - 1].blue = - output_tf->tf_pts.blue[start_index]; + rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; + rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; + rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_start)); + dal_fixed31_32_from_int(segment_start)); arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); - arr_points[2].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2), - dal_fixed31_32_from_int(segment_end)); + dal_fixed31_32_from_int(segment_end)); y_r = rgb_resulted[0].red; y_g = rgb_resulted[0].green; @@ -1646,9 +1133,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b)); arr_points[0].y = y1_min; - arr_points[0].slope = dal_fixed31_32_div( - arr_points[0].y, - arr_points[0].x); + arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x); y_r = rgb_resulted[hw_points - 1].red; y_g = rgb_resulted[hw_points - 1].green; y_b = rgb_resulted[hw_points - 1].blue; @@ -1659,10 +1144,8 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b)); arr_points[1].y = y3_max; - arr_points[2].y = y3_max; arr_points[1].slope = dal_fixed31_32_zero; - arr_points[2].slope = dal_fixed31_32_zero; if (output_tf->tf == TRANSFER_FUNCTION_PQ) { /* for PQ, we want to have a straight line from last HW X point, @@ -1674,9 +1157,6 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func arr_points[1].slope = dal_fixed31_32_div( dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), dal_fixed31_32_sub(end_value, arr_points[1].x)); - arr_points[2].slope = dal_fixed31_32_div( - dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y), - dal_fixed31_32_sub(end_value, arr_points[1].x)); } regamma_params->hw_points_num = hw_points; @@ -1687,15 +1167,13 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; regamma_params->arr_curve_points[i].offset = - regamma_params->arr_curve_points[k]. - offset + (1 << seg_distr[k]); + regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); } i++; } if (seg_distr[k] != -1) - regamma_params->arr_curve_points[k].segments_num = - seg_distr[k]; + regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; rgb = rgb_resulted; rgb_plus_1 = rgb_resulted + 1; @@ -1710,15 +1188,9 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue)) rgb_plus_1->blue = rgb->blue; - rgb->delta_red = dal_fixed31_32_sub( - rgb_plus_1->red, - rgb->red); - rgb->delta_green = dal_fixed31_32_sub( - rgb_plus_1->green, - rgb->green); - rgb->delta_blue = dal_fixed31_32_sub( - rgb_plus_1->blue, - rgb->blue); + rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red); + rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green); + rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue); ++rgb_plus_1; ++rgb; @@ -1727,12 +1199,14 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func convert_to_custom_float(rgb_resulted, arr_points, hw_points); + PERF_TRACE(); + return true; } -static bool dcn10_set_output_transfer_func( - struct pipe_ctx *pipe_ctx, - const struct dc_stream_state *stream) +static bool +dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, + const struct dc_stream_state *stream) { struct dpp *dpp = pipe_ctx->plane_res.dpp; @@ -1742,18 +1216,21 @@ static bool dcn10_set_output_transfer_func( dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; if (stream->out_transfer_func && - stream->out_transfer_func->type == - TF_TYPE_PREDEFINED && - stream->out_transfer_func->tf == - TRANSFER_FUNCTION_SRGB) { - dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_SRGB); - } else if (dcn10_translate_regamma_to_hw_format( - stream->out_transfer_func, &dpp->regamma_params)) { - dpp->funcs->opp_program_regamma_pwl(dpp, &dpp->regamma_params); - dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_USER); - } else { - dpp->funcs->opp_set_regamma_mode(dpp, OPP_REGAMMA_BYPASS); - } + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) + dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB); + + /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full + * update. + */ + else if (dcn10_translate_regamma_to_hw_format( + stream->out_transfer_func, + &dpp->regamma_params)) { + dpp->funcs->dpp_program_regamma_pwl( + dpp, + &dpp->regamma_params, OPP_REGAMMA_USER); + } else + dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS); return true; } @@ -1772,7 +1249,7 @@ static void dcn10_pipe_control_lock( return; if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); if (lock) pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); @@ -1780,7 +1257,7 @@ static void dcn10_pipe_control_lock( pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } static bool wait_for_reset_trigger_to_occur( @@ -1833,14 +1310,15 @@ static void dcn10_enable_timing_synchronization( for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( - grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst); - + grouped_pipes[i]->stream_res.tg, + grouped_pipes[0]->stream_res.tg->inst); DC_SYNC_INFO("Waiting for trigger\n"); /* Need to get only check 1 pipe for having reset as all the others are * synchronized. Look at last pipe programmed to reset. */ + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg); for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( @@ -1849,7 +1327,30 @@ static void dcn10_enable_timing_synchronization( DC_SYNC_INFO("Sync complete\n"); } -static void print_rq_dlg_ttu( +static void dcn10_enable_per_frame_crtc_position_reset( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]) +{ + struct dc_context *dc_ctx = dc->ctx; + int i; + + DC_SYNC_INFO("Setting up\n"); + for (i = 0; i < group_size; i++) + grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( + grouped_pipes[i]->stream_res.tg, + grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst, + &grouped_pipes[i]->stream->triggered_crtc_reset); + + DC_SYNC_INFO("Waiting for trigger\n"); + + for (i = 1; i < group_size; i++) + wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); + + DC_SYNC_INFO("Multi-display sync is complete\n"); +} + +/*static void print_rq_dlg_ttu( struct dc *core_dc, struct pipe_ctx *pipe_ctx) { @@ -1970,19 +1471,104 @@ static void print_rq_dlg_ttu( pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear ); } +*/ + +static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, + struct vm_system_aperture_param *apt, + struct dce_hwseq *hws) +{ + PHYSICAL_ADDRESS_LOC physical_page_number; + uint32_t logical_addr_low; + uint32_t logical_addr_high; + + REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part); + REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part); + + REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, + LOGICAL_ADDR, &logical_addr_low); + + REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, + LOGICAL_ADDR, &logical_addr_high); + + apt->sys_default.quad_part = physical_page_number.quad_part << 12; + apt->sys_low.quad_part = (int64_t)logical_addr_low << 18; + apt->sys_high.quad_part = (int64_t)logical_addr_high << 18; +} + +/* Temporary read settings, future will get values from kmd directly */ +static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, + struct vm_context0_param *vm0, + struct dce_hwseq *hws) +{ + PHYSICAL_ADDRESS_LOC fb_base; + PHYSICAL_ADDRESS_LOC fb_offset; + uint32_t fb_base_value; + uint32_t fb_offset_value; + + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); + + REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); + REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part); + + REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part); + REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part); + + REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part); + REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part); + + REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part); + REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part); + + /* + * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space. + * Therefore we need to do + * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE + */ + fb_base.quad_part = (uint64_t)fb_base_value << 24; + fb_offset.quad_part = (uint64_t)fb_offset_value << 24; + vm0->pte_base.quad_part += fb_base.quad_part; + vm0->pte_base.quad_part -= fb_offset.quad_part; +} + + +static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp) +{ + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + struct vm_system_aperture_param apt = { {{ 0 } } }; + struct vm_context0_param vm0 = { { { 0 } } }; + + mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws); + mmhub_read_vm_context0_settings(hubp1, &vm0, hws); + + hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); + hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0); +} -static void dcn10_power_on_fe( +static void dcn10_enable_plane( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { - struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } + undo_DEGVIDCN10_253_wa(dc); + power_on_plane(dc->hwseq, pipe_ctx->pipe_idx); @@ -1995,6 +1581,7 @@ static void dcn10_power_on_fe( OPP_PIPE_CLOCK_EN, 1); /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ +/* TODO: enable/disable in dm as per update type. if (plane_state) { dm_logger_write(dc->ctx->logger, LOG_DC, "Pipe:%d 0x%x: addr hi:0x%x, " @@ -2030,9 +1617,12 @@ static void dcn10_power_on_fe( pipe_ctx->plane_res.scl_data.recout.y); print_rq_dlg_ttu(dc, pipe_ctx); } +*/ + if (dc->config.gpu_vm_support) + dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp); if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } } @@ -2085,8 +1675,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, int i; struct out_csc_color_matrix tbl_entry; - if (pipe_ctx->stream->csc_color_matrix.enable_adjustment - == true) { + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { enum dc_color_space color_space = pipe_ctx->stream->output_color_space; @@ -2096,9 +1685,66 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; - pipe_ctx->plane_res.dpp->funcs->opp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); + + if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) + pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, &tbl_entry); + } else { + if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL) + pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace); + } +} + +static void set_mpc_output_csc(struct dc *dc, + struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix, + int opp_id) +{ + struct mpc *mpc = dc->res_pool->mpc; + int i; + struct out_csc_color_matrix tbl_entry; + enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; + + + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { + //uint16_t matrix[12]; + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = matrix[i]; + tbl_entry.color_space = colorspace; + + if (mpc->funcs->set_output_csc != NULL) + mpc->funcs->set_output_csc(mpc, + opp_id, + &tbl_entry, + ocsc_mode); + } else { + if (mpc->funcs->set_ocsc_default != NULL) + mpc->funcs->set_ocsc_default(mpc, + opp_id, + colorspace, + ocsc_mode); } } + +static void program_output_csc(struct dc *dc, + struct pipe_ctx *pipe_ctx, + enum dc_color_space colorspace, + uint16_t *matrix, + int opp_id) +{ + if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) + program_csc_matrix(pipe_ctx, + colorspace, + matrix); + else + set_mpc_output_csc(dc, + pipe_ctx, + colorspace, + matrix, + opp_id); + +} + static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { if (pipe_ctx->plane_state->visible) @@ -2186,145 +1832,95 @@ static void dcn10_get_surface_visual_confirm_color( } } -static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, - struct vm_system_aperture_param *apt, - struct dce_hwseq *hws) +static uint16_t fixed_point_to_int_frac( + struct fixed31_32 arg, + uint8_t integer_bits, + uint8_t fractional_bits) { - PHYSICAL_ADDRESS_LOC physical_page_number; - uint32_t logical_addr_low; - uint32_t logical_addr_high; + int32_t numerator; + int32_t divisor = 1 << fractional_bits; - REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, - PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part); - REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, - PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part); + uint16_t result; - REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, - LOGICAL_ADDR, &logical_addr_low); + uint16_t d = (uint16_t)dal_fixed31_32_floor( + dal_fixed31_32_abs( + arg)); - REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, - LOGICAL_ADDR, &logical_addr_high); - - apt->sys_default.quad_part = physical_page_number.quad_part << 12; - apt->sys_low.quad_part = (int64_t)logical_addr_low << 18; - apt->sys_high.quad_part = (int64_t)logical_addr_high << 18; -} - -/* Temporary read settings, future will get values from kmd directly */ -static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, - struct vm_context0_param *vm0, - struct dce_hwseq *hws) -{ - PHYSICAL_ADDRESS_LOC fb_base; - PHYSICAL_ADDRESS_LOC fb_offset; - uint32_t fb_base_value; - uint32_t fb_offset_value; - - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); - - REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, - PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); - REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, - PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part); + if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) + numerator = (uint16_t)dal_fixed31_32_floor( + dal_fixed31_32_mul_int( + arg, + divisor)); + else { + numerator = dal_fixed31_32_floor( + dal_fixed31_32_sub( + dal_fixed31_32_from_int( + 1LL << integer_bits), + dal_fixed31_32_recip( + dal_fixed31_32_from_int( + divisor)))); + } - REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, - LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part); - REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, - LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part); + if (numerator >= 0) + result = (uint16_t)numerator; + else + result = (uint16_t)( + (1 << (integer_bits + fractional_bits + 1)) + numerator); - REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, - LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part); - REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, - LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part); + if ((result != 0) && dal_fixed31_32_lt( + arg, dal_fixed31_32_zero)) + result |= 1 << (integer_bits + fractional_bits); - REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, - PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part); - REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, - PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part); + return result; +} - /* - * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space. - * Therefore we need to do - * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR - * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE - */ - fb_base.quad_part = (uint64_t)fb_base_value << 24; - fb_offset.quad_part = (uint64_t)fb_offset_value << 24; - vm0->pte_base.quad_part += fb_base.quad_part; - vm0->pte_base.quad_part -= fb_offset.quad_part; +void build_prescale_params(struct dc_bias_and_scale *bias_and_scale, + const struct dc_plane_state *plane_state) +{ + if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN + && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID + && plane_state->input_csc_color_matrix.enable_adjustment + && plane_state->coeff_reduction_factor.value != 0) { + bias_and_scale->scale_blue = fixed_point_to_int_frac( + dal_fixed31_32_mul(plane_state->coeff_reduction_factor, + dal_fixed31_32_from_fraction(256, 255)), + 2, + 13); + bias_and_scale->scale_red = bias_and_scale->scale_blue; + bias_and_scale->scale_green = bias_and_scale->scale_blue; + } else { + bias_and_scale->scale_blue = 0x2000; + bias_and_scale->scale_red = 0x2000; + bias_and_scale->scale_green = 0x2000; + } } -static void dcn10_program_pte_vm(struct hubp *hubp, - enum surface_pixel_format format, - union dc_tiling_info *tiling_info, - enum dc_rotation_angle rotation, - struct dce_hwseq *hws) +static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) { - struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); - struct vm_system_aperture_param apt = { {{ 0 } } }; - struct vm_context0_param vm0 = { { { 0 } } }; - + struct dc_bias_and_scale bns_params = {0}; - mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws); - mmhub_read_vm_context0_settings(hubp1, &vm0, hws); + // program the input csc + dpp->funcs->dpp_setup(dpp, + plane_state->format, + EXPANSION_MODE_ZERO, + plane_state->input_csc_color_matrix, + COLOR_SPACE_YCBCR601_LIMITED); - hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt); - hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0); + //set scale and bias registers + build_prescale_params(&bns_params, plane_state); + if (dpp->funcs->dpp_program_bias_and_scale) + dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); } -static void update_dchubp_dpp( - struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_state *context) +static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) { - struct dce_hwseq *hws = dc->hwseq; - struct hubp *hubp = pipe_ctx->plane_res.hubp; - struct dpp *dpp = pipe_ctx->plane_res.dpp; - struct dc_plane_state *plane_state = pipe_ctx->plane_state; - union plane_size size = plane_state->plane_size; struct mpcc_cfg mpcc_cfg = {0}; + struct hubp *hubp = pipe_ctx->plane_res.hubp; struct pipe_ctx *top_pipe; - bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + bool per_pixel_alpha = + pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ - /* depends on DML calculation, DPP clock value may change dynamically */ - enable_dppclk( - dc->hwseq, - pipe_ctx->pipe_idx, - pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, - context->bw.dcn.calc_clk.dppclk_div); - dc->current_state->bw.dcn.cur_clk.dppclk_div = - context->bw.dcn.calc_clk.dppclk_div; - context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; - - /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG - * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. - * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG - */ - REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); - - hubp->funcs->hubp_setup( - hubp, - &pipe_ctx->dlg_regs, - &pipe_ctx->ttu_regs, - &pipe_ctx->rq_regs, - &pipe_ctx->pipe_dlg_param); - - size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; - - if (dc->config.gpu_vm_support) - dcn10_program_pte_vm( - pipe_ctx->plane_res.hubp, - plane_state->format, - &plane_state->tiling_info, - plane_state->rotation, - hws - ); - - dpp->funcs->ipp_setup(dpp, - plane_state->format, - EXPANSION_MODE_ZERO); mpcc_cfg.dpp_id = hubp->inst; mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst; @@ -2347,31 +1943,112 @@ static void update_dchubp_dpp( && per_pixel_alpha; hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, &mpcc_cfg); hubp->opp_id = mpcc_cfg.opp_id; +} + +static void update_scaler(struct pipe_ctx *pipe_ctx) +{ + bool per_pixel_alpha = + pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; + + /* TODO: proper fix once fpga works */ pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; /* scaler configuration */ pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); +} + +static void update_dchubp_dpp( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context) +{ + struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + union plane_size size = plane_state->plane_size; - hubp->funcs->mem_program_viewport(hubp, - &pipe_ctx->plane_res.scl_data.viewport, &pipe_ctx->plane_res.scl_data.viewport_c); + /* depends on DML calculation, DPP clock value may change dynamically */ + if (pipe_ctx->plane_state->update_flags.raw != 0) { + enable_dppclk( + dc->hwseq, + pipe_ctx->pipe_idx, + pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, + context->bw.dcn.calc_clk.dppclk_div); + dc->current_state->bw.dcn.cur_clk.dppclk_div = + context->bw.dcn.calc_clk.dppclk_div; + context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; + } - /*gamut remap*/ - program_gamut_remap(pipe_ctx); + /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG + * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. + * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG + */ + if (plane_state->update_flags.bits.full_update) { + REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); + + hubp->funcs->hubp_setup( + hubp, + &pipe_ctx->dlg_regs, + &pipe_ctx->ttu_regs, + &pipe_ctx->rq_regs, + &pipe_ctx->pipe_dlg_param); + } + + size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport; + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.bpp_change) + update_dpp(dpp, plane_state); + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change) + update_mpcc(dc, pipe_ctx); + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change || + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.position_change) { + update_scaler(pipe_ctx); + } + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.scaling_change) { + hubp->funcs->mem_program_viewport( + hubp, + &pipe_ctx->plane_res.scl_data.viewport, + &pipe_ctx->plane_res.scl_data.viewport_c); + } + + if (plane_state->update_flags.bits.full_update) { + /*gamut remap*/ + program_gamut_remap(pipe_ctx); + + program_output_csc(dc, + pipe_ctx, + pipe_ctx->stream->output_color_space, + pipe_ctx->stream->csc_color_matrix.matrix, + hubp->opp_id); + } - program_csc_matrix(pipe_ctx, - pipe_ctx->stream->output_color_space, - pipe_ctx->stream->csc_color_matrix.matrix); + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.horizontal_mirror_change || + plane_state->update_flags.bits.rotation_change || + plane_state->update_flags.bits.swizzle_change || + plane_state->update_flags.bits.bpp_change) { + hubp->funcs->hubp_program_surface_config( + hubp, + plane_state->format, + &plane_state->tiling_info, + &size, + plane_state->rotation, + &plane_state->dcc, + plane_state->horizontal_mirror); + } - hubp->funcs->hubp_program_surface_config( - hubp, - plane_state->format, - &plane_state->tiling_info, - &size, - plane_state->rotation, - &plane_state->dcc, - plane_state->horizontal_mirror); + hubp->power_gated = false; dc->hwss.update_plane_addr(dc, pipe_ctx); @@ -2385,23 +2062,8 @@ static void program_all_pipe_in_tree( struct pipe_ctx *pipe_ctx, struct dc_state *context) { - unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; - if (pipe_ctx->top_pipe == NULL) { - /* lock otg_master_update to process all pipes associated with - * this OTG. this is done only one time. - */ - /* watermark is for all pipes */ - program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz); - - if (dc->debug.sanity_checks) { - /* pstate stuck check after watermark update */ - verify_allow_pstate_change_high(dc->hwseq); - } - - pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); - pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset; pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start; pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset; @@ -2414,42 +2076,25 @@ static void program_all_pipe_in_tree( } if (pipe_ctx->plane_state != NULL) { - struct dc_cursor_position position = { 0 }; struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; - dcn10_power_on_fe(dc, pipe_ctx, context); - - /* temporary dcn1 wa: - * watermark update requires toggle after a/b/c/d sets are programmed - * if hubp is pg then wm value doesn't get properaged to hubp - * need to toggle after ungate to ensure wm gets to hubp. - * - * final solution: we need to get SMU to do the toggle as - * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have - * both driver and fw accessing same register - */ - toggle_watermark_change_req(dc->hwseq); + if (pipe_ctx->plane_state->update_flags.bits.full_update) + dcn10_enable_plane(dc, pipe_ctx, context); update_dchubp_dpp(dc, pipe_ctx, context); - /* TODO: this is a hack w/a for switching from mpo to pipe split */ - dc_stream_set_cursor_position(pipe_ctx->stream, &position); - - dc_stream_set_cursor_attributes(pipe_ctx->stream, - &pipe_ctx->stream->cursor_attributes); + if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) + dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); - if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) { - dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->plane_state); - dc->hwss.set_output_transfer_func( - pipe_ctx, pipe_ctx->stream); - } - } - - if (dc->debug.sanity_checks) { - /* pstate stuck check after each pipe is programmed */ - verify_allow_pstate_change_high(dc->hwseq); + /* dcn10_translate_regamma_to_hw_format takes 750us to finish + * only do gamma programming for full update. + * TODO: This can be further optimized/cleaned up + * Always call this for now since it does memcmp inside before + * doing heavy calculation and programming + */ + if (pipe_ctx->plane_state->update_flags.bits.full_update) + dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); } if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) @@ -2486,7 +2131,6 @@ static void dcn10_pplib_apply_display_requirements( static void optimize_shared_resources(struct dc *dc) { if (dc->current_state->stream_count == 0) { - apply_DEGVIDCN10_253_wa(dc); /* S0i2 message */ dcn10_pplib_apply_display_requirements(dc, dc->current_state); } @@ -2497,67 +2141,80 @@ static void optimize_shared_resources(struct dc *dc) static void ready_shared_resources(struct dc *dc, struct dc_state *context) { - if (dc->current_state->stream_count == 0 && - !dc->debug.disable_stutter) - undo_DEGVIDCN10_253_wa(dc); - /* S0i2 message */ if (dc->current_state->stream_count == 0 && context->stream_count != 0) dcn10_pplib_apply_display_requirements(dc, context); } +static struct pipe_ctx *find_top_pipe_for_stream( + struct dc *dc, + struct dc_state *context, + const struct dc_stream_state *stream) +{ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *old_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) + continue; + + if (pipe_ctx->stream != stream) + continue; + + if (!pipe_ctx->top_pipe) + return pipe_ctx; + } + return NULL; +} + static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, struct dc_state *context) { - int i, be_idx; + int i; + struct timing_generator *tg; + bool removed_pipe[4] = { false }; + unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; + bool program_water_mark = false; - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); + struct pipe_ctx *top_pipe_to_program = + find_top_pipe_for_stream(dc, context, stream); - be_idx = -1; - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (stream == context->res_ctx.pipe_ctx[i].stream) { - be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; - break; - } - } + if (!top_pipe_to_program) + return; - ASSERT(be_idx != -1); + tg = top_pipe_to_program->stream_res.tg; + + tg->funcs->lock(tg); if (num_planes == 0) { - for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { - struct pipe_ctx *old_pipe_ctx = - &dc->current_state->res_ctx.pipe_ctx[i]; - if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { - old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); - dcn10_power_down_fe(dc, old_pipe_ctx->pipe_idx); - } - } - return; + /* OTG blank before remove all front end */ + tg->funcs->set_blank(tg, true); } - /* reset unused mpcc */ + /* Disconnect unused mpcc */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - - if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) - continue; - /* * Powergate reused pipes that are not powergated * fairly hacky right now, using opp_id as indicator + * TODO: After move dc_post to dc_update, this will + * be removed. */ - if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { - if (pipe_ctx->plane_res.hubp->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) { - dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); + if (old_pipe_ctx->stream_res.tg == tg && + old_pipe_ctx->plane_res.hubp && + old_pipe_ctx->plane_res.hubp->opp_id != 0xf) { + dcn10_disable_plane(dc, pipe_ctx); /* * power down fe will unlock when calling reset, need * to lock it back here. Messy, need rework. @@ -2566,36 +2223,12 @@ static void dcn10_apply_ctx_for_surface( } } + if (!pipe_ctx->plane_state && + old_pipe_ctx->plane_state && + old_pipe_ctx->stream_res.tg == tg) { - if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) - || (!pipe_ctx->stream && old_pipe_ctx->stream)) { - if (old_pipe_ctx->stream_res.tg->inst != be_idx) - continue; - - if (!old_pipe_ctx->top_pipe) { - ASSERT(0); - continue; - } - - /* reset mpc */ - dc->res_pool->mpc->funcs->remove( - dc->res_pool->mpc, - &(old_pipe_ctx->stream_res.opp->mpc_tree), - old_pipe_ctx->stream_res.opp->inst, - old_pipe_ctx->pipe_idx); - old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[old_pipe_ctx->plane_res.hubp->mpcc_id] = true; - - /*dm_logger_write(dc->ctx->logger, LOG_ERROR, - "[debug_mpo: apply_ctx disconnect pending on mpcc %d]\n", - old_pipe_ctx->mpcc->inst);*/ - - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); - - old_pipe_ctx->top_pipe = NULL; - old_pipe_ctx->bottom_pipe = NULL; - old_pipe_ctx->plane_state = NULL; - old_pipe_ctx->stream = NULL; + plane_atomic_disconnect(dc, old_pipe_ctx); + removed_pipe[i] = true; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset mpcc for pipe %d\n", @@ -2603,18 +2236,53 @@ static void dcn10_apply_ctx_for_surface( } } + if (num_planes > 0) { + program_all_pipe_in_tree(dc, top_pipe_to_program, context); + + /* TODO: this is a hack w/a for switching from mpo to pipe split */ + if (stream->cursor_attributes.address.quad_part != 0) { + struct dc_cursor_position position = { 0 }; + + dc_stream_set_cursor_position( + (struct dc_stream_state *)stream, + &position); + dc_stream_set_cursor_attributes( + (struct dc_stream_state *)stream, + &stream->cursor_attributes); + } + } + + tg->funcs->unlock(tg); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *old_pipe_ctx = + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->stream != stream) - continue; + if (pipe_ctx->stream == stream && + pipe_ctx->plane_state && + pipe_ctx->plane_state->update_flags.bits.full_update) + program_water_mark = true; - /* looking for top pipe to program */ - if (!pipe_ctx->top_pipe) - program_all_pipe_in_tree(dc, pipe_ctx, context); + if (removed_pipe[i] && num_planes == 0) + dcn10_disable_plane(dc, old_pipe_ctx); } - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, + if (program_water_mark) { + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ + dcn10_verify_allow_pstate_change_high(dc); + } + /* watermark is for all pipes */ + hubbub1_program_watermarks(dc->res_pool->hubbub, + &context->bw.dcn.watermarks, ref_clk_mhz); + + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ + dcn10_verify_allow_pstate_change_high(dc); + } + } +/* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, "\n============== Watermark parameters ==============\n" "a.urgent_ns: %d \n" "a.cstate_enter_plus_exit: %d \n" @@ -2660,9 +2328,7 @@ static void dcn10_apply_ctx_for_surface( context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns, context->bw.dcn.watermarks.d.pte_meta_urgent_ns ); - - if (dc->debug.sanity_checks) - verify_allow_pstate_change_high(dc->hwseq); +*/ } static void dcn10_set_bandwidth( @@ -2676,7 +2342,7 @@ static void dcn10_set_bandwidth( struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) @@ -2732,7 +2398,7 @@ static void dcn10_set_bandwidth( dcn10_pplib_apply_display_requirements(dc, context); if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } /* need to fix this function. not doing the right thing here */ @@ -2857,7 +2523,7 @@ static void dcn10_wait_for_mpcc_disconnect( int i; if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } if (!pipe_ctx->stream_res.opp) @@ -2875,7 +2541,7 @@ static void dcn10_wait_for_mpcc_disconnect( } if (dc->debug.sanity_checks) { - verify_allow_pstate_change_high(dc->hwseq); + dcn10_verify_allow_pstate_change_high(dc); } } @@ -2909,7 +2575,11 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) } } - +void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) +{ + if (hws->ctx->dc->res_pool->hubbub != NULL) + hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data); +} static const struct hw_sequencer_funcs dcn10_funcs = { .program_gamut_remap = program_gamut_remap, @@ -2926,13 +2596,13 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .power_down = dce110_power_down, .enable_accelerated_mode = dce110_enable_accelerated_mode, .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, .update_info_frame = dce110_update_info_frame, .enable_stream = dce110_enable_stream, .disable_stream = dce110_disable_stream, .unblank_stream = dce110_unblank_stream, .enable_display_power_gating = dcn10_dummy_display_power_gating, - .power_down_front_end = dcn10_power_down_fe, - .power_on_front_end = dcn10_power_on_fe, + .disable_plane = dcn10_disable_plane, .pipe_control_lock = dcn10_pipe_control_lock, .set_bandwidth = dcn10_set_bandwidth, .reset_hw_ctx_wrap = reset_hw_ctx_wrap, @@ -2946,6 +2616,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = { .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, .ready_shared_resources = ready_shared_resources, .optimize_shared_resources = optimize_shared_resources, + .pplib_apply_display_requirements = + dcn10_pplib_apply_display_requirements, .edp_backlight_control = hwss_edp_backlight_control, .edp_power_control = hwss_edp_power_control }; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index ca53dc1cc19b..b9d326082717 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -35,4 +35,5 @@ extern void fill_display_configs( const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); + #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 76573e1f5b01..b016f4cbd45c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -335,11 +335,22 @@ void mpc10_update_blend_mode( MPCC_ALPHA_MULTIPLIED_MODE, cfg->pre_multiplied_alpha); } +int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id) +{ + struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); + int opp_id = 0xF; + + REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); + + return opp_id; +} + const struct mpc_funcs dcn10_mpc_funcs = { .add = mpc10_mpcc_add, .remove = mpc10_mpcc_remove, .wait_for_idle = mpc10_assert_idle_mpcc, .update_blend_mode = mpc10_update_blend_mode, + .get_opp_id = mpc10_get_opp_id, }; void dcn10_mpc_construct(struct dcn10_mpc *mpc10, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h index 683ce4aaa76e..e85e1f342266 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h @@ -134,5 +134,6 @@ void mpc10_assert_idle_mpcc( void mpc10_update_blend_mode( struct mpc *mpc, struct mpcc_cfg *cfg); +int mpc10_get_opp_id(struct mpc *mpc, int mpcc_id); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index a136f70b7a3c..6d6f67b7d30e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -38,7 +38,6 @@ oppn10->base.ctx - /************* FORMATTER ************/ /** @@ -47,7 +46,7 @@ * 2) enable truncation * 3) HW remove 12bit FMT support for DCE11 power saving reason. */ -static void set_truncation( +static void opp1_set_truncation( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { @@ -57,7 +56,7 @@ static void set_truncation( FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE); } -static void set_spatial_dither( +static void opp1_set_spatial_dither( struct dcn10_opp *oppn10, const struct bit_depth_reduction_params *params) { @@ -136,14 +135,14 @@ static void set_spatial_dither( FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM); } -static void oppn10_program_bit_depth_reduction( +void opp1_program_bit_depth_reduction( struct output_pixel_processor *opp, const struct bit_depth_reduction_params *params) { struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - set_truncation(oppn10, params); - set_spatial_dither(oppn10, params); + opp1_set_truncation(oppn10, params); + opp1_set_spatial_dither(oppn10, params); /* TODO * set_temporal_dither(oppn10, params); */ @@ -156,7 +155,7 @@ static void oppn10_program_bit_depth_reduction( * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly * 1: YCbCr 4:2:2 */ -static void set_pixel_encoding( +static void opp1_set_pixel_encoding( struct dcn10_opp *oppn10, const struct clamping_and_pixel_encoding_params *params) { @@ -186,7 +185,7 @@ static void set_pixel_encoding( * 7 for programable * 2) Enable clamp if Limited range requested */ -static void opp_set_clamping( +static void opp1_set_clamping( struct dcn10_opp *oppn10, const struct clamping_and_pixel_encoding_params *params) { @@ -224,7 +223,7 @@ static void opp_set_clamping( } -static void oppn10_set_dyn_expansion( +void opp1_set_dyn_expansion( struct output_pixel_processor *opp, enum dc_color_space color_sp, enum dc_color_depth color_dpth, @@ -264,17 +263,17 @@ static void oppn10_set_dyn_expansion( } } -static void opp_program_clamping_and_pixel_encoding( +static void opp1_program_clamping_and_pixel_encoding( struct output_pixel_processor *opp, const struct clamping_and_pixel_encoding_params *params) { struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); - opp_set_clamping(oppn10, params); - set_pixel_encoding(oppn10, params); + opp1_set_clamping(oppn10, params); + opp1_set_pixel_encoding(oppn10, params); } -static void oppn10_program_fmt( +void opp1_program_fmt( struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, struct clamping_and_pixel_encoding_params *clamping) @@ -286,20 +285,18 @@ static void oppn10_program_fmt( /* dithering is affected by <CrtcSourceSelect>, hence should be * programmed afterwards */ - oppn10_program_bit_depth_reduction( + opp1_program_bit_depth_reduction( opp, fmt_bit_depth); - opp_program_clamping_and_pixel_encoding( + opp1_program_clamping_and_pixel_encoding( opp, clamping); return; } - - -static void oppn10_set_stereo_polarity( +void opp1_set_stereo_polarity( struct output_pixel_processor *opp, bool enable, bool rightEyePolarity) { @@ -312,18 +309,18 @@ static void oppn10_set_stereo_polarity( /* Constructor, Destructor */ /*****************************************/ -static void dcn10_opp_destroy(struct output_pixel_processor **opp) +void opp1_destroy(struct output_pixel_processor **opp) { kfree(TO_DCN10_OPP(*opp)); *opp = NULL; } static struct opp_funcs dcn10_opp_funcs = { - .opp_set_dyn_expansion = oppn10_set_dyn_expansion, - .opp_program_fmt = oppn10_program_fmt, - .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction, - .opp_set_stereo_polarity = oppn10_set_stereo_polarity, - .opp_destroy = dcn10_opp_destroy + .opp_set_dyn_expansion = opp1_set_dyn_expansion, + .opp_program_fmt = opp1_program_fmt, + .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction, + .opp_set_stereo_polarity = opp1_set_stereo_polarity, + .opp_destroy = opp1_destroy }; void dcn10_opp_construct(struct dcn10_opp *oppn10, @@ -333,17 +330,10 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask) { - int i; oppn10->base.ctx = ctx; oppn10->base.inst = inst; oppn10->base.funcs = &dcn10_opp_funcs; - oppn10->base.mpc_tree.dpp[0] = inst; - oppn10->base.mpc_tree.mpcc[0] = inst; - oppn10->base.mpc_tree.num_pipes = 1; - for (i = 0; i < MAX_PIPES; i++) - oppn10->base.mpcc_disconnect_pending[i] = false; - oppn10->regs = regs; oppn10->opp_shift = opp_shift; oppn10->opp_mask = opp_mask; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h index 790ce6014832..f3c298ec37fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h @@ -46,6 +46,16 @@ #define OPP_REG_LIST_DCN10(id) \ OPP_REG_LIST_DCN(id) +#define OPP_COMMON_REG_VARIABLE_LIST \ + uint32_t FMT_BIT_DEPTH_CONTROL; \ + uint32_t FMT_CONTROL; \ + uint32_t FMT_DITHER_RAND_R_SEED; \ + uint32_t FMT_DITHER_RAND_G_SEED; \ + uint32_t FMT_DITHER_RAND_B_SEED; \ + uint32_t FMT_CLAMP_CNTL; \ + uint32_t FMT_DYNAMIC_EXP_CNTL; \ + uint32_t FMT_MAP420_MEMORY_CONTROL; + #define OPP_MASK_SH_LIST_DCN(mask_sh) \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ @@ -74,40 +84,6 @@ OPP_MASK_SH_LIST_DCN(mask_sh) #define OPP_DCN10_REG_FIELD_LIST(type) \ - type DPG_EN; \ - type DPG_MODE; \ - type DPG_VRES; \ - type DPG_HRES; \ - type DPG_COLOUR0_R_CR; \ - type DPG_COLOUR1_R_CR; \ - type DPG_COLOUR0_B_CB; \ - type DPG_COLOUR1_B_CB; \ - type DPG_COLOUR0_G_Y; \ - type DPG_COLOUR1_G_Y; \ - type CM_OCSC_C11; \ - type CM_OCSC_C12; \ - type CM_OCSC_C13; \ - type CM_OCSC_C14; \ - type CM_OCSC_C21; \ - type CM_OCSC_C22; \ - type CM_OCSC_C23; \ - type CM_OCSC_C24; \ - type CM_OCSC_C31; \ - type CM_OCSC_C32; \ - type CM_OCSC_C33; \ - type CM_OCSC_C34; \ - type CM_COMB_C11; \ - type CM_COMB_C12; \ - type CM_COMB_C13; \ - type CM_COMB_C14; \ - type CM_COMB_C21; \ - type CM_COMB_C22; \ - type CM_COMB_C23; \ - type CM_COMB_C24; \ - type CM_COMB_C31; \ - type CM_COMB_C32; \ - type CM_COMB_C33; \ - type CM_COMB_C34; \ type FMT_TRUNCATE_EN; \ type FMT_TRUNCATE_DEPTH; \ type FMT_TRUNCATE_MODE; \ @@ -129,41 +105,18 @@ type FMT_DYNAMIC_EXP_EN; \ type FMT_DYNAMIC_EXP_MODE; \ type FMT_MAP420MEM_PWR_FORCE; \ - type FMT_STEREOSYNC_OVERRIDE + type FMT_STEREOSYNC_OVERRIDE; -struct dcn10_opp_shift { - OPP_DCN10_REG_FIELD_LIST(uint8_t); +struct dcn10_opp_registers { + OPP_COMMON_REG_VARIABLE_LIST }; -struct dcn10_opp_mask { - OPP_DCN10_REG_FIELD_LIST(uint32_t); +struct dcn10_opp_shift { + OPP_DCN10_REG_FIELD_LIST(uint8_t) }; -struct dcn10_opp_registers { - uint32_t DPG_CONTROL; - uint32_t DPG_COLOUR_B_CB; - uint32_t DPG_COLOUR_G_Y; - uint32_t DPG_COLOUR_R_CR; - uint32_t CM_OCSC_C11_C12; - uint32_t CM_OCSC_C13_C14; - uint32_t CM_OCSC_C21_C22; - uint32_t CM_OCSC_C23_C24; - uint32_t CM_OCSC_C31_C32; - uint32_t CM_OCSC_C33_C34; - uint32_t CM_COMB_C11_C12; - uint32_t CM_COMB_C13_C14; - uint32_t CM_COMB_C21_C22; - uint32_t CM_COMB_C23_C24; - uint32_t CM_COMB_C31_C32; - uint32_t CM_COMB_C33_C34; - uint32_t FMT_BIT_DEPTH_CONTROL; - uint32_t FMT_CONTROL; - uint32_t FMT_DITHER_RAND_R_SEED; - uint32_t FMT_DITHER_RAND_G_SEED; - uint32_t FMT_DITHER_RAND_B_SEED; - uint32_t FMT_CLAMP_CNTL; - uint32_t FMT_DYNAMIC_EXP_CNTL; - uint32_t FMT_MAP420_MEMORY_CONTROL; +struct dcn10_opp_mask { + OPP_DCN10_REG_FIELD_LIST(uint32_t) }; struct dcn10_opp { @@ -183,4 +136,25 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10, const struct dcn10_opp_shift *opp_shift, const struct dcn10_opp_mask *opp_mask); +void opp1_set_dyn_expansion( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); + +void opp1_program_fmt( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + +void opp1_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + +void opp1_set_stereo_polarity( + struct output_pixel_processor *opp, + bool enable, bool rightEyePolarity); + +void opp1_destroy(struct output_pixel_processor **opp); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9fc8f827f2a1..10cce51d31d2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -48,16 +48,17 @@ #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" #include "dcn10_hubp.h" +#include "dcn10_hubbub.h" -#include "vega10/soc15ip.h" +#include "soc15ip.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" -#include "raven1/NBIO/nbio_7_0_offset.h" +#include "nbio/nbio_7_0_offset.h" -#include "raven1/MMHUB/mmhub_9_1_offset.h" -#include "raven1/MMHUB/mmhub_9_1_sh_mask.h" +#include "mmhub/mmhub_9_1_offset.h" +#include "mmhub/mmhub_9_1_sh_mask.h" #include "reg_helper.h" #include "dce/dce_abm.h" @@ -367,25 +368,38 @@ static const struct bios_registers bios_regs = { NBIO_SR(BIOS_SCRATCH_6) }; -#define mi_regs(id)\ +#define hubp_regs(id)\ [id] = {\ - MI_REG_LIST_DCN10(id)\ + HUBP_REG_LIST_DCN10(id)\ } -static const struct dcn_mi_registers mi_regs[] = { - mi_regs(0), - mi_regs(1), - mi_regs(2), - mi_regs(3), +static const struct dcn_mi_registers hubp_regs[] = { + hubp_regs(0), + hubp_regs(1), + hubp_regs(2), + hubp_regs(3), }; -static const struct dcn_mi_shift mi_shift = { - MI_MASK_SH_LIST_DCN10(__SHIFT) +static const struct dcn_mi_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN10(__SHIFT) }; -static const struct dcn_mi_mask mi_mask = { - MI_MASK_SH_LIST_DCN10(_MASK) +static const struct dcn_mi_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN10(_MASK) +}; + + +static const struct dcn_hubbub_registers hubbub_reg = { + HUBBUB_REG_LIST_DCN10(0) +}; + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) +}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN10(_MASK) }; #define clk_src_regs(index, pllid)\ @@ -519,6 +533,22 @@ static struct mpc *dcn10_mpc_create(struct dc_context *ctx) return &mpc10->base; } +static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) +{ + struct hubbub *hubbub = kzalloc(sizeof(struct hubbub), + GFP_KERNEL); + + if (!hubbub) + return NULL; + + hubbub1_construct(hubbub, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask); + + return hubbub; +} + static struct timing_generator *dcn10_timing_generator_create( struct dc_context *ctx, uint32_t instance) @@ -647,6 +677,7 @@ static struct dce_hwseq *dcn10_hwseq_create( hws->regs = &hwseq_reg; hws->shifts = &hwseq_shift; hws->masks = &hwseq_mask; + hws->wa.DEGVIDCN10_253 = true; } return hws; } @@ -700,6 +731,12 @@ static void destruct(struct dcn10_resource_pool *pool) kfree(TO_DCN10_MPC(pool->base.mpc)); pool->base.mpc = NULL; } + + if (pool->base.hubbub != NULL) { + kfree(pool->base.hubbub); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); @@ -768,7 +805,7 @@ static struct hubp *dcn10_hubp_create( return NULL; dcn10_hubp_construct(hubp1, ctx, inst, - &mi_regs[inst], &mi_shift, &mi_mask); + &hubp_regs[inst], &hubp_shift, &hubp_mask); return &hubp1->base; } @@ -1233,8 +1270,8 @@ static bool construct( dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 256; - dc->caps.max_slave_planes = 1; + dc->caps.is_apu = true; if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) dc->debug = debug_defaults_drv; @@ -1274,7 +1311,7 @@ static bool construct( if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); - goto clock_source_create_fail; + goto fail; } } @@ -1283,7 +1320,7 @@ static bool construct( if (pool->base.display_clock == NULL) { dm_error("DC: failed to create display clock!\n"); BREAK_TO_DEBUGGER(); - goto disp_clk_create_fail; + goto fail; } } @@ -1294,7 +1331,7 @@ static bool construct( if (pool->base.dmcu == NULL) { dm_error("DC: failed to create dmcu!\n"); BREAK_TO_DEBUGGER(); - goto res_create_fail; + goto fail; } pool->base.abm = dce_abm_create(ctx, @@ -1304,7 +1341,7 @@ static bool construct( if (pool->base.abm == NULL) { dm_error("DC: failed to create abm!\n"); BREAK_TO_DEBUGGER(); - goto res_create_fail; + goto fail; } dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); @@ -1344,13 +1381,11 @@ static bool construct( } { - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) struct irq_service_init_data init_data; init_data.ctx = dc->ctx; pool->base.irqs = dal_irq_service_dcn10_create(&init_data); if (!pool->base.irqs) - goto irqs_create_fail; - #endif + goto fail; } /* index to valid pipe resource */ @@ -1368,7 +1403,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create memory input!\n"); - goto mi_create_fail; + goto fail; } pool->base.ipps[j] = dcn10_ipp_create(ctx, i); @@ -1376,7 +1411,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create input pixel processor!\n"); - goto ipp_create_fail; + goto fail; } pool->base.dpps[j] = dcn10_dpp_create(ctx, i); @@ -1384,7 +1419,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create dpp!\n"); - goto dpp_create_fail; + goto fail; } pool->base.opps[j] = dcn10_opp_create(ctx, i); @@ -1392,7 +1427,7 @@ static bool construct( BREAK_TO_DEBUGGER(); dm_error( "DC: failed to create output pixel processor!\n"); - goto opp_create_fail; + goto fail; } pool->base.timing_generators[j] = dcn10_timing_generator_create( @@ -1400,8 +1435,9 @@ static bool construct( if (pool->base.timing_generators[j] == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create tg!\n"); - goto otg_create_fail; + goto fail; } + /* check next valid pipe */ j++; } @@ -1419,13 +1455,20 @@ static bool construct( if (pool->base.mpc == NULL) { BREAK_TO_DEBUGGER(); dm_error("DC: failed to create mpc!\n"); - goto mpc_create_fail; + goto fail; + } + + pool->base.hubbub = dcn10_hubbub_create(ctx); + if (pool->base.hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto fail; } if (!resource_construct(num_virtual_links, dc, &pool->base, (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? &res_create_funcs : &res_create_maximus_funcs))) - goto res_create_fail; + goto fail; dcn10_hw_sequencer_construct(dc); dc->caps.max_planes = pool->base.pipe_count; @@ -1434,16 +1477,7 @@ static bool construct( return true; -disp_clk_create_fail: -mpc_create_fail: -otg_create_fail: -opp_create_fail: -dpp_create_fail: -ipp_create_fail: -mi_create_fail: -irqs_create_fail: -res_create_fail: -clock_source_create_fail: +fail: destruct(pool); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c index fced178c8c79..73ff78f9cae1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c @@ -290,6 +290,16 @@ static void tgn10_program_timing( } +static void tgn10_set_blank_data_double_buffer(struct timing_generator *tg, bool enable) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; + + REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, + OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); +} + /** * unblank_crtc * Call ASIC Control Object to UnBlank CRTC. @@ -306,8 +316,7 @@ static void tgn10_unblank_crtc(struct timing_generator *tg) * this check will be removed. */ if (vertical_interrupt_enable) - REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, - OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 1); + tgn10_set_blank_data_double_buffer(tg, true); REG_UPDATE_2(OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, 0, @@ -334,8 +343,7 @@ static void tgn10_blank_crtc(struct timing_generator *tg) OTG_BLANK_DATA_EN, 1, 1, 100000); - REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, - OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0); + tgn10_set_blank_data_double_buffer(tg, false); } static void tgn10_set_blank(struct timing_generator *tg, @@ -385,19 +393,9 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable) OTG_CLOCK_GATE_DIS, 0, OTG_CLOCK_EN, 0); - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OTG_CLOCK_CONTROL, - OTG_CLOCK_ON, 0, - 1, 1000); - REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, 0, OPTC_INPUT_CLK_EN, 0); - - if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) - REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, - OPTC_INPUT_CLK_ON, 0, - 1, 1000); } } @@ -560,10 +558,11 @@ static void tgn10_lock(struct timing_generator *tg) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 1); + /* Should be fast, status does not update on maximus */ if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) REG_WAIT(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, 1, - 1, 100); + 1, 10); } static void tgn10_unlock(struct timing_generator *tg) @@ -572,11 +571,6 @@ static void tgn10_unlock(struct timing_generator *tg) REG_SET(OTG_MASTER_UPDATE_LOCK, 0, OTG_MASTER_UPDATE_LOCK, 0); - - /* why are we waiting here? */ - REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, - OTG_UPDATE_PENDING, 0, - 1, 100000); } static void tgn10_get_position(struct timing_generator *tg, @@ -610,12 +604,28 @@ static bool tgn10_did_triggered_reset_occur( struct timing_generator *tg) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); - uint32_t occurred; + uint32_t occurred_force, occurred_vsync; REG_GET(OTG_FORCE_COUNT_NOW_CNTL, - OTG_FORCE_COUNT_NOW_OCCURRED, &occurred); + OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); + + REG_GET(OTG_VERT_SYNC_CONTROL, + OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); - return occurred != 0; + return occurred_vsync != 0 || occurred_force != 0; +} + +static void tgn10_disable_reset_trigger(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + REG_WRITE(OTG_TRIGA_CNTL, 0); + + REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, + OTG_FORCE_COUNT_NOW_CLEAR, 1); + + REG_SET(OTG_VERT_SYNC_CONTROL, 0, + OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); } static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_tg_inst) @@ -652,14 +662,49 @@ static void tgn10_enable_reset_trigger(struct timing_generator *tg, int source_t OTG_FORCE_COUNT_NOW_MODE, 2); } -static void tgn10_disable_reset_trigger(struct timing_generator *tg) +void tgn10_enable_crtc_reset( + struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp) { struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + uint32_t falling_edge = 0; + uint32_t rising_edge = 0; - REG_WRITE(OTG_TRIGA_CNTL, 0); + switch (crtc_tp->event) { - REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, - OTG_FORCE_COUNT_NOW_CLEAR, 1); + case CRTC_EVENT_VSYNC_RISING: + rising_edge = 1; + break; + + case CRTC_EVENT_VSYNC_FALLING: + falling_edge = 1; + break; + } + + REG_SET_4(OTG_TRIGA_CNTL, 0, + /* vsync signal from selected OTG pipe based + * on OTG_TRIG_SOURCE_PIPE_SELECT setting + */ + OTG_TRIGA_SOURCE_SELECT, 20, + OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, + /* always detect falling edge */ + OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, + OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); + + switch (crtc_tp->delay) { + case TRIGGER_DELAY_NEXT_LINE: + REG_SET(OTG_VERT_SYNC_CONTROL, 0, + OTG_AUTO_FORCE_VSYNC_MODE, 1); + break; + case TRIGGER_DELAY_NEXT_PIXEL: + REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, + /* force H count to H_TOTAL and V count to V_TOTAL in + * progressive mode and V_TOTAL-1 in interlaced mode + */ + OTG_FORCE_COUNT_NOW_MODE, 2); + break; + } } static void tgn10_wait_for_state(struct timing_generator *tg, @@ -1154,7 +1199,24 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); } +static void tgn10_tg_init(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + + tgn10_set_blank_data_double_buffer(tg, true); + REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); +} + +static bool tgn10_is_tg_enabled(struct timing_generator *tg) +{ + struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg); + uint32_t otg_enabled = 0; + + REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); + + return (otg_enabled != 0); +} static const struct timing_generator_funcs dcn10_tg_funcs = { .validate_timing = tgn10_validate_timing, .program_timing = tgn10_program_timing, @@ -1174,6 +1236,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_blank_color = tgn10_program_blank_color, .did_triggered_reset_occur = tgn10_did_triggered_reset_occur, .enable_reset_trigger = tgn10_enable_reset_trigger, + .enable_crtc_reset = tgn10_enable_crtc_reset, .disable_reset_trigger = tgn10_disable_reset_trigger, .lock = tgn10_lock, .unlock = tgn10_unlock, @@ -1182,7 +1245,10 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .set_static_screen_control = tgn10_set_static_screen_control, .set_test_pattern = tgn10_set_test_pattern, .program_stereo = tgn10_program_stereo, - .is_stereo_left_eye = tgn10_is_stereo_left_eye + .is_stereo_left_eye = tgn10_is_stereo_left_eye, + .set_blank_data_double_buffer = tgn10_set_blank_data_double_buffer, + .tg_init = tgn10_tg_init, + .is_tg_enabled = tgn10_is_tg_enabled, }; void dcn10_timing_generator_init(struct dcn10_timing_generator *tgn10) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h index 7d4818d7aa31..bb1cbfdc3554 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h @@ -72,7 +72,10 @@ SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ SRI(OPPBUF_CONTROL, OPPBUF, inst),\ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ - SRI(CONTROL, VTG, inst) + SRI(CONTROL, VTG, inst),\ + SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ + SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ + SRI(OTG_GSL_CONTROL, OTG, inst) #define TG_COMMON_REG_LIST_DCN1_0(inst) \ TG_COMMON_REG_LIST_DCN(inst),\ @@ -82,6 +85,9 @@ struct dcn_tg_registers { + uint32_t OTG_VERT_SYNC_CONTROL; + uint32_t OTG_MASTER_UPDATE_MODE; + uint32_t OTG_GSL_CONTROL; uint32_t OTG_VSTARTUP_PARAM; uint32_t OTG_VUPDATE_PARAM; uint32_t OTG_VREADY_PARAM; @@ -204,11 +210,23 @@ struct dcn_tg_registers { SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ - SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh) + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh) + #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -313,11 +331,22 @@ struct dcn_tg_registers { type OPTC_SRC_SEL;\ type OPTC_SEG0_SRC_SEL;\ type OPTC_UNDERFLOW_OCCURRED_STATUS;\ + type OPTC_UNDERFLOW_CLEAR;\ type OPPBUF_ACTIVE_WIDTH;\ type OPPBUF_3D_VACT_SPACE1_SIZE;\ type VTG0_ENABLE;\ type VTG0_FP2;\ - type VTG0_VCOUNT_INIT; + type VTG0_VCOUNT_INIT;\ + type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ + type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ + type OTG_AUTO_FORCE_VSYNC_MODE;\ + type MASTER_UPDATE_INTERLACED_MODE;\ + type OTG_GSL0_EN;\ + type OTG_GSL1_EN;\ + type OTG_GSL2_EN;\ + type OTG_GSL_MASTER_EN;\ + type OTG_GSL_FORCE_DELAY;\ + type OTG_GSL_CHECK_ALL_FIELDS; struct dcn_tg_shift { TG_REG_FIELD_LIST(uint8_t) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index d4917037ac42..225b7bfb09a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -373,6 +373,13 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id); unsigned long long dm_get_timestamp(struct dc_context *ctx); /* + * performance tracing + */ +void dm_perf_trace_timestamp(const char *func_name, unsigned int line); +#define PERF_TRACE() dm_perf_trace_timestamp(__func__, __LINE__) + + +/* * Debug and verification hooks */ bool dm_helpers_dc_conn_log( diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h index baf182177736..2d9d6298f0d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h @@ -229,7 +229,7 @@ struct _vcs_dpi_display_output_params_st { int output_bpp; int dsc_enable; int wb_enable; - int output_bpc; + int opp_input_bpc; int output_type; int output_format; int output_standard; diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c index ea661ee44674..1f337ecfeab0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c @@ -28,6 +28,8 @@ #include "dml_inline_defs.h" +#define BPP_INVALID 0 +#define BPP_BLENDED_PIPE 0xffffffff static const unsigned int NumberOfStates = DC__VOLTAGE_STATES; static void fetch_socbb_params(struct display_mode_lib *mode_lib); @@ -587,7 +589,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_slices; mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] = - dout->output_bpc == 0 ? 12 : dout->output_bpc; + dout->opp_input_bpc == 0 ? 12 : dout->opp_input_bpc; mode_lib->vba.WritebackEnable[mode_lib->vba.NumberOfActivePlanes] = dout->wb_enable; mode_lib->vba.WritebackSourceHeight[mode_lib->vba.NumberOfActivePlanes] = dout->wb.wb_src_height; @@ -3928,7 +3930,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 12) return 12; else - return 0; + return BPP_INVALID; } else if (Format == dm_444) { if (DecimalBPP >= 36) return 36; @@ -3937,7 +3939,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 24) return 24; else - return 0; + return BPP_INVALID; } else { if (DecimalBPP / 1.5 >= 24) return 24; @@ -3946,27 +3948,27 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP / 1.5 >= 16) return 16; else - return 0; + return BPP_INVALID; } } else { if (DSCEnabled) { if (Format == dm_420) { if (DecimalBPP < 6) - return 0; + return BPP_INVALID; else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16) return 1.5 * DSCInputBitPerComponent - 1 / 16; else return dml_floor(16 * DecimalBPP, 1) / 16; } else if (Format == dm_n422) { if (DecimalBPP < 7) - return 0; + return BPP_INVALID; else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16) return 2 * DSCInputBitPerComponent - 1 / 16; else return dml_floor(16 * DecimalBPP, 1) / 16; } else { if (DecimalBPP < 8) - return 0; + return BPP_INVALID; else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16) return 3 * DSCInputBitPerComponent - 1 / 16; else @@ -3980,7 +3982,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 12) return 12; else - return 0; + return BPP_INVALID; } else if (Format == dm_s422 || Format == dm_n422) { if (DecimalBPP >= 24) return 24; @@ -3989,7 +3991,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 16) return 16; else - return 0; + return BPP_INVALID; } else { if (DecimalBPP >= 36) return 36; @@ -3998,7 +4000,7 @@ static unsigned int TruncToValidBPP( else if (DecimalBPP >= 24) return 24; else - return 0; + return BPP_INVALID; } } } @@ -4922,11 +4924,7 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.ViewportSizeSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { if (mode_lib->vba.ODMCombineEnablePerState[i][k] == true) { - if (dml_min( - mode_lib->vba.SwathWidthYSingleDPP[k], - dml_round( - mode_lib->vba.HActive[k] / 2.0 - * mode_lib->vba.HRatio[k])) + if (dml_min(mode_lib->vba.SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k])) > mode_lib->vba.MaximumSwathWidth[k]) { mode_lib->vba.ViewportSizeSupport[i] = false; } @@ -4980,12 +4978,8 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.RequiresDSC[i][k] = 0; mode_lib->vba.RequiresFEC[i][k] = 0; mode_lib->vba.OutputBppPerState[i][k] = - TruncToValidBPP( - dml_min( - 600.0, - mode_lib->vba.PHYCLKPerState[i]) - / mode_lib->vba.PixelClockBackEnd[k] - * 24, + TruncToValidBPP(dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) + / mode_lib->vba.PixelClockBackEnd[k] * 24, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], @@ -5000,30 +4994,16 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { mode_lib->vba.Outbpp = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * 270.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); mode_lib->vba.OutbppDSC = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * (1.0 - - mode_lib->vba.EffectiveFECOverhead - / 100.0) - * 270.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) + * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, true, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], @@ -5046,32 +5026,18 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.OutputBppPerState[i][k] = mode_lib->vba.Outbpp; } - if (mode_lib->vba.Outbpp == 0) { + if (mode_lib->vba.Outbpp == BPP_INVALID) { mode_lib->vba.Outbpp = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * 540.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); mode_lib->vba.OutbppDSC = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * (1.0 - - mode_lib->vba.EffectiveFECOverhead - / 100.0) - * 540.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) + * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, true, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], @@ -5094,40 +5060,26 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ mode_lib->vba.OutputBppPerState[i][k] = mode_lib->vba.Outbpp; } - if (mode_lib->vba.Outbpp == 0 + if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 810.0) { mode_lib->vba.Outbpp = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * 810.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, false, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); mode_lib->vba.OutbppDSC = - TruncToValidBPP( - (1.0 - - mode_lib->vba.Downspreading - / 100.0) - * (1.0 - - mode_lib->vba.EffectiveFECOverhead - / 100.0) - * 810.0 - * mode_lib->vba.OutputLinkDPLanes[k] - / mode_lib->vba.PixelClockBackEnd[k] - * 8.0, + TruncToValidBPP((1.0 - mode_lib->vba.Downspreading / 100.0) + * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0 + * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, true, mode_lib->vba.Output[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.DSCInputBitPerComponent[k]); if (mode_lib->vba.DSCEnabled[k] == true - || mode_lib->vba.Outbpp == 0) { + || mode_lib->vba.Outbpp == BPP_INVALID) { mode_lib->vba.RequiresDSC[i][k] = true; if (mode_lib->vba.Output[k] == dm_dp) { mode_lib->vba.RequiresFEC[i][k] = @@ -5147,14 +5099,14 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } } } else { - mode_lib->vba.OutputBppPerState[i][k] = 0; + mode_lib->vba.OutputBppPerState[i][k] = BPP_BLENDED_PIPE; } } } for (i = 0; i <= DC__VOLTAGE_STATES; i++) { mode_lib->vba.DIOSupport[i] = true; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - if (mode_lib->vba.OutputBppPerState[i][k] == 0 + if (mode_lib->vba.OutputBppPerState[i][k] == BPP_INVALID || (mode_lib->vba.OutputFormat[k] == dm_420 && mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) { @@ -5243,8 +5195,8 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ } else { mode_lib->vba.slices = 1.0; } - if (mode_lib->vba.OutputBppPerState[i][k] == 0 - || mode_lib->vba.OutputBppPerState[i][k] == 0) { + if (mode_lib->vba.OutputBppPerState[i][k] == BPP_BLENDED_PIPE + || mode_lib->vba.OutputBppPerState[i][k] == BPP_INVALID) { mode_lib->vba.bpp = 0.0; } else { mode_lib->vba.bpp = mode_lib->vba.OutputBppPerState[i][k]; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c index 4ced9a7d63dd..0c2314efb47e 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c @@ -34,9 +34,9 @@ #include "hw_factory_dce120.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" #define block HPD #define reg_num 0 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c index af3843a69652..a225b02cc779 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c @@ -33,9 +33,9 @@ #include "include/gpio_types.h" #include "../hw_translate.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c index 409763c70ce5..5235f69f0602 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c @@ -34,9 +34,9 @@ #include "hw_factory_dcn10.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" +#include "soc15ip.h" #define block HPD #define reg_num 0 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c index 64a6915b846b..347864810d01 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c @@ -33,9 +33,9 @@ #include "include/gpio_types.h" #include "../hw_translate.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 668981a4c285..a401636bf3f8 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -36,9 +36,9 @@ #include "../dce110/aux_engine_dce110.h" #include "../dce110/i2caux_dce110.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index 13b807d8aff8..bed7cc3e77de 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -36,9 +36,9 @@ #include "../dce110/i2c_hw_engine_dce110.h" #include "../dce110/i2caux_dce110.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" +#include "soc15ip.h" /* begin ********************* * macros to expend register list macro defined in HW object header file */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b69f321e2ab6..d680b565af6f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -139,6 +139,7 @@ struct resource_pool { struct timing_generator *timing_generators[MAX_PIPES]; struct stream_encoder *stream_enc[MAX_PIPES * 2]; + struct hubbub *hubbub; struct mpc *mpc; struct pp_smu_funcs_rv *pp_smu; struct pp_smu_display_requirement_rv pp_smu_req; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h index c93b9b9a817c..48217ecfabd4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h @@ -27,9 +27,19 @@ #include "dm_services_types.h" +struct abm_backlight_registers { + unsigned int BL_PWM_CNTL; + unsigned int BL_PWM_CNTL2; + unsigned int BL_PWM_PERIOD_CNTL; + unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; +}; + struct abm { struct dc_context *ctx; const struct abm_funcs *funcs; + + /* registers setting needs to be saved and restored at InitBacklight */ + struct abm_backlight_registers stored_backlight_registers; }; struct abm_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h index 0574c29cc4a8..b59712b41b81 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h @@ -27,12 +27,29 @@ #include "dm_services_types.h" +enum dmcu_state { + DMCU_NOT_INITIALIZED = 0, + DMCU_RUNNING = 1 +}; + +struct dmcu_version { + unsigned int day; + unsigned int month; + unsigned int year; + unsigned int interface_version; +}; + struct dmcu { struct dc_context *ctx; const struct dmcu_funcs *funcs; + + enum dmcu_state dmcu_state; + struct dmcu_version dmcu_version; + unsigned int cached_wait_loop_number; }; struct dmcu_funcs { + bool (*dmcu_init)(struct dmcu *dmcu); bool (*load_iram)(struct dmcu *dmcu, unsigned int start_offset, const char *src, @@ -44,7 +61,8 @@ struct dmcu_funcs { void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state); void (*set_psr_wait_loop)(struct dmcu *dmcu, unsigned int wait_loop_number); - void (*get_psr_wait_loop)(unsigned int *psr_wait_loop_number); + void (*get_psr_wait_loop)(struct dmcu *dmcu, + unsigned int *psr_wait_loop_number); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index 83a68460edcd..ccb4896975c2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -62,59 +62,63 @@ struct dpp_funcs { struct dpp *dpp, const struct dpp_grph_csc_adjustment *adjust); - void (*opp_set_csc_default)( + void (*dpp_set_csc_default)( struct dpp *dpp, - const struct default_adjustment *default_adjust); + enum dc_color_space colorspace); - void (*opp_set_csc_adjustment)( + void (*dpp_set_csc_adjustment)( struct dpp *dpp, const struct out_csc_color_matrix *tbl_entry); - void (*opp_power_on_regamma_lut)( + void (*dpp_power_on_regamma_lut)( struct dpp *dpp, bool power_on); - void (*opp_program_regamma_lut)( + void (*dpp_program_regamma_lut)( struct dpp *dpp, const struct pwl_result_data *rgb, uint32_t num); - void (*opp_configure_regamma_lut)( + void (*dpp_configure_regamma_lut)( struct dpp *dpp, bool is_ram_a); - void (*opp_program_regamma_lutb_settings)( + void (*dpp_program_regamma_lutb_settings)( struct dpp *dpp, const struct pwl_params *params); - void (*opp_program_regamma_luta_settings)( + void (*dpp_program_regamma_luta_settings)( struct dpp *dpp, const struct pwl_params *params); - void (*opp_program_regamma_pwl)( - struct dpp *dpp, const struct pwl_params *params); + void (*dpp_program_regamma_pwl)( + struct dpp *dpp, + const struct pwl_params *params, + enum opp_regamma mode); - void (*opp_set_regamma_mode)( - struct dpp *dpp_base, - enum opp_regamma mode); + void (*dpp_program_bias_and_scale)( + struct dpp *dpp, + struct dc_bias_and_scale *params); - void (*ipp_set_degamma)( + void (*dpp_set_degamma)( struct dpp *dpp_base, enum ipp_degamma_mode mode); - void (*ipp_program_input_lut)( + void (*dpp_program_input_lut)( struct dpp *dpp_base, const struct dc_gamma *gamma); - void (*ipp_program_degamma_pwl)(struct dpp *dpp_base, + void (*dpp_program_degamma_pwl)(struct dpp *dpp_base, const struct pwl_params *params); - void (*ipp_setup)( + void (*dpp_setup)( struct dpp *dpp_base, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); - void (*ipp_full_bypass)(struct dpp *dpp_base); + void (*dpp_full_bypass)(struct dpp *dpp_base); void (*set_cursor_attributes)( struct dpp *dpp_base, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 0d186be24cf4..49b12f602e79 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -34,9 +34,12 @@ struct hubp { struct dc_plane_address request_address; struct dc_plane_address current_address; int inst; + + /* run time states */ int opp_id; int mpcc_id; struct dc_cursor_attributes curs_attr; + bool power_gated; }; @@ -100,6 +103,8 @@ struct hubp_funcs { const struct dc_cursor_position *pos, const struct dc_cursor_mi_param *param); + void (*hubp_disconnect)(struct hubp *hubp); + }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 9602f261b614..ddc56700109b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -73,7 +73,7 @@ struct pwl_result_data { struct pwl_params { struct gamma_curve arr_curve_points[34]; - struct curve_points arr_points[3]; + struct curve_points arr_points[2]; struct pwl_result_data rgb_resulted[256 + 3]; uint32_t hw_points_num; }; @@ -131,6 +131,32 @@ struct out_csc_color_matrix { uint16_t regval[12]; }; +struct output_csc_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + +static const struct output_csc_matrix output_csc_matrix[] = { + { COLOR_SPACE_SRGB, + { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} }, + { COLOR_SPACE_SRGB_LIMITED, + { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} }, + { COLOR_SPACE_YCBCR601, + { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 0xFB45, + 0xF6B7, 0xE04, 0x1004} }, + { COLOR_SPACE_YCBCR709, + { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA, + 0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} }, + + /* TODO: correct values below */ + { COLOR_SPACE_YCBCR601_LIMITED, + { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991, + 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} }, + { COLOR_SPACE_YCBCR709_LIMITED, + { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, + 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, +}; + enum opp_regamma { OPP_REGAMMA_BYPASS = 0, OPP_REGAMMA_SRGB, @@ -138,4 +164,18 @@ enum opp_regamma { OPP_REGAMMA_USER }; +struct csc_transform { + uint16_t matrix[12]; + bool enable_adjustment; +}; + +struct dc_bias_and_scale { + uint16_t scale_red; + uint16_t bias_red; + uint16_t scale_green; + uint16_t bias_green; + uint16_t scale_blue; + uint16_t bias_blue; +}; + #endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index f11aa484f46e..2109eac20a3d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -85,8 +85,10 @@ struct ipp_funcs { /* setup ipp to expand/convert input to pixel processor internal format */ void (*ipp_setup)( struct input_pixel_processor *ipp, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); /* DCE function to setup IPP. TODO: see if we can consolidate to setup */ void (*ipp_program_prescale)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 3d33bcda7059..8a08f0a97f94 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -111,7 +111,7 @@ struct link_encoder_funcs { const struct dc_link_settings *link_settings, enum clock_source_id clock_source); void (*disable_output)(struct link_encoder *link_enc, - enum signal_type signal, struct dc_link *link); + enum signal_type signal); void (*dp_set_lane_settings)(struct link_encoder *enc, const struct link_training_settings *link_settings); void (*dp_set_phy_pattern)(struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index d4188b2c0626..72ea33526a5c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -28,6 +28,12 @@ #include "dc_hw_types.h" #include "opp.h" +enum mpc_output_csc_mode { + MPC_OUTPUT_CSC_DISABLE = 0, + MPC_OUTPUT_CSC_COEF_A, + MPC_OUTPUT_CSC_COEF_B +}; + struct mpcc_cfg { int dpp_id; int opp_id; @@ -56,6 +62,18 @@ struct mpc_funcs { void (*update_blend_mode)(struct mpc *mpc, struct mpcc_cfg *cfg); + int (*get_opp_id)(struct mpc *mpc, int mpcc_id); + + void (*set_output_csc)(struct mpc *mpc, + int opp_id, + const struct out_csc_color_matrix *tbl_entry, + enum mpc_output_csc_mode ocsc_mode); + + void (*set_ocsc_default)(struct mpc *mpc, + int opp_id, + enum dc_color_space color_space, + enum mpc_output_csc_mode ocsc_mode); + }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 75adb8fec551..579d1059a3d4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -284,6 +284,18 @@ struct opp_funcs { void (*opp_set_test_pattern)( struct output_pixel_processor *opp, bool enable); + + void (*opp_dpg_blank_enable)( + struct output_pixel_processor *opp, + bool enable, + const struct tg_color *color, + int width, + int height); + + void (*opp_convert_pti)( + struct output_pixel_processor *opp, + bool enable, + bool polarity); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index c6ab38c5b2be..860259913d78 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -158,7 +158,11 @@ struct timing_generator_funcs { const struct dcp_gsl_params *gsl_params); void (*unlock)(struct timing_generator *tg); void (*lock)(struct timing_generator *tg); - void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst); + void (*enable_reset_trigger)(struct timing_generator *tg, + int source_tg_inst); + void (*enable_crtc_reset)(struct timing_generator *tg, + int source_tg_inst, + struct crtc_trigger_info *crtc_tp); void (*disable_reset_trigger)(struct timing_generator *tg); void (*tear_down_global_swap_lock)(struct timing_generator *tg); void (*enable_advanced_request)(struct timing_generator *tg, @@ -178,6 +182,11 @@ struct timing_generator_funcs { void (*program_stereo)(struct timing_generator *tg, const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); bool (*is_stereo_left_eye)(struct timing_generator *tg); + + void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable); + + void (*tg_init)(struct timing_generator *tg); + bool (*is_tg_enabled)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index ea88997e1bbd..6f6c02b89f90 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -250,8 +250,10 @@ struct transform_funcs { void (*ipp_setup)( struct transform *xfm_base, - enum surface_pixel_format input_format, - enum expansion_mode mode); + enum surface_pixel_format format, + enum expansion_mode mode, + struct csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space); void (*ipp_full_bypass)(struct transform *xfm_base); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 8734689a9245..5dc4ecf618ff 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -39,6 +39,11 @@ enum pipe_gating_control { struct dce_hwseq_wa { bool blnd_crtc_trigger; + bool DEGVIDCN10_253; +}; + +struct hwseq_wa_state { + bool DEGVIDCN10_253_applied; }; struct dce_hwseq { @@ -47,6 +52,7 @@ struct dce_hwseq { const struct dce_hwseq_shift *shifts; const struct dce_hwseq_mask *masks; struct dce_hwseq_wa wa; + struct hwseq_wa_state wa_state; }; struct pipe_ctx; @@ -114,6 +120,11 @@ struct hw_sequencer_funcs { int group_size, struct pipe_ctx *grouped_pipes[]); + void (*enable_per_frame_crtc_position_reset)( + struct dc *dc, + int group_size, + struct pipe_ctx *grouped_pipes[]); + void (*enable_display_pipe_clock_gating)( struct dc_context *ctx, bool clock_gating); @@ -124,9 +135,9 @@ struct hw_sequencer_funcs { struct dc_bios *dcb, enum pipe_gating_control power_gating); - void (*power_down_front_end)(struct dc *dc, int fe_idx); + void (*disable_plane)(struct dc *dc, struct pipe_ctx *pipe_ctx); - void (*power_on_front_end)(struct dc *dc, + void (*enable_plane)(struct dc *dc, struct pipe_ctx *pipe, struct dc_state *context); @@ -178,12 +189,16 @@ struct hw_sequencer_funcs { void (*ready_shared_resources)(struct dc *dc, struct dc_state *context); void (*optimize_shared_resources)(struct dc *dc); + void (*pplib_apply_display_requirements)( + struct dc *dc, + struct dc_state *context); void (*edp_power_control)( - struct link_encoder *enc, + struct dc_link *link, bool enable); void (*edp_backlight_control)( struct dc_link *link, bool enable); + }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 2ad56b1a4099..66d52580e29f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -30,9 +30,9 @@ #include "irq_service_dce120.h" #include "../dce110/irq_service_dce110.h" -#include "vega10/DC/dce_12_0_offset.h" -#include "vega10/DC/dce_12_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dce/dce_12_0_offset.h" +#include "dce/dce_12_0_sh_mask.h" +#include "soc15ip.h" #include "ivsrcid/ivsrcid_vislands30.h" diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index 74ad24714f6b..7f7db66c48b0 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -29,9 +29,9 @@ #include "../dce110/irq_service_dce110.h" -#include "raven1/DCN/dcn_1_0_offset.h" -#include "raven1/DCN/dcn_1_0_sh_mask.h" -#include "vega10/soc15ip.h" +#include "dcn/dcn_1_0_offset.h" +#include "dcn/dcn_1_0_sh_mask.h" +#include "soc15ip.h" #include "irq_service_dcn10.h" diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 88c2bde3f039..57a54a7b89e5 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -58,8 +58,7 @@ static void virtual_link_encoder_enable_dp_mst_output( static void virtual_link_encoder_disable_output( struct link_encoder *link_enc, - enum signal_type signal, - struct dc_link *link) {} + enum signal_type signal) {} static void virtual_link_encoder_dp_set_lane_settings( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index 0ff2a899b8f7..019e7a095ea1 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -27,12 +27,8 @@ #define DP_BRANCH_DEVICE_ID_1 0x0010FA #define DP_BRANCH_DEVICE_ID_2 0x0022B9 -#define DP_SINK_DEVICE_ID_1 0x4CE000 #define DP_BRANCH_DEVICE_ID_3 0x00001A #define DP_BRANCH_DEVICE_ID_4 0x0080e1 -#define DP_BRANCH_DEVICE_ID_5 0x006037 -#define DP_SINK_DEVICE_ID_2 0x001CF8 - enum ddc_result { DDC_RESULT_UNKNOWN = 0, @@ -115,40 +111,11 @@ struct av_sync_data { uint8_t aud_del_ins3;/* DPCD 0002Dh */ }; -/*DP to VGA converter*/ -static const uint8_t DP_VGA_CONVERTER_ID_1[] = "mVGAa"; -/*DP to Dual link DVI converter*/ -static const uint8_t DP_DVI_CONVERTER_ID_1[] = "m2DVIa"; /*Travis*/ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; /*Nutmeg*/ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; -/*DP to VGA converter*/ -static const uint8_t DP_VGA_CONVERTER_ID_4[] = "DpVga"; /*DP to Dual link DVI converter*/ static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; -/*DP to Dual link DVI converter 2*/ -static const uint8_t DP_DVI_CONVERTER_ID_42[] = "v2DVIa"; - -static const uint8_t DP_SINK_DEV_STRING_ID2_REV0[] = "\0\0\0\0\0\0"; - -/* Identifies second generation PSR TCON from Parade: Device ID string: - * yy-xx-**-**-**-** - */ -/* xx - Hw ID high byte */ -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_HIGH_BYTE = - 0x06; - -/* yy - HW ID low byte, the same silicon has several package/feature flavors */ -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE1 = - 0x61; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE2 = - 0x62; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE3 = - 0x63; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE4 = - 0x72; -static const uint32_t DP_SINK_DEV_STRING_ID2_REV1_HW_ID_LOW_BYTE5 = - 0x73; #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/grph_object_id.h b/drivers/gpu/drm/amd/display/include/grph_object_id.h index 5eb2b4dc7b9c..03a7a9ca95ea 100644 --- a/drivers/gpu/drm/amd/display/include/grph_object_id.h +++ b/drivers/gpu/drm/amd/display/include/grph_object_id.h @@ -248,7 +248,7 @@ static inline enum controller_id dal_graphics_object_id_get_controller_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_CONTROLLER) - return id.id; + return (enum controller_id) id.id; return CONTROLLER_ID_UNDEFINED; } @@ -256,7 +256,7 @@ static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_CLOCK_SOURCE) - return id.id; + return (enum clock_source_id) id.id; return CLOCK_SOURCE_ID_UNDEFINED; } @@ -264,7 +264,7 @@ static inline enum encoder_id dal_graphics_object_id_get_encoder_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_ENCODER) - return id.id; + return (enum encoder_id) id.id; return ENCODER_ID_UNKNOWN; } @@ -272,7 +272,7 @@ static inline enum connector_id dal_graphics_object_id_get_connector_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_CONNECTOR) - return id.id; + return (enum connector_id) id.id; return CONNECTOR_ID_UNKNOWN; } @@ -280,7 +280,7 @@ static inline enum audio_id dal_graphics_object_id_get_audio_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_AUDIO) - return id.id; + return (enum audio_id) id.id; return AUDIO_ID_UNKNOWN; } @@ -288,7 +288,7 @@ static inline enum engine_id dal_graphics_object_id_get_engine_id( struct graphics_object_id id) { if (id.type == OBJECT_TYPE_ENGINE) - return id.id; + return (enum engine_id) id.id; return ENGINE_ID_UNKNOWN; } #endif diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 8e1fe70097be..28dee960d509 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -57,6 +57,11 @@ void dm_logger_append( const char *msg, ...); +void dm_logger_append_va( + struct log_entry *entry, + const char *msg, + va_list args); + void dm_logger_open( struct dal_logger *logger, struct log_entry *entry, diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 4d7db4aa28e0..b4723af368a5 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -132,14 +132,6 @@ struct core_freesync { #define MOD_FREESYNC_TO_CORE(mod_freesync)\ container_of(mod_freesync, struct core_freesync, public) -static bool check_dc_support(const struct dc *dc) -{ - if (dc->stream_funcs.adjust_vmin_vmax == NULL) - return false; - - return true; -} - struct mod_freesync *mod_freesync_create(struct dc *dc) { struct core_freesync *core_freesync = @@ -169,9 +161,6 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) core_freesync->dc = dc; - if (!check_dc_support(dc)) - goto fail_construct; - /* Create initial module folder in registry for freesync enable data */ flag.save_per_edid = true; flag.save_per_link = false; @@ -599,10 +588,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, update_stream_freesync_context(core_freesync, streams[stream_idx]); - core_freesync->dc->stream_funcs. - adjust_vmin_vmax(core_freesync->dc, streams, - num_streams, v_total_min, - v_total_max); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_min, + v_total_max); return true; @@ -625,8 +613,7 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, core_freesync, streams[stream_idx]); - core_freesync->dc->stream_funcs. - adjust_vmin_vmax( + dc_stream_adjust_vmin_vmax( core_freesync->dc, streams, num_streams, v_total_nominal, v_total_nominal); @@ -645,11 +632,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, core_freesync, streams[stream_idx]); - core_freesync->dc->stream_funcs. - adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, v_total_nominal, - v_total_nominal); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); /* Reset the cached variables */ reset_freesync_state_variables(state); @@ -665,11 +650,9 @@ static bool set_freesync_on_streams(struct core_freesync *core_freesync, * not support freesync because a former stream has * be programmed */ - core_freesync->dc->stream_funcs. - adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, v_total_nominal, - v_total_nominal); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total_nominal, + v_total_nominal); /* Reset the cached variables */ reset_freesync_state_variables(state); } @@ -786,9 +769,8 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, vmin = inserted_frame_v_total; /* Program V_TOTAL */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, vmin, vmax); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, vmin, vmax); } if (state->btr.frame_counter > 0) @@ -822,17 +804,15 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, update_stream_freesync_context(core_freesync, streams[0]); /* Program static screen ramp values */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, streams, - num_streams, v_total, - v_total); + dc_stream_adjust_vmin_vmax(core_freesync->dc, streams, + num_streams, v_total, + v_total); triggers.overlay_update = true; triggers.surface_update = true; - core_freesync->dc->stream_funcs.set_static_screen_events( - core_freesync->dc, streams, num_streams, - &triggers); + dc_stream_set_static_screen_events(core_freesync->dc, streams, + num_streams, &triggers); } } @@ -916,9 +896,8 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, triggers.overlay_update = true; triggers.surface_update = true; - core_freesync->dc->stream_funcs.set_static_screen_events( - core_freesync->dc, streams, num_streams, - &triggers); + dc_stream_set_static_screen_events(core_freesync->dc, streams, + num_streams, &triggers); if (freesync_program_required) /* Program freesync according to current state*/ @@ -1084,10 +1063,9 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, max_refresh); /* Program vtotal min/max */ - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, &streams, 1, - state->freesync_range.vmin, - state->freesync_range.vmax); + dc_stream_adjust_vmin_vmax(core_freesync->dc, &streams, 1, + state->freesync_range.vmin, + state->freesync_range.vmax); } if (min_refresh != 0 && @@ -1163,9 +1141,9 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); index = map_index_from_stream(core_freesync, stream); - if (core_freesync->dc->stream_funcs.get_crtc_position( - core_freesync->dc, &stream, 1, - &position.vertical_count, &position.nominal_vcount)) { + if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1, + &position.vertical_count, + &position.nominal_vcount)) { *nom_v_pos = position.nominal_vcount; *v_pos = position.vertical_count; @@ -1223,9 +1201,9 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, triggers.overlay_update = true; triggers.surface_update = true; - core_freesync->dc->stream_funcs.set_static_screen_events( - core_freesync->dc, streams, num_streams, - &triggers); + dc_stream_set_static_screen_events(core_freesync->dc, + streams, num_streams, + &triggers); } } @@ -1424,10 +1402,8 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, vmax = vmin; - core_freesync->dc->stream_funcs.adjust_vmin_vmax( - core_freesync->dc, &stream, - 1, vmin, - vmax); + dc_stream_adjust_vmin_vmax(core_freesync->dc, &stream, + 1, vmin, vmax); } } diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index b72f8a43d86b..9fa3aaef3f33 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -25,7 +25,6 @@ #include <drm/amd_asic_type.h> -struct seq_file; #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ @@ -61,71 +60,12 @@ enum amd_clockgating_state { AMD_CG_STATE_UNGATE, }; -enum amd_dpm_forced_level { - AMD_DPM_FORCED_LEVEL_AUTO = 0x1, - AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, - AMD_DPM_FORCED_LEVEL_LOW = 0x4, - AMD_DPM_FORCED_LEVEL_HIGH = 0x8, - AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, - AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, - AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, - AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, -}; enum amd_powergating_state { AMD_PG_STATE_GATE = 0, AMD_PG_STATE_UNGATE, }; -struct amd_vce_state { - /* vce clocks */ - u32 evclk; - u32 ecclk; - /* gpu clocks */ - u32 sclk; - u32 mclk; - u8 clk_idx; - u8 pstate; -}; - - -#define AMD_MAX_VCE_LEVELS 6 - -enum amd_vce_level { - AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ - AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ - AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ - AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ - AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ - AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ -}; - -enum amd_pp_profile_type { - AMD_PP_GFX_PROFILE, - AMD_PP_COMPUTE_PROFILE, -}; - -struct amd_pp_profile { - enum amd_pp_profile_type type; - uint32_t min_sclk; - uint32_t min_mclk; - uint16_t activity_threshold; - uint8_t up_hyst; - uint8_t down_hyst; -}; - -enum amd_fan_ctrl_mode { - AMD_FAN_CTRL_NONE = 0, - AMD_FAN_CTRL_MANUAL = 1, - AMD_FAN_CTRL_AUTO = 2, -}; - -enum pp_clock_type { - PP_SCLK, - PP_MCLK, - PP_PCIE, -}; /* CG flags */ #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) @@ -169,27 +109,6 @@ enum pp_clock_type { #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) #define AMD_PG_SUPPORT_MMHUB (1 << 13) -enum amd_pm_state_type { - /* not used for dpm */ - POWER_STATE_TYPE_DEFAULT, - POWER_STATE_TYPE_POWERSAVE, - /* user selectable states */ - POWER_STATE_TYPE_BATTERY, - POWER_STATE_TYPE_BALANCED, - POWER_STATE_TYPE_PERFORMANCE, - /* internal states */ - POWER_STATE_TYPE_INTERNAL_UVD, - POWER_STATE_TYPE_INTERNAL_UVD_SD, - POWER_STATE_TYPE_INTERNAL_UVD_HD, - POWER_STATE_TYPE_INTERNAL_UVD_HD2, - POWER_STATE_TYPE_INTERNAL_UVD_MVC, - POWER_STATE_TYPE_INTERNAL_BOOT, - POWER_STATE_TYPE_INTERNAL_THERMAL, - POWER_STATE_TYPE_INTERNAL_ACPI, - POWER_STATE_TYPE_INTERNAL_ULV, - POWER_STATE_TYPE_INTERNAL_3DPERF, -}; - struct amd_ip_funcs { /* Name of IP block */ char *name; @@ -233,95 +152,4 @@ struct amd_ip_funcs { }; -enum amd_pp_task; -enum amd_pp_clock_type; -struct pp_states_info; -struct amd_pp_simple_clock_info; -struct amd_pp_display_configuration; -struct amd_pp_clock_info; -struct pp_display_clock_request; -struct pp_wm_sets_with_clock_ranges_soc15; -struct pp_clock_levels_with_voltage; -struct pp_clock_levels_with_latency; -struct amd_pp_clocks; - -struct amd_pm_funcs { -/* export for dpm on ci and si */ - int (*pre_set_power_state)(void *handle); - int (*set_power_state)(void *handle); - void (*post_set_power_state)(void *handle); - void (*display_configuration_changed)(void *handle); - void (*print_power_state)(void *handle, void *ps); - bool (*vblank_too_short)(void *handle); - void (*enable_bapm)(void *handle, bool enable); - int (*check_state_equal)(void *handle, - void *cps, - void *rps, - bool *equal); -/* export for sysfs */ - int (*get_temperature)(void *handle); - void (*set_fan_control_mode)(void *handle, u32 mode); - u32 (*get_fan_control_mode)(void *handle); - int (*set_fan_speed_percent)(void *handle, u32 speed); - int (*get_fan_speed_percent)(void *handle, u32 *speed); - int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); - int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); - int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); - int (*get_sclk_od)(void *handle); - int (*set_sclk_od)(void *handle, uint32_t value); - int (*get_mclk_od)(void *handle); - int (*set_mclk_od)(void *handle, uint32_t value); - int (*read_sensor)(void *handle, int idx, void *value, int *size); - enum amd_dpm_forced_level (*get_performance_level)(void *handle); - enum amd_pm_state_type (*get_current_power_state)(void *handle); - int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); - int (*get_pp_num_states)(void *handle, struct pp_states_info *data); - int (*get_pp_table)(void *handle, char **table); - int (*set_pp_table)(void *handle, const char *buf, size_t size); - void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); - - int (*reset_power_profile_state)(void *handle, - struct amd_pp_profile *request); - int (*get_power_profile_state)(void *handle, - struct amd_pp_profile *query); - int (*set_power_profile_state)(void *handle, - struct amd_pp_profile *request); - int (*switch_power_profile)(void *handle, - enum amd_pp_profile_type type); -/* export to amdgpu */ - void (*powergate_uvd)(void *handle, bool gate); - void (*powergate_vce)(void *handle, bool gate); - struct amd_vce_state* (*get_vce_clock_state)(void *handle, u32 idx); - int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, - void *input, void *output); - int (*load_firmware)(void *handle); - int (*wait_for_fw_loading_complete)(void *handle); - int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); -/* export to DC */ - u32 (*get_sclk)(void *handle, bool low); - u32 (*get_mclk)(void *handle, bool low); - int (*display_configuration_change)(void *handle, - const struct amd_pp_display_configuration *input); - int (*get_display_power_level)(void *handle, - struct amd_pp_simple_clock_info *output); - int (*get_current_clocks)(void *handle, - struct amd_pp_clock_info *clocks); - int (*get_clock_by_type)(void *handle, - enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks); - int (*get_clock_by_type_with_latency)(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks); - int (*get_clock_by_type_with_voltage)(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks); - int (*set_watermarks_for_clocks_ranges)(void *handle, - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - int (*display_clock_voltage_request)(void *handle, - struct pp_display_clock_request *clock); - int (*get_display_mode_validation_clocks)(void *handle, - struct amd_pp_simple_clock_info *clocks); -}; - - #endif /* __AMD_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h new file mode 100644 index 000000000000..b1e878ecf9bf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h @@ -0,0 +1,453 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_OFFSET_HEADER +#define _athub_1_0_OFFSET_HEADER + + + +// addressBlock: athub_atsdec +// base address: 0x3080 +#define mmATC_ATS_CNTL 0x0000 +#define mmATC_ATS_CNTL_BASE_IDX 0 +#define mmATC_ATS_STATUS 0x0003 +#define mmATC_ATS_STATUS_BASE_IDX 0 +#define mmATC_ATS_FAULT_CNTL 0x0004 +#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_INFO 0x0005 +#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006 +#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 +#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007 +#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 +#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008 +#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 +#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009 +#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 +#define mmATHUB_MISC_CNTL 0x000a +#define mmATHUB_MISC_CNTL_BASE_IDX 0 +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b +#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 +#define mmATC_VMID0_PASID_MAPPING 0x000c +#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID1_PASID_MAPPING 0x000d +#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID2_PASID_MAPPING 0x000e +#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID3_PASID_MAPPING 0x000f +#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID4_PASID_MAPPING 0x0010 +#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID5_PASID_MAPPING 0x0011 +#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID6_PASID_MAPPING 0x0012 +#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID7_PASID_MAPPING 0x0013 +#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID8_PASID_MAPPING 0x0014 +#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID9_PASID_MAPPING 0x0015 +#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID10_PASID_MAPPING 0x0016 +#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID11_PASID_MAPPING 0x0017 +#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID12_PASID_MAPPING 0x0018 +#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID13_PASID_MAPPING 0x0019 +#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID14_PASID_MAPPING 0x001a +#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID15_PASID_MAPPING 0x001b +#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0 +#define mmATC_ATS_VMID_STATUS 0x001c +#define mmATC_ATS_VMID_STATUS_BASE_IDX 0 +#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d +#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0 +#define mmATC_PERFCOUNTER0_CFG 0x001e +#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER1_CFG 0x001f +#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER2_CFG 0x0020 +#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER3_CFG 0x0021 +#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022 +#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmATC_PERFCOUNTER_LO 0x0023 +#define mmATC_PERFCOUNTER_LO_BASE_IDX 0 +#define mmATC_PERFCOUNTER_HI 0x0024 +#define mmATC_PERFCOUNTER_HI_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL 0x0025 +#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_PASID_CNTL 0x0026 +#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027 +#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028 +#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 +#define mmATHUB_COMMAND 0x0029 +#define mmATHUB_COMMAND_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a +#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b +#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c +#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d +#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e +#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f +#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030 +#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031 +#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032 +#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033 +#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034 +#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035 +#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036 +#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037 +#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038 +#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 +#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039 +#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 +#define mmATHUB_MEM_POWER_LS 0x003a +#define mmATHUB_MEM_POWER_LS_BASE_IDX 0 +#define mmATS_IH_CREDIT 0x003b +#define mmATS_IH_CREDIT_BASE_IDX 0 +#define mmATHUB_IH_CREDIT 0x003c +#define mmATHUB_IH_CREDIT_BASE_IDX 0 +#define mmATC_VMID16_PASID_MAPPING 0x003d +#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID17_PASID_MAPPING 0x003e +#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID18_PASID_MAPPING 0x003f +#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID19_PASID_MAPPING 0x0040 +#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID20_PASID_MAPPING 0x0041 +#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID21_PASID_MAPPING 0x0042 +#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID22_PASID_MAPPING 0x0043 +#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID23_PASID_MAPPING 0x0044 +#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID24_PASID_MAPPING 0x0045 +#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID25_PASID_MAPPING 0x0046 +#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID26_PASID_MAPPING 0x0047 +#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID27_PASID_MAPPING 0x0048 +#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID28_PASID_MAPPING 0x0049 +#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID29_PASID_MAPPING 0x004a +#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID30_PASID_MAPPING 0x004b +#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0 +#define mmATC_VMID31_PASID_MAPPING 0x004c +#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0 +#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d +#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0 +#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e +#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 +#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f +#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmATC_ATS_SDPPORT_CNTL 0x0050 +#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052 +#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053 +#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0 + + +// addressBlock: athub_xpbdec +// base address: 0x31f0 +#define mmXPB_RTR_SRC_APRTR0 0x005c +#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR1 0x005d +#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR2 0x005e +#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR3 0x005f +#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR4 0x0060 +#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR5 0x0061 +#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR6 0x0062 +#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR7 0x0063 +#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR8 0x0064 +#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0 +#define mmXPB_RTR_SRC_APRTR9 0x0065 +#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066 +#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067 +#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068 +#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0 +#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069 +#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP0 0x006a +#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP1 0x006b +#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP2 0x006c +#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP3 0x006d +#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP4 0x006e +#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP5 0x006f +#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP6 0x0070 +#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP7 0x0071 +#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP8 0x0072 +#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0 +#define mmXPB_RTR_DEST_MAP9 0x0073 +#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074 +#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075 +#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076 +#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0 +#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077 +#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0 +#define mmXPB_CLG_CFG0 0x0078 +#define mmXPB_CLG_CFG0_BASE_IDX 0 +#define mmXPB_CLG_CFG1 0x0079 +#define mmXPB_CLG_CFG1_BASE_IDX 0 +#define mmXPB_CLG_CFG2 0x007a +#define mmXPB_CLG_CFG2_BASE_IDX 0 +#define mmXPB_CLG_CFG3 0x007b +#define mmXPB_CLG_CFG3_BASE_IDX 0 +#define mmXPB_CLG_CFG4 0x007c +#define mmXPB_CLG_CFG4_BASE_IDX 0 +#define mmXPB_CLG_CFG5 0x007d +#define mmXPB_CLG_CFG5_BASE_IDX 0 +#define mmXPB_CLG_CFG6 0x007e +#define mmXPB_CLG_CFG6_BASE_IDX 0 +#define mmXPB_CLG_CFG7 0x007f +#define mmXPB_CLG_CFG7_BASE_IDX 0 +#define mmXPB_CLG_EXTRA 0x0080 +#define mmXPB_CLG_EXTRA_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_MSK 0x0081 +#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0 +#define mmXPB_LB_ADDR 0x0082 +#define mmXPB_LB_ADDR_BASE_IDX 0 +#define mmXPB_WCB_STS 0x0083 +#define mmXPB_WCB_STS_BASE_IDX 0 +#define mmXPB_HST_CFG 0x0084 +#define mmXPB_HST_CFG_BASE_IDX 0 +#define mmXPB_P2P_BAR_CFG 0x0085 +#define mmXPB_P2P_BAR_CFG_BASE_IDX 0 +#define mmXPB_P2P_BAR0 0x0086 +#define mmXPB_P2P_BAR0_BASE_IDX 0 +#define mmXPB_P2P_BAR1 0x0087 +#define mmXPB_P2P_BAR1_BASE_IDX 0 +#define mmXPB_P2P_BAR2 0x0088 +#define mmXPB_P2P_BAR2_BASE_IDX 0 +#define mmXPB_P2P_BAR3 0x0089 +#define mmXPB_P2P_BAR3_BASE_IDX 0 +#define mmXPB_P2P_BAR4 0x008a +#define mmXPB_P2P_BAR4_BASE_IDX 0 +#define mmXPB_P2P_BAR5 0x008b +#define mmXPB_P2P_BAR5_BASE_IDX 0 +#define mmXPB_P2P_BAR6 0x008c +#define mmXPB_P2P_BAR6_BASE_IDX 0 +#define mmXPB_P2P_BAR7 0x008d +#define mmXPB_P2P_BAR7_BASE_IDX 0 +#define mmXPB_P2P_BAR_SETUP 0x008e +#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0 +#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090 +#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0 +#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091 +#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR0 0x0092 +#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR1 0x0093 +#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR2 0x0094 +#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR3 0x0095 +#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR4 0x0096 +#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR5 0x0097 +#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR6 0x0098 +#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR7 0x0099 +#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR8 0x009a +#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0 +#define mmXPB_PEER_SYS_BAR9 0x009b +#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c +#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d +#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e +#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0 +#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f +#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0 +#define mmXPB_CLK_GAT 0x00a0 +#define mmXPB_CLK_GAT_BASE_IDX 0 +#define mmXPB_INTF_CFG 0x00a1 +#define mmXPB_INTF_CFG_BASE_IDX 0 +#define mmXPB_INTF_STS 0x00a2 +#define mmXPB_INTF_STS_BASE_IDX 0 +#define mmXPB_PIPE_STS 0x00a3 +#define mmXPB_PIPE_STS_BASE_IDX 0 +#define mmXPB_SUB_CTRL 0x00a4 +#define mmXPB_SUB_CTRL_BASE_IDX 0 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5 +#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0 +#define mmXPB_PERF_KNOBS 0x00a6 +#define mmXPB_PERF_KNOBS_BASE_IDX 0 +#define mmXPB_STICKY 0x00a7 +#define mmXPB_STICKY_BASE_IDX 0 +#define mmXPB_STICKY_W1C 0x00a8 +#define mmXPB_STICKY_W1C_BASE_IDX 0 +#define mmXPB_MISC_CFG 0x00a9 +#define mmXPB_MISC_CFG_BASE_IDX 0 +#define mmXPB_INTF_CFG2 0x00aa +#define mmXPB_INTF_CFG2_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_RD 0x00ab +#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0 +#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac +#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0 +#define mmXPB_CLG_GFX_MATCH 0x00ad +#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0 +#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae +#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0 +#define mmXPB_CLG_MM_MATCH 0x00af +#define mmXPB_CLG_MM_MATCH_BASE_IDX 0 +#define mmXPB_CLG_MM_MATCH_MSK 0x00b0 +#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1 +#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2 +#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3 +#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4 +#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5 +#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6 +#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7 +#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0 +#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8 +#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9 +#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba +#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb +#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0 +#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc +#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0 + + +// addressBlock: athub_rpbdec +// base address: 0x33b0 +#define mmRPB_PASSPW_CONF 0x00cc +#define mmRPB_PASSPW_CONF_BASE_IDX 0 +#define mmRPB_BLOCKLEVEL_CONF 0x00cd +#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0 +#define mmRPB_TAG_CONF 0x00cf +#define mmRPB_TAG_CONF_BASE_IDX 0 +#define mmRPB_EFF_CNTL 0x00d1 +#define mmRPB_EFF_CNTL_BASE_IDX 0 +#define mmRPB_ARB_CNTL 0x00d2 +#define mmRPB_ARB_CNTL_BASE_IDX 0 +#define mmRPB_ARB_CNTL2 0x00d3 +#define mmRPB_ARB_CNTL2_BASE_IDX 0 +#define mmRPB_BIF_CNTL 0x00d4 +#define mmRPB_BIF_CNTL_BASE_IDX 0 +#define mmRPB_WR_SWITCH_CNTL 0x00d5 +#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0 +#define mmRPB_RD_SWITCH_CNTL 0x00d7 +#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0 +#define mmRPB_CID_QUEUE_WR 0x00d8 +#define mmRPB_CID_QUEUE_WR_BASE_IDX 0 +#define mmRPB_CID_QUEUE_RD 0x00d9 +#define mmRPB_CID_QUEUE_RD_BASE_IDX 0 +#define mmRPB_CID_QUEUE_EX 0x00dc +#define mmRPB_CID_QUEUE_EX_BASE_IDX 0 +#define mmRPB_CID_QUEUE_EX_DATA 0x00dd +#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0 +#define mmRPB_SWITCH_CNTL2 0x00de +#define mmRPB_SWITCH_CNTL2_BASE_IDX 0 +#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df +#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0 +#define mmRPB_VC_SWITCH_RDWR 0x00e0 +#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_LO 0x00e1 +#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_HI 0x00e2 +#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0 +#define mmRPB_PERFCOUNTER0_CFG 0x00e3 +#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER1_CFG 0x00e4 +#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER2_CFG 0x00e5 +#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER3_CFG 0x00e6 +#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0 +#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7 +#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define mmRPB_RD_QUEUE_CNTL 0x00e9 +#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0 +#define mmRPB_RD_QUEUE_CNTL2 0x00ea +#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0 +#define mmRPB_WR_QUEUE_CNTL 0x00eb +#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0 +#define mmRPB_WR_QUEUE_CNTL2 0x00ec +#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0 +#define mmRPB_EA_QUEUE_WR 0x00ed +#define mmRPB_EA_QUEUE_WR_BASE_IDX 0 +#define mmRPB_ATS_CNTL 0x00ee +#define mmRPB_ATS_CNTL_BASE_IDX 0 +#define mmRPB_ATS_CNTL2 0x00ef +#define mmRPB_ATS_CNTL2_BASE_IDX 0 +#define mmRPB_SDPPORT_CNTL 0x00f0 +#define mmRPB_SDPPORT_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h new file mode 100644 index 000000000000..2968c6e2f7b9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h @@ -0,0 +1,2045 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _athub_1_0_SH_MASK_HEADER +#define _athub_1_0_SH_MASK_HEADER + + +// addressBlock: athub_atsdec +//ATC_ATS_CNTL +#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 +#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 +#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 +#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 +#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 +#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 +#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 +#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L +#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L +#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L +#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L +#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L +#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L +#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L +//ATC_ATS_STATUS +#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 +#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 +#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 +#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L +#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L +#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L +#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L +#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L +//ATC_ATS_FAULT_CNTL +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 +#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL +#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L +#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L +//ATC_ATS_FAULT_STATUS_INFO +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 +#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 +#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL +#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L +#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L +#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L +#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L +#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L +//ATC_ATS_FAULT_STATUS_ADDR +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL +//ATC_ATS_DEFAULT_PAGE_LOW +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 +#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL +//ATC_TRANS_FAULT_RSPCNTRL +#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa +#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb +#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc +#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd +#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe +#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf +#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 +#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a +#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b +#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c +#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d +#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e +#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f +#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L +#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L +//ATC_ATS_FAULT_STATUS_INFO2 +#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 +#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 +#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 +#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L +#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL +#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L +//ATHUB_MISC_CNTL +#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 +#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 +#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 +#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 +#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 +#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b +#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c +#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L +#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L +#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L +#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L +#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L +#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L +#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L +//ATC_VMID_PASID_MAPPING_UPDATE_STATUS +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L +#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L +//ATC_VMID0_PASID_MAPPING +#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID1_PASID_MAPPING +#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID2_PASID_MAPPING +#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID3_PASID_MAPPING +#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID4_PASID_MAPPING +#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID5_PASID_MAPPING +#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID6_PASID_MAPPING +#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID7_PASID_MAPPING +#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID8_PASID_MAPPING +#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID9_PASID_MAPPING +#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID10_PASID_MAPPING +#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID11_PASID_MAPPING +#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID12_PASID_MAPPING +#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID13_PASID_MAPPING +#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID14_PASID_MAPPING +#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID15_PASID_MAPPING +#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_ATS_VMID_STATUS +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf +#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 +#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 +#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 +#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 +#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 +#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 +#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 +#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 +#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 +#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 +#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a +#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b +#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c +#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d +#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e +#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f +#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L +#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L +#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L +#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L +#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L +#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L +#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L +#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L +#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L +#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L +#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L +#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L +#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L +#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L +#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L +#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L +#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L +#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L +#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L +#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L +#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L +#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L +#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L +#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L +#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L +#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L +#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L +#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L +#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L +#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L +#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L +#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L +//ATC_ATS_GFX_ATCL2_STATUS +#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 +#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L +//ATC_PERFCOUNTER0_CFG +#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER1_CFG +#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER2_CFG +#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER3_CFG +#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//ATC_PERFCOUNTER_RSLT_CNTL +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//ATC_PERFCOUNTER_LO +#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATC_PERFCOUNTER_HI +#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//ATHUB_PCIE_ATS_CNTL +#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_PASID_CNTL +#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 +#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 +#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 +#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L +#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L +#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L +//ATHUB_PCIE_PAGE_REQ_CNTL +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L +#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L +//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//ATHUB_COMMAND +#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L +//ATHUB_PCIE_ATS_CNTL_VF_0 +#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_1 +#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_2 +#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_3 +#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_4 +#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_5 +#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_6 +#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_7 +#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_8 +#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_9 +#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_10 +#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_11 +#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_12 +#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_13 +#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_14 +#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//ATHUB_PCIE_ATS_CNTL_VF_15 +#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//ATHUB_MEM_POWER_LS +#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATS_IH_CREDIT +#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//ATHUB_IH_CREDIT +#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//ATC_VMID16_PASID_MAPPING +#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID17_PASID_MAPPING +#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID18_PASID_MAPPING +#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID19_PASID_MAPPING +#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID20_PASID_MAPPING +#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID21_PASID_MAPPING +#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID22_PASID_MAPPING +#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID23_PASID_MAPPING +#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID24_PASID_MAPPING +#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID25_PASID_MAPPING +#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID26_PASID_MAPPING +#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID27_PASID_MAPPING +#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID28_PASID_MAPPING +#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID29_PASID_MAPPING +#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID30_PASID_MAPPING +#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_VMID31_PASID_MAPPING +#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 +#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e +#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f +#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL +#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L +#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L +//ATC_ATS_MMHUB_ATCL2_STATUS +#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 +#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L +//ATHUB_SHARED_VIRT_RESET_REQ +#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//ATHUB_SHARED_ACTIVE_FCN_ID +#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//ATC_ATS_SDPPORT_CNTL +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe +#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L +#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L +#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L +//ATC_ATS_VMID_SNAPSHOT_GFX_STAT +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L +#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L +//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L +#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L + + +// addressBlock: athub_xpbdec +//XPB_RTR_SRC_APRTR0 +#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR1 +#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR2 +#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR3 +#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR4 +#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR5 +#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR6 +#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR7 +#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR8 +#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_SRC_APRTR9 +#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 +#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR0 +#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR1 +#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR2 +#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_XDMA_RTR_SRC_APRTR3 +#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 +#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL +//XPB_RTR_DEST_MAP0 +#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP1 +#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP2 +#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP3 +#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP4 +#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP5 +#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP6 +#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP7 +#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP8 +#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L +//XPB_RTR_DEST_MAP9 +#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 +#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 +#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 +#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a +#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L +#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L +#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP0 +#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP1 +#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP2 +#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L +//XPB_XDMA_RTR_DEST_MAP3 +#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 +#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a +#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L +#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L +#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L +#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L +//XPB_CLG_CFG0 +#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG1 +#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG2 +#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG3 +#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG4 +#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG5 +#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG6 +#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_CFG7 +#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 +#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 +#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa +#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL +#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L +#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L +//XPB_CLG_EXTRA +#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb +#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc +#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf +#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 +#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a +#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b +#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L +#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L +#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L +#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L +#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L +#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L +//XPB_CLG_EXTRA_MSK +#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb +#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 +#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L +#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L +//XPB_LB_ADDR +#define XPB_LB_ADDR__CMP0__SHIFT 0x0 +#define XPB_LB_ADDR__MASK0__SHIFT 0xa +#define XPB_LB_ADDR__CMP1__SHIFT 0x14 +#define XPB_LB_ADDR__MASK1__SHIFT 0x1a +#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL +#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L +#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L +#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L +//XPB_WCB_STS +#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 +#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 +#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 +#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL +#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L +#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L +//XPB_HST_CFG +#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 +#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L +//XPB_P2P_BAR_CFG +#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 +#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 +#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 +#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 +#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 +#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 +#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa +#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb +#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc +#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL +#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L +#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L +#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L +#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L +#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L +#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L +#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L +#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L +//XPB_P2P_BAR0 +#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR0__VALID__SHIFT 0xc +#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR0__VALID_MASK 0x00001000L +#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR1 +#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR1__VALID__SHIFT 0xc +#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR1__VALID_MASK 0x00001000L +#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR2 +#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR2__VALID__SHIFT 0xc +#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR2__VALID_MASK 0x00001000L +#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR3 +#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR3__VALID__SHIFT 0xc +#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR3__VALID_MASK 0x00001000L +#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR4 +#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR4__VALID__SHIFT 0xc +#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR4__VALID_MASK 0x00001000L +#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR5 +#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR5__VALID__SHIFT 0xc +#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR5__VALID_MASK 0x00001000L +#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR6 +#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR6__VALID__SHIFT 0xc +#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR6__VALID_MASK 0x00001000L +#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR7 +#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 +#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 +#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR7__VALID__SHIFT 0xc +#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL +#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L +#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR7__VALID_MASK 0x00001000L +#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR_SETUP +#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 +#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 +#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc +#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd +#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe +#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf +#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 +#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL +#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L +#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L +#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L +#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L +#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L +#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L +//XPB_P2P_BAR_DELTA_ABOVE +#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 +#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 +#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL +#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L +//XPB_P2P_BAR_DELTA_BELOW +#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 +#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 +#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL +#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L +//XPB_PEER_SYS_BAR0 +#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR1 +#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR2 +#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR3 +#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR4 +#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR5 +#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR6 +#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR7 +#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR8 +#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL +//XPB_PEER_SYS_BAR9 +#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 +#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 +#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L +#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR0 +#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR1 +#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR2 +#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL +//XPB_XDMA_PEER_SYS_BAR3 +#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 +#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 +#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L +#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL +//XPB_CLK_GAT +#define XPB_CLK_GAT__ONDLY__SHIFT 0x0 +#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 +#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc +#define XPB_CLK_GAT__ENABLE__SHIFT 0x12 +#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 +#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL +#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L +#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L +#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L +#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L +//XPB_INTF_CFG +#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 +#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 +#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 +#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 +#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 +#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 +#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a +#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b +#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d +#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e +#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f +#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL +#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L +#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L +#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L +#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L +#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L +#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L +#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L +#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L +#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L +#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L +//XPB_INTF_STS +#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 +#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 +#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf +#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 +#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 +#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 +#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 +#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL +#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L +#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L +#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L +#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L +#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L +#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L +//XPB_PIPE_STS +#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 +#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 +#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 +#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf +#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 +#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 +#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 +#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 +#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 +#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 +#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 +#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 +#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 +#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L +#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL +#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L +#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L +#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L +#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L +#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L +#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L +#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L +#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L +#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L +#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L +#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L +//XPB_SUB_CTRL +#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 +#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 +#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 +#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 +#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 +#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 +#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 +#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 +#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 +#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 +#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa +#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb +#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc +#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd +#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe +#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf +#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 +#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 +#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 +#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 +#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L +#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L +#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L +#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L +#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L +#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L +#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L +#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L +#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L +#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L +#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L +#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L +#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L +#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L +#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L +#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L +#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L +#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L +#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L +#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L +//XPB_MAP_INVERT_FLUSH_NUM_LSB +#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 +#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL +//XPB_PERF_KNOBS +#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 +#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 +#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc +#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL +#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L +#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L +//XPB_STICKY +#define XPB_STICKY__BITS__SHIFT 0x0 +#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL +//XPB_STICKY_W1C +#define XPB_STICKY_W1C__BITS__SHIFT 0x0 +#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL +//XPB_MISC_CFG +#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 +#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 +#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 +#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 +#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f +#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL +#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L +#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L +#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L +#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L +//XPB_INTF_CFG2 +#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 +#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL +//XPB_CLG_EXTRA_RD +#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb +#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc +#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf +#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 +#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a +#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b +#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L +#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L +#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L +#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L +#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L +#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L +//XPB_CLG_EXTRA_MSK_RD +#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 +#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 +#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb +#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 +#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL +#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L +#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L +#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L +//XPB_CLG_GFX_MATCH +#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 +#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 +#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc +#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 +#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 +#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 +#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a +#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b +#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL +#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L +#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L +#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L +#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L +#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L +#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L +#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L +//XPB_CLG_GFX_MATCH_MSK +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L +#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L +//XPB_CLG_MM_MATCH +#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 +#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 +#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc +#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 +#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 +#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 +#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a +#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b +#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL +#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L +#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L +#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L +#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L +#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L +#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L +#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L +//XPB_CLG_MM_MATCH_MSK +#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc +#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 +#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL +#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L +#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L +#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L +//XPB_CLG_GFX_UNITID_MAPPING0 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING1 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING2 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING3 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING4 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING5 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING6 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_GFX_UNITID_MAPPING7 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING0 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING1 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING2 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L +//XPB_CLG_MM_UNITID_MAPPING3 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 +#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL +#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L +#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L + + +// addressBlock: athub_rpbdec +//RPB_PASSPW_CONF +#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 +#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 +#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 +#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 +#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 +#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 +#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 +#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 +#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L +#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L +#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L +#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L +#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L +#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L +#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L +#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L +#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L +#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L +#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L +#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L +#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L +//RPB_BLOCKLEVEL_CONF +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 +#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 +#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 +#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L +#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL +#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L +#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L +#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L +#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L +#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L +#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L +//RPB_TAG_CONF +#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 +#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 +#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 +#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL +#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L +#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L +//RPB_EFF_CNTL +#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 +#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 +#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL +#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L +//RPB_ARB_CNTL +#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 +#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 +#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 +#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 +#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 +#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL +#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L +#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L +#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L +//RPB_ARB_CNTL2 +#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 +#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 +#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 +#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL +#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L +//RPB_BIF_CNTL +#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 +#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 +#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 +#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 +#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 +#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 +#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b +#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c +#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d +#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e +#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL +#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L +#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L +#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L +#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L +#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L +#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L +#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L +#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L +#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L +//RPB_WR_SWITCH_CNTL +#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 +#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe +#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 +#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c +#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL +#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L +#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L +#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L +#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L +//RPB_RD_SWITCH_CNTL +#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 +#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 +#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe +#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 +#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c +#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL +#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L +#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L +#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L +#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L +//RPB_CID_QUEUE_WR +#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 +#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 +#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb +#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc +#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf +#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 +#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL +#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L +#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L +#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L +#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L +#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L +//RPB_CID_QUEUE_RD +#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 +#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 +#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb +#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe +#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL +#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L +#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L +#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L +//RPB_CID_QUEUE_EX +#define RPB_CID_QUEUE_EX__START__SHIFT 0x0 +#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 +#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L +#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL +//RPB_CID_QUEUE_EX_DATA +#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 +#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 +#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL +#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L +//RPB_SWITCH_CNTL2 +#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 +#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 +#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe +#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 +#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL +#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L +#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L +#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L +//RPB_DEINTRLV_COMBINE_CNTL +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL +#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L +#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L +//RPB_VC_SWITCH_RDWR +#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 +#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 +#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa +#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L +#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL +#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L +//RPB_PERFCOUNTER_LO +#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//RPB_PERFCOUNTER_HI +#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//RPB_PERFCOUNTER0_CFG +#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER1_CFG +#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER2_CFG +#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER3_CFG +#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//RPB_PERFCOUNTER_RSLT_CNTL +#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//RPB_RD_QUEUE_CNTL +#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 +#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 +#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 +#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 +#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 +#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L +#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L +#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L +#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L +#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L +#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L +#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L +//RPB_RD_QUEUE_CNTL2 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL +#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L +#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L +//RPB_WR_QUEUE_CNTL +#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 +#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 +#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 +#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 +#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 +#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L +#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L +#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L +#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L +#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L +#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L +#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L +//RPB_WR_QUEUE_CNTL2 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL +#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L +#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L +//RPB_EA_QUEUE_WR +#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 +#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 +#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 +#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb +#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL +#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L +#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L +#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L +//RPB_ATS_CNTL +#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 +#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 +#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 +#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 +#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf +#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 +#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 +#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 +#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L +#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L +#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL +#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L +#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L +#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L +#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L +#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L +//RPB_ATS_CNTL2 +#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 +#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 +#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc +#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf +#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 +#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL +#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L +#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L +#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L +#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L +//RPB_SDPPORT_CNTL +#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 +#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 +#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 +#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa +#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf +#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 +#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 +#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b +#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L +#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L +#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L +#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L +#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L +#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L +#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L +#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L +#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L +#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L +#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h index f730d0629020..f730d0629020 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h index 6d3162c42957..6d3162c42957 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h index 4ccf9681c45d..4ccf9681c45d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h index b28d4b64c05d..b28d4b64c05d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h index 663d3af35baf..663d3af35baf 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index e6d6171aa8b9..e6d6171aa8b9 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 5c5e9b445432..5c5e9b445432 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h index db7ef5ede0e5..db7ef5ede0e5 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h new file mode 100644 index 000000000000..94325fc3abd5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _hdp_4_0_OFFSET_HEADER +#define _hdp_4_0_OFFSET_HEADER + + + +// addressBlock: hdp_hdpdec +// base address: 0x3c80 +#define mmHDP_MMHUB_TLVL 0x0000 +#define mmHDP_MMHUB_TLVL_BASE_IDX 0 +#define mmHDP_MMHUB_UNITID 0x0001 +#define mmHDP_MMHUB_UNITID_BASE_IDX 0 +#define mmHDP_NONSURFACE_BASE 0x0040 +#define mmHDP_NONSURFACE_BASE_BASE_IDX 0 +#define mmHDP_NONSURFACE_INFO 0x0041 +#define mmHDP_NONSURFACE_INFO_BASE_IDX 0 +#define mmHDP_NONSURFACE_BASE_HI 0x0042 +#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0 +#define mmHDP_NONSURF_FLAGS 0x00c8 +#define mmHDP_NONSURF_FLAGS_BASE_IDX 0 +#define mmHDP_NONSURF_FLAGS_CLR 0x00c9 +#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 +#define mmHDP_HOST_PATH_CNTL 0x00cc +#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0 +#define mmHDP_SW_SEMAPHORE 0x00cd +#define mmHDP_SW_SEMAPHORE_BASE_IDX 0 +#define mmHDP_DEBUG0 0x00ce +#define mmHDP_DEBUG0_BASE_IDX 0 +#define mmHDP_LAST_SURFACE_HIT 0x00d0 +#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0 +#define mmHDP_READ_CACHE_INVALIDATE 0x00d1 +#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0 +#define mmHDP_OUTSTANDING_REQ 0x00d2 +#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0 +#define mmHDP_MISC_CNTL 0x00d3 +#define mmHDP_MISC_CNTL_BASE_IDX 0 +#define mmHDP_MEM_POWER_LS 0x00d4 +#define mmHDP_MEM_POWER_LS_BASE_IDX 0 +#define mmHDP_MMHUB_CNTL 0x00d5 +#define mmHDP_MMHUB_CNTL_BASE_IDX 0 +#define mmHDP_EDC_CNT 0x00d6 +#define mmHDP_EDC_CNT_BASE_IDX 0 +#define mmHDP_VERSION 0x00d7 +#define mmHDP_VERSION_BASE_IDX 0 +#define mmHDP_CLK_CNTL 0x00d8 +#define mmHDP_CLK_CNTL_BASE_IDX 0 +#define mmHDP_MEMIO_CNTL 0x00f6 +#define mmHDP_MEMIO_CNTL_BASE_IDX 0 +#define mmHDP_MEMIO_ADDR 0x00f7 +#define mmHDP_MEMIO_ADDR_BASE_IDX 0 +#define mmHDP_MEMIO_STATUS 0x00f8 +#define mmHDP_MEMIO_STATUS_BASE_IDX 0 +#define mmHDP_MEMIO_WR_DATA 0x00f9 +#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0 +#define mmHDP_MEMIO_RD_DATA 0x00fa +#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0 +#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100 +#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 +#define mmHDP_XDP_D2H_FLUSH 0x0101 +#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0 +#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102 +#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_3 0x0103 +#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_4 0x0104 +#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_5 0x0105 +#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_6 0x0106 +#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_7 0x0107 +#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_8 0x0108 +#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_9 0x0109 +#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_10 0x010a +#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_11 0x010b +#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_12 0x010c +#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_13 0x010d +#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_14 0x010e +#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_15 0x010f +#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_16 0x0110 +#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_17 0x0111 +#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_18 0x0112 +#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_19 0x0113 +#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_20 0x0114 +#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_21 0x0115 +#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_22 0x0116 +#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_23 0x0117 +#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_24 0x0118 +#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_25 0x0119 +#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_26 0x011a +#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_27 0x011b +#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_28 0x011c +#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_29 0x011d +#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_30 0x011e +#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_31 0x011f +#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_32 0x0120 +#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_33 0x0121 +#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0 +#define mmHDP_XDP_D2H_RSVD_34 0x0122 +#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0 +#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123 +#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR_CFG 0x0124 +#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125 +#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126 +#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127 +#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128 +#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129 +#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a +#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b +#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 +#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c +#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 +#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d +#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 +#define mmHDP_XDP_HDP_MC_CFG 0x012e +#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0 +#define mmHDP_XDP_HST_CFG 0x012f +#define mmHDP_XDP_HST_CFG_BASE_IDX 0 +#define mmHDP_XDP_HDP_IPH_CFG 0x0131 +#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR0 0x0134 +#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR1 0x0135 +#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR2 0x0136 +#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR3 0x0137 +#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR4 0x0138 +#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR5 0x0139 +#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR6 0x013a +#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0 +#define mmHDP_XDP_P2P_BAR7 0x013b +#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0 +#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c +#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 +#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d +#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 +#define mmHDP_XDP_BUSY_STS 0x013e +#define mmHDP_XDP_BUSY_STS_BASE_IDX 0 +#define mmHDP_XDP_STICKY 0x013f +#define mmHDP_XDP_STICKY_BASE_IDX 0 +#define mmHDP_XDP_CHKN 0x0140 +#define mmHDP_XDP_CHKN_BASE_IDX 0 +#define mmHDP_XDP_BARS_ADDR_39_36 0x0144 +#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 +#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 +#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 +#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148 +#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmHDP_XDP_MMHUB_ERROR 0x0149 +#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h new file mode 100644 index 000000000000..25e28691d62d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h @@ -0,0 +1,601 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _hdp_4_0_SH_MASK_HEADER +#define _hdp_4_0_SH_MASK_HEADER + + +// addressBlock: hdp_hdpdec +//HDP_MMHUB_TLVL +#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 +#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 +#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 +#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc +#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 +#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L +#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L +#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L +#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L +#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L +//HDP_MMHUB_UNITID +#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 +#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 +#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 +#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL +#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L +#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L +//HDP_NONSURFACE_BASE +#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 +#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL +//HDP_NONSURFACE_INFO +#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 +#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 +#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L +#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L +//HDP_NONSURFACE_BASE_HI +#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 +#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL +//HDP_NONSURF_FLAGS +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 +#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L +#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L +//HDP_NONSURF_FLAGS_CLR +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 +#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L +#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L +//HDP_HOST_PATH_CNTL +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f +#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L +#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L +#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L +#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L +#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L +#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L +//HDP_SW_SEMAPHORE +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 +#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL +//HDP_DEBUG0 +#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 +#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL +//HDP_LAST_SURFACE_HIT +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 +#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L +//HDP_READ_CACHE_INVALIDATE +#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 +#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L +//HDP_OUTSTANDING_REQ +#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 +#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 +#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL +#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L +//HDP_MISC_CNTL +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 +#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 +#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb +#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 +#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 +#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 +#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 +#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a +#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b +#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c +#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d +#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e +#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L +#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL +#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L +#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L +#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L +#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L +#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L +#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L +#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L +#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L +#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L +#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L +#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L +#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L +//HDP_MEM_POWER_LS +#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 +#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 +#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L +#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L +//HDP_MMHUB_CNTL +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 +#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 +#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L +#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L +#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L +//HDP_EDC_CNT +#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 +#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 +#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L +#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL +//HDP_VERSION +#define HDP_VERSION__MINVER__SHIFT 0x0 +#define HDP_VERSION__MAJVER__SHIFT 0x8 +#define HDP_VERSION__REV__SHIFT 0x10 +#define HDP_VERSION__MINVER_MASK 0x000000FFL +#define HDP_VERSION__MAJVER_MASK 0x0000FF00L +#define HDP_VERSION__REV_MASK 0x00FF0000L +//HDP_CLK_CNTL +#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 +#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 +#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c +#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d +#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e +#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f +#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL +#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L +#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L +#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L +#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L +#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L +//HDP_MEMIO_CNTL +#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 +#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 +#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf +#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 +#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 +#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L +#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L +#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL +#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L +#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L +#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L +#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L +#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L +#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L +#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L +//HDP_MEMIO_ADDR +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 +#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL +//HDP_MEMIO_STATUS +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 +#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L +#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L +#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L +#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L +//HDP_MEMIO_WR_DATA +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 +#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL +//HDP_MEMIO_RD_DATA +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 +#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL +//HDP_XDP_DIRECT2HDP_FIRST +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_FLUSH +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L +#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L +//HDP_XDP_D2H_BAR_UPDATE +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L +#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L +//HDP_XDP_D2H_RSVD_3 +#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_4 +#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_5 +#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_6 +#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_7 +#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_8 +#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_9 +#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_10 +#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_11 +#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_12 +#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_13 +#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_14 +#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_15 +#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_16 +#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_17 +#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_18 +#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_19 +#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_20 +#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_21 +#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_22 +#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_23 +#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_24 +#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_25 +#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_26 +#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_27 +#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_28 +#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_29 +#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_30 +#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_31 +#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_32 +#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_33 +#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_D2H_RSVD_34 +#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 +#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_DIRECT2HDP_LAST +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 +#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL +//HDP_XDP_P2P_BAR_CFG +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL +#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L +//HDP_XDP_P2P_MBX_OFFSET +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL +//HDP_XDP_P2P_MBX_ADDR0 +#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR1 +#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR2 +#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR3 +#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR4 +#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR5 +#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_P2P_MBX_ADDR6 +#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 +#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L +//HDP_XDP_HDP_MBX_MC_CFG +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L +#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L +//HDP_XDP_HDP_MC_CFG +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L +#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L +//HDP_XDP_HST_CFG +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 +#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L +#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L +#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L +//HDP_XDP_HDP_IPH_CFG +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L +#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L +//HDP_XDP_P2P_BAR0 +#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR1 +#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR2 +#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR3 +#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR4 +#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR5 +#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR6 +#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L +//HDP_XDP_P2P_BAR7 +#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 +#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 +#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 +#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL +#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L +#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L +//HDP_XDP_FLUSH_ARMED_STS +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL +//HDP_XDP_FLUSH_CNTR0_STS +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 +#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL +//HDP_XDP_BUSY_STS +#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 +#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL +//HDP_XDP_STICKY +#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 +#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 +#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL +#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L +//HDP_XDP_CHKN +#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 +#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 +#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 +#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 +#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL +#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L +#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L +#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L +//HDP_XDP_BARS_ADDR_39_36 +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c +#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL +#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L +#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L +#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L +#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L +#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L +#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L +#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L +//HDP_XDP_MC_VM_FB_LOCATION_BASE +#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL +//HDP_XDP_GPU_IOV_VIOLATION_LOG +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//HDP_XDP_MMHUB_ERROR +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L +#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L +#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L +#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L +#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L +#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L +#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h index 02989fe9f7bd..02989fe9f7bd 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h index 352ffae7a7ca..352ffae7a7ca 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h index 34278ef2aa1b..34278ef2aa1b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h index 4b6fc7242277..4b6fc7242277 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h index 8effec70a3c0..8effec70a3c0 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_default.h index f087a2bf3863..f087a2bf3863 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h index 1063e5e8ea0e..1063e5e8ea0e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h index 9b0c8c575160..9b0c8c575160 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MP/mp_10_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_10_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h new file mode 100644 index 000000000000..299e5266a8c0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h @@ -0,0 +1,375 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_9_0_OFFSET_HEADER +#define _mp_9_0_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define mmMP0_SMN_C2PMSG_32 0x0060 +#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_33 0x0061 +#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_34 0x0062 +#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_35 0x0063 +#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_36 0x0064 +#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_37 0x0065 +#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_38 0x0066 +#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_39 0x0067 +#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_40 0x0068 +#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_41 0x0069 +#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_42 0x006a +#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_43 0x006b +#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_44 0x006c +#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_45 0x006d +#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_46 0x006e +#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_47 0x006f +#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_48 0x0070 +#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_49 0x0071 +#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_50 0x0072 +#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_51 0x0073 +#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_52 0x0074 +#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_53 0x0075 +#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_54 0x0076 +#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_55 0x0077 +#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_56 0x0078 +#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_57 0x0079 +#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_58 0x007a +#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_59 0x007b +#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_60 0x007c +#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_61 0x007d +#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_62 0x007e +#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_63 0x007f +#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_64 0x0080 +#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_65 0x0081 +#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_66 0x0082 +#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_67 0x0083 +#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_68 0x0084 +#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_69 0x0085 +#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_70 0x0086 +#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_71 0x0087 +#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_72 0x0088 +#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_73 0x0089 +#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_74 0x008a +#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_75 0x008b +#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_76 0x008c +#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_77 0x008d +#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_78 0x008e +#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_79 0x008f +#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_80 0x0090 +#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_81 0x0091 +#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_82 0x0092 +#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_83 0x0093 +#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_84 0x0094 +#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_85 0x0095 +#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_86 0x0096 +#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_87 0x0097 +#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_88 0x0098 +#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_89 0x0099 +#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_90 0x009a +#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_91 0x009b +#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_92 0x009c +#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_93 0x009d +#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_94 0x009e +#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_95 0x009f +#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_96 0x00a0 +#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_97 0x00a1 +#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_98 0x00a2 +#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_99 0x00a3 +#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_100 0x00a4 +#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_101 0x00a5 +#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_102 0x00a6 +#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_103 0x00a7 +#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 +#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmMP0_SMN_IH_CREDIT 0x00c1 +#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT 0x00c2 +#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define mmMP1_SMN_ACP2MP_RESP 0x0240 +#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_DC2MP_RESP 0x0241 +#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_UVD2MP_RESP 0x0242 +#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_VCE2MP_RESP 0x0243 +#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_RLC2MP_RESP 0x0244 +#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_32 0x0260 +#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_33 0x0261 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_34 0x0262 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_35 0x0263 +#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_36 0x0264 +#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_37 0x0265 +#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_38 0x0266 +#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_39 0x0267 +#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_40 0x0268 +#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_41 0x0269 +#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_42 0x026a +#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_43 0x026b +#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_44 0x026c +#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_45 0x026d +#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_46 0x026e +#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_47 0x026f +#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_48 0x0270 +#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_49 0x0271 +#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_50 0x0272 +#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_51 0x0273 +#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_52 0x0274 +#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_55 0x0277 +#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_56 0x0278 +#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_57 0x0279 +#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_58 0x027a +#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_59 0x027b +#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_60 0x027c +#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_61 0x027d +#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_62 0x027e +#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_63 0x027f +#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_64 0x0280 +#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_65 0x0281 +#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_67 0x0283 +#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_68 0x0284 +#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_69 0x0285 +#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_70 0x0286 +#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_71 0x0287 +#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_72 0x0288 +#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_73 0x0289 +#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_74 0x028a +#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_76 0x028c +#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_77 0x028d +#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_78 0x028e +#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_79 0x028f +#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_80 0x0290 +#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_81 0x0291 +#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_83 0x0293 +#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_84 0x0294 +#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_85 0x0295 +#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_86 0x0296 +#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_87 0x0297 +#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_88 0x0298 +#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_89 0x0299 +#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_91 0x029b +#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_92 0x029c +#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_93 0x029d +#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_94 0x029e +#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_95 0x029f +#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_96 0x02a0 +#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_97 0x02a1 +#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_98 0x02a2 +#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_99 0x02a3 +#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_100 0x02a4 +#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_101 0x02a5 +#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_102 0x02a6 +#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_103 0x02a7 +#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 +#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmMP1_SMN_IH_CREDIT 0x02c1 +#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT 0x02c2 +#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define mmMP1_SMN_FPS_CNT 0x02c4 +#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 +#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 +#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 +#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 +#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 +#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 +#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 +#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 +#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 +#define mmMP1_SMN_EXT_SCRATCH8 0x03c8 +#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1Pub_CruDec +// base address: 0x0 +#define mmMP1_SMN_PUB_CTRL 0x02c5 +#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 + + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h new file mode 100644 index 000000000000..d5a623deca77 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h @@ -0,0 +1,1463 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_9_0_SH_MASK_HEADER +#define _mp_9_0_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_ACTIVE_FCN_ID +#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL +//MP0_SMN_IH_SW_INT_CTRL +#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_ACP2MP_RESP +#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_DC2MP_RESP +#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_UVD2MP_RESP +#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_VCE2MP_RESP +#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_RLC2MP_RESP +#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_ACTIVE_FCN_ID +#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH8 +#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL + + + + +// addressBlock: mp_SmuMp0Pub_CruDec +//MP0_SOC_INFO +#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 +#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 +#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L +#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL +//MP0_PUB_SCRATCH0 +#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP0_PUB_SCRATCH1 +#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP0_PUB_SCRATCH2 +#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP0_PUB_SCRATCH3 +#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 +#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP0_FW_INTF +#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 +#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L +//MP0_C2PMSG_0 +#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_1 +#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_2 +#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_3 +#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_4 +#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_5 +#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_6 +#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_7 +#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_8 +#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_9 +#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_10 +#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_11 +#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_12 +#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_13 +#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_14 +#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_15 +#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_16 +#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_17 +#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_18 +#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_19 +#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_20 +#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_21 +#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_22 +#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_23 +#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_24 +#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_25 +#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_26 +#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_27 +#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_28 +#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_29 +#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_30 +#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_31 +#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_0 +#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_1 +#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_2 +#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_3 +#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2CMSG_INTEN +#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP0_P2CMSG_INTSTS +#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP0_C2PMSG_ATTR_0 +#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_1 +#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_2 +#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_3 +#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_4 +#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_5 +#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL +//MP0_C2PMSG_ATTR_6 +#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 +#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL +//MP0_P2CMSG_ATTR +#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 +#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL +//MP0_P2SMSG_0 +#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_1 +#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_2 +#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_3 +#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 +#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP0_P2SMSG_ATTR +#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 +#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL +//MP0_S2PMSG_ATTR +#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 +#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L +//MP0_P2SMSG_INTSTS +#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP0_S2PMSG_0 +#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 +#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_32 +#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_33 +#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_34 +#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_35 +#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_36 +#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_37 +#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_38 +#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_39 +#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_40 +#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_41 +#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_42 +#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_43 +#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_44 +#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_45 +#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_46 +#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_47 +#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_48 +#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_49 +#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_50 +#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_51 +#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_52 +#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_53 +#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_54 +#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_55 +#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_56 +#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_57 +#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_58 +#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_59 +#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_60 +#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_61 +#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_62 +#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_63 +#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_64 +#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_65 +#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_66 +#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_67 +#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_68 +#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_69 +#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_70 +#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_71 +#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_72 +#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_73 +#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_74 +#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_75 +#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_76 +#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_77 +#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_78 +#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_79 +#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_80 +#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_81 +#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_82 +#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_83 +#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_84 +#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_85 +#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_86 +#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_87 +#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_88 +#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_89 +#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_90 +#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_91 +#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_92 +#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_93 +#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_94 +#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_95 +#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_96 +#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_97 +#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_98 +#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_99 +#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_100 +#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_101 +#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_102 +#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_C2PMSG_103 +#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_ACTIVE_FCN_ID +#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP0_IH_CREDIT +#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_IH_SW_INT +#define MP0_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_IH_SW_INT_CTRL +#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +//CGTT_DRM_CLK_CTRL0 +#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L +#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//DRM_LIGHT_SLEEP_CTRL +#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 +#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_SMN_PUB_CTRL +#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 +#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MP1_PUB_SCRATCH0 +#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH1 +#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH2 +#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_PUB_SCRATCH3 +#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_C2PMSG_0 +#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_1 +#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_2 +#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_3 +#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_4 +#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_5 +#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_6 +#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_7 +#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_8 +#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_9 +#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_10 +#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_11 +#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_12 +#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_13 +#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_14 +#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_15 +#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_16 +#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_17 +#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_18 +#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_19 +#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_20 +#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_21 +#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_22 +#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_23 +#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_24 +#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_25 +#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_26 +#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_27 +#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_28 +#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_29 +#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_30 +#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_31 +#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_0 +#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_1 +#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_2 +#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_3 +#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_INTEN +#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP1_P2CMSG_INTSTS +#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_P2SMSG_0 +#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_1 +#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_2 +#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_3 +#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2SMSG_INTSTS +#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_S2PMSG_0 +#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_ACP2MP_RESP +#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_DC2MP_RESP +#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_UVD2MP_RESP +#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_VCE2MP_RESP +#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_RLC2MP_RESP +#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 +#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_32 +#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_33 +#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_34 +#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_35 +#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_36 +#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_37 +#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_38 +#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_39 +#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_40 +#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_41 +#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_42 +#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_43 +#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_44 +#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_45 +#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_46 +#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_47 +#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_48 +#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_49 +#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_50 +#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_51 +#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_52 +#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_53 +#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_54 +#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_55 +#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_56 +#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_57 +#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_58 +#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_59 +#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_60 +#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_61 +#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_62 +#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_63 +#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_64 +#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_65 +#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_66 +#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_67 +#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_68 +#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_69 +#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_70 +#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_71 +#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_72 +#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_73 +#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_74 +#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_75 +#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_76 +#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_77 +#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_78 +#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_79 +#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_80 +#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_81 +#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_82 +#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_83 +#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_84 +#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_85 +#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_86 +#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_87 +#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_88 +#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_89 +#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_90 +#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_91 +#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_92 +#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_93 +#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_94 +#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_95 +#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_96 +#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_97 +#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_98 +#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_99 +#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_100 +#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_101 +#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_102 +#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_103 +#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_ACTIVE_FCN_ID +#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MP1_IH_CREDIT +#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_IH_SW_INT +#define MP1_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_IH_SW_INT_CTRL +#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_FPS_CNT +#define MP1_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_PUB_CTRL +#define MP1_PUB_CTRL__RESET__SHIFT 0x0 +#define MP1_PUB_CTRL__RESET_MASK 0x00000001L +//MP1_EXT_SCRATCH0 +#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH1 +#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH2 +#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH3 +#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH4 +#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH5 +#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH6 +#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_EXT_SCRATCH7 +#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h index 68d0ffad28c7..68d0ffad28c7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h index c7518b84f559..c7518b84f559 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h index 8058796d658a..8058796d658a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h index 13d4de645190..13d4de645190 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h index a02b67943372..a02b67943372 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h index f5fc31ffcd73..f5fc31ffcd73 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h index 435462294fbc..435462294fbc 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h index 88602479a1aa..88602479a1aa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h index 96ab3fe89620..96ab3fe89620 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h index 1ee3a2329ee4..1ee3a2329ee4 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h deleted file mode 100644 index eac125c9e300..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/DCN/dcn_1_0_default.h +++ /dev/null @@ -1,7988 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _dcn_1_0_DEFAULT_HEADER -#define _dcn_1_0_DEFAULT_HEADER - - -// addressBlock: dce_dc_hda_azcontroller_azdec -#define smnAZCONTROLLER0_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_MINOR_VERSION_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_MAJOR_VERSION_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_WAKE_ENABLE_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_STATE_CHANGE_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_GLOBAL_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_STREAM_SYNCHRONIZATION_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_WRITE_POINTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_READ_POINTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_CORB_SIZE_DEFAULT 0x00000002 -#define smnAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_WRITE_POINTER_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_CONTROL_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_RIRB_SIZE_DEFAULT 0x00000002 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azendpoint_azdec -#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azinputendpoint_azdec -#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azroot_azdec -#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define smnAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream0_azdec -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream1_azdec -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream2_azdec -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream3_azdec -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream4_azdec -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream5_azdec -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream6_azdec -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream7_azdec -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define smnAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] -#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] -#define mmCRTC8_IDX_DEFAULT 0x00000000 -#define mmCRTC8_DATA_DEFAULT 0x00000000 -#define mmGENFC_WT_DEFAULT 0x00000000 -#define mmGENS1_DEFAULT 0x00000000 -#define mmATTRDW_DEFAULT 0x00000000 -#define mmATTRX_DEFAULT 0x00000000 -#define mmATTRDR_DEFAULT 0x00000000 -#define mmGENMO_WT_DEFAULT 0x00000000 -#define mmGENS0_DEFAULT 0x00000000 -#define mmGENENB_DEFAULT 0x00000000 -#define mmSEQ8_IDX_DEFAULT 0x00000000 -#define mmSEQ8_DATA_DEFAULT 0x00000000 -#define mmDAC_MASK_DEFAULT 0x00000000 -#define mmDAC_R_INDEX_DEFAULT 0x00000000 -#define mmDAC_W_INDEX_DEFAULT 0x00000000 -#define mmDAC_DATA_DEFAULT 0x00000000 -#define mmGENFC_RD_DEFAULT 0x00000000 -#define mmGENMO_RD_DEFAULT 0x00000000 -#define mmGRPH8_IDX_DEFAULT 0x00000000 -#define mmGRPH8_DATA_DEFAULT 0x00000000 -#define mmCRTC8_IDX_1_DEFAULT 0x00000000 -#define mmCRTC8_DATA_1_DEFAULT 0x00000000 -#define mmGENFC_WT_1_DEFAULT 0x00000000 -#define mmGENS1_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azcontroller_azdec -#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmCORB_READ_POINTER_DEFAULT 0x00000000 -#define mmCORB_CONTROL_DEFAULT 0x00000000 -#define mmCORB_STATUS_DEFAULT 0x00000000 -#define mmCORB_SIZE_DEFAULT 0x00000002 -#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 -#define mmRIRB_CONTROL_DEFAULT 0x00000000 -#define mmRIRB_STATUS_DEFAULT 0x00000000 -#define mmRIRB_SIZE_DEFAULT 0x00000002 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azendpoint_azdec -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azinputendpoint_azdec -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azroot_azdec -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream0_azdec -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream1_azdec -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream2_azdec -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream3_azdec -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream4_azdec -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream5_azdec -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream6_azdec -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azstream7_azdec -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] - - -// addressBlock: dce_dc_mmhubbub_vga_dispdec -#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f -#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f -#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 -#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 -#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 -#define mmD1VGA_CONTROL_DEFAULT 0x00000000 -#define mmD2VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 -#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 -#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 -#define mmD3VGA_CONTROL_DEFAULT 0x00000000 -#define mmD4VGA_CONTROL_DEFAULT 0x00000000 -#define mmD5VGA_CONTROL_DEFAULT 0x00000000 -#define mmD6VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 - - -// addressBlock: dce_dc_dccg_dccg_dispdec -#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO_DBUF_EN_DEFAULT 0x00000000 -#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmREFCLK_CNTL_DEFAULT 0x00000000 -#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 -#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 -#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 -#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 -#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 -#define mmDCE_VERSION_DEFAULT 0x00000000 -#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 -#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 -#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 -#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 -#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 -#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 -#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 -#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028 -#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001 -#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800 -#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee02dd -#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmSOCCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000 -#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464 -#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x007f007f -#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000 -#define mmOTG0_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO0_MODULO_DEFAULT 0x00000000 -#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG1_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO1_MODULO_DEFAULT 0x00000000 -#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG2_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO2_MODULO_DEFAULT 0x00000000 -#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG3_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO3_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO3_MODULO_DEFAULT 0x00000000 -#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG4_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO4_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO4_MODULO_DEFAULT 0x00000000 -#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmOTG5_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO5_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO5_MODULO_DEFAULT 0x00000000 -#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDPPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000 -#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100 -#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200 -#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300 -#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400 -#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500 -#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000 -#define mmDVOACLKD_CNTL_DEFAULT 0x00070000 -#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000 -#define mmDVOACLKC_CNTL_DEFAULT 0x00030000 -#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030 -#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001 -#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001 -#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_CNT_CTRL_DEFAULT 0x00000000 -#define mmDCCG_VSYNC_CNT_INT_CTRL_DEFAULT 0x00000000 -#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff - - -// addressBlock: dce_dc_dccg_dccg_dfs_dispdec -#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064 - - -// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec -#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec -#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dccg_dccg_pll_dispdec -#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_rbbmif_dispdec -#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00 -#define mmRBBMIF_STATUS_DEFAULT 0x00000000 -#define mmRBBMIF_INT_STATUS_DEFAULT 0x80000000 -#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 -#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dc_pg_dispdec -#define mmDOMAIN0_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN0_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN1_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN1_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN2_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN2_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN3_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN3_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN4_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN4_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN5_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN5_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN6_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN6_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN7_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN7_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN8_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN8_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN9_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN9_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN10_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN10_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN11_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN11_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN12_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN12_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN13_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN13_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN14_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN14_PG_STATUS_DEFAULT 0x00000000 -#define mmDOMAIN15_PG_CONFIG_DEFAULT 0x00000001 -#define mmDOMAIN15_PG_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL_1_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL_2_DEFAULT 0x00000000 -#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000 -#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dmu_misc_dispdec -#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000 -#define mmDMU_CLK_CNTL_DEFAULT 0x00000000 -#define mmDMU_MEM_PWR_CNTL_DEFAULT 0x00000000 -#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_dmcu_dispdec -#define mmDMCU_CTRL_DEFAULT 0xffff0101 -#define mmDMCU_STATUS_DEFAULT 0x00000001 -#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004 -#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000 -#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000 -#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000 -#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000 -#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000 -#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000 -#define mmDMCU_INT_CNT_DEFAULT 0x00000000 -#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000 -#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102 -#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_DEFAULT 0x00000000 -#define mmDMCU_INT_CNT_CONTINUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmu_ihc_dispdec -#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE12_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE13_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE14_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE15_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE16_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE17_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE18_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE19_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE20_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE21_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE22_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_VREADY_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_FLIP_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec -#define mmCNV0_WB_ENABLE_DEFAULT 0x00000000 -#define mmCNV0_WB_EC_CONFIG_DEFAULT 0x55000000 -#define mmCNV0_CNV_MODE_DEFAULT 0x00000000 -#define mmCNV0_CNV_WINDOW_START_DEFAULT 0x00000000 -#define mmCNV0_CNV_WINDOW_SIZE_DEFAULT 0x00100010 -#define mmCNV0_CNV_UPDATE_DEFAULT 0x00000000 -#define mmCNV0_CNV_SOURCE_SIZE_DEFAULT 0x00100010 -#define mmCNV0_CNV_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C11_C12_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C13_C14_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C21_C22_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C23_C24_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C31_C32_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_C33_C34_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 -#define mmCNV0_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff -#define mmCNV0_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff -#define mmCNV0_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff -#define mmCNV0_CNV_TEST_CNTL_DEFAULT 0x00000000 -#define mmCNV0_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0 -#define mmCNV0_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 -#define mmCNV0_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 -#define mmCNV0_CNV_INPUT_SELECT_DEFAULT 0x00000001 -#define mmCNV0_WB_SOFT_RESET_DEFAULT 0x00000000 -#define mmCNV0_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 -#define mmCNV0_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 - - -// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec -#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_MODE_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_TAP_CONTROL_DEFAULT 0x00001111 -#define mmWBSCL0_WBSCL_DEST_SIZE_DEFAULT 0x00010001 -#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL0_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010 -#define mmWBSCL0_WBSCL_CLAMP_DEFAULT 0x01fe01fe -#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 -#define mmWBSCL0_WBSCL_TEST_CNTL_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 -#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff -#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 -#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 -#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 -#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec -#define mmCNV1_WB_ENABLE_DEFAULT 0x00000000 -#define mmCNV1_WB_EC_CONFIG_DEFAULT 0x55000000 -#define mmCNV1_CNV_MODE_DEFAULT 0x00000000 -#define mmCNV1_CNV_WINDOW_START_DEFAULT 0x00000000 -#define mmCNV1_CNV_WINDOW_SIZE_DEFAULT 0x00100010 -#define mmCNV1_CNV_UPDATE_DEFAULT 0x00000000 -#define mmCNV1_CNV_SOURCE_SIZE_DEFAULT 0x00100010 -#define mmCNV1_CNV_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C11_C12_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C13_C14_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C21_C22_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C23_C24_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C31_C32_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_C33_C34_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 -#define mmCNV1_CNV_CSC_CLAMP_R_DEFAULT 0x00000fff -#define mmCNV1_CNV_CSC_CLAMP_G_DEFAULT 0x00000fff -#define mmCNV1_CNV_CSC_CLAMP_B_DEFAULT 0x00000fff -#define mmCNV1_CNV_TEST_CNTL_DEFAULT 0x00000000 -#define mmCNV1_CNV_TEST_CRC_RED_DEFAULT 0x0000fff0 -#define mmCNV1_CNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 -#define mmCNV1_CNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 -#define mmCNV1_CNV_INPUT_SELECT_DEFAULT 0x00000001 -#define mmCNV1_WB_SOFT_RESET_DEFAULT 0x00000000 -#define mmCNV1_WB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 -#define mmCNV1_WB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 - - -// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec -#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_MODE_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_TAP_CONTROL_DEFAULT 0x00001111 -#define mmWBSCL1_WBSCL_DEST_SIZE_DEFAULT 0x00010001 -#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL1_WBSCL_ROUND_OFFSET_DEFAULT 0x00800010 -#define mmWBSCL1_WBSCL_CLAMP_DEFAULT 0x01fe01fe -#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 -#define mmWBSCL1_WBSCL_TEST_CNTL_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 -#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff -#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 -#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 -#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 -#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec -#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec -#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec -#define mmWBIF0_MISC_CTRL_DEFAULT 0x00010001 -#define mmWBIF0_SMU_WM_CONTROL_DEFAULT 0x00000000 -#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmWBIF1_MISC_CTRL_DEFAULT 0x00010001 -#define mmWBIF1_SMU_WM_CONTROL_DEFAULT 0x00000000 -#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmVGA_SRC_SPLIT_CNTL_DEFAULT 0x00000000 -#define mmMMHUBBUB_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmMMHUBBUB_MEM_PWR_CNTL_DEFAULT 0x0000c180 -#define mmMMHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmMMHUBBUB_SOFT_RESET_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_vgaif_dispdec -#define mmMCIF_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080 -#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream0_dispdec -#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream1_dispdec -#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream2_dispdec -#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream3_dispdec -#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream4_dispdec -#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream5_dispdec -#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream6_dispdec -#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream7_dispdec -#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_az_misc_dispdec -#define mmAZ_CLOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint0_dispdec -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint1_dispdec -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint2_dispdec -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint3_dispdec -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint4_dispdec -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint5_dispdec -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint6_dispdec -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0endpoint7_dispdec -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0controller_dispdec -#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000 -#define mmAZALIA_AUDIO_DTO_DEFAULT 0x00300018 -#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001 -#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000 -#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000 -#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000 -#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 -#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060 -#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008 -#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080 -#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0root_dispdec -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700 -#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream8_dispdec -#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream9_dispdec -#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream10_dispdec -#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream11_dispdec -#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream12_dispdec -#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream13_dispdec -#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream14_dispdec -#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0stream15_dispdec -#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec -#define mmDCHUBBUB_SDPIF_CFG0_DEFAULT 0x00cd3001 -#define mmDCHUBBUB_SDPIF_CFG1_DEFAULT 0x0000005c -#define mmDCHUBBUB_FORCE_IO_STATUS_0_DEFAULT 0x00000002 -#define mmDCHUBBUB_FORCE_IO_STATUS_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_FB_BASE_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_FB_TOP_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_FB_OFFSET_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_AGP_BOT_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_AGP_TOP_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_AGP_BASE_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_BASE_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_TOP_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_DEF_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_APER_DEF_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec -#define mmDCHUBBUB_RET_PATH_DCC_CFG_DEFAULT 0x00000001 -#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC_CTRL_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC0_VAL_R_G_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC0_VAL_B_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC1_VAL_R_G_DEFAULT 0x00000000 -#define mmDCHUBBUB_CRC1_VAL_B_A_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_hubbub_dispdec -#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_DEFAULT 0x01000100 -#define mmDCHUBBUB_ARB_SAT_LEVEL_DEFAULT 0xffffffff -#define mmDCHUBBUB_ARB_QOS_FORCE_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_DEFAULT 0x00000000 -#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_DEFAULT 0x00000010 -#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_DEFAULT 0x00000000 -#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_DEFAULT 0x00000000 -#define mmSURFACE_CHECK0_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK0_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK1_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK1_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK2_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK2_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK3_ADDRESS_LSB_DEFAULT 0x00000000 -#define mmSURFACE_CHECK3_ADDRESS_MSB_DEFAULT 0x00000000 -#define mmVTG0_CONTROL_DEFAULT 0x00000000 -#define mmVTG1_CONTROL_DEFAULT 0x00000000 -#define mmVTG2_CONTROL_DEFAULT 0x00000000 -#define mmVTG3_CONTROL_DEFAULT 0x00000000 -#define mmVTG4_CONTROL_DEFAULT 0x00000000 -#define mmVTG5_CONTROL_DEFAULT 0x00000000 -#define mmDCHUBBUB_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCHUBBUB_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmDCFCLK_CNTL_DEFAULT 0x80000200 -#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_DEFAULT 0x00000000 -#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_DEFAULT 0x00000000 -#define mmDCHUBBUB_VLINE_SNAPSHOT_DEFAULT 0x00000000 -#define mmDCHUBBUB_SPARE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec -#define mmHUBP0_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP0_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP0_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP0_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP0_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec -#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ0_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ0_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ0_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ0_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ0_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ0_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ0_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ0_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ0_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ0_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ0_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec -#define mmHUBPRET0_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec -#define mmCURSOR0_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec -#define mmHUBP1_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP1_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP1_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP1_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP1_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec -#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ1_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ1_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ1_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ1_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ1_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ1_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ1_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ1_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ1_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ1_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ1_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec -#define mmHUBPRET1_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec -#define mmCURSOR1_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec -#define mmHUBP2_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP2_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP2_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP2_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP2_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec -#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ2_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ2_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ2_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ2_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ2_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ2_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ2_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ2_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ2_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ2_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ2_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec -#define mmHUBPRET2_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec -#define mmCURSOR2_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec -#define mmHUBP3_DCSURF_SURFACE_CONFIG_DEFAULT 0x00000008 -#define mmHUBP3_DCSURF_ADDR_CONFIG_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_TILING_CONFIG_DEFAULT 0x00000080 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_CNTL_DEFAULT 0x00001001 -#define mmHUBP3_HUBP_CLK_CNTL_DEFAULT 0x00000000 -#define mmHUBP3_DCHUBP_VMPG_CONFIG_DEFAULT 0x00000000 -#define mmHUBP3_HUBPREQ_DEBUG_DB_DEFAULT 0x00000000 -#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_DEFAULT 0x00000000 -#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec -#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_DEFAULT 0x00003040 -#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_DEFAULT 0x04000000 -#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_EXPANSION_MODE_DEFAULT 0x00000055 -#define mmHUBPREQ3_DCN_TTU_QOS_WM_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_DEFAULT 0x00012010 -#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000000 -#define mmHUBPREQ3_BLANK_OFFSET_0_DEFAULT 0x00000000 -#define mmHUBPREQ3_BLANK_OFFSET_1_DEFAULT 0x00000000 -#define mmHUBPREQ3_DST_DIMENSIONS_DEFAULT 0x00000000 -#define mmHUBPREQ3_DST_AFTER_SCALER_DEFAULT 0x00000000 -#define mmHUBPREQ3_PREFETCH_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ3_PREFETCH_SETTINS_C_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ3_VBLANK_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_0_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_1_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_2_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_3_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_4_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_5_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_6_DEFAULT 0x00000000 -#define mmHUBPREQ3_NOM_PARAMETERS_7_DEFAULT 0x00000000 -#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_DEFAULT 0x00000000 -#define mmHUBPREQ3_PER_LINE_DELIVERY_DEFAULT 0x00000000 -#define mmHUBPREQ3_CURSOR_SETTINS_DEFAULT 0x00000000 -#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_DEFAULT 0x00000000 -#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec -#define mmHUBPRET3_HUBPRET_CONTROL_DEFAULT 0x00e40000 -#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE0_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE1_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_INTERRUPT_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_DEFAULT 0x00000000 -#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_DEFAULT 0x00000421 - - -// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec -#define mmCURSOR3_CURSOR_CONTROL_DEFAULT 0x01000000 -#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_SIZE_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_POSITION_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_HOT_SPOT_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_DST_OFFSET_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec -#define mmDPP_TOP0_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP0_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP0_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP0_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP0_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP0_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG0_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG0_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG0_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR0_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR0_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR0_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec -#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL0_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL0_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL0_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL0_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL0_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL0_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL0_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL0_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL0_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL0_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL0_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL0_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL0_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL0_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec -#define mmCM0_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM0_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM0_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM0_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM0_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM0_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM0_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM0_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM0_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM0_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM0_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM0_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM0_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM0_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM0_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM0_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM0_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM0_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec -#define mmDPP_TOP1_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP1_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP1_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP1_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP1_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP1_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG1_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG1_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG1_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR1_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR1_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR1_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec -#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL1_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL1_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL1_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL1_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL1_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL1_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL1_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL1_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL1_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL1_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL1_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL1_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL1_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL1_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec -#define mmCM1_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM1_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM1_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM1_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM1_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM1_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM1_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM1_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM1_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM1_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM1_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM1_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM1_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM1_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM1_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM1_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM1_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM1_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec -#define mmDPP_TOP2_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP2_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP2_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP2_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP2_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP2_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG2_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG2_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG2_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR2_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR2_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR2_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec -#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL2_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL2_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL2_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL2_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL2_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL2_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL2_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL2_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL2_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL2_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL2_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL2_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL2_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL2_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec -#define mmCM2_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM2_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM2_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM2_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM2_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM2_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM2_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM2_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM2_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM2_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM2_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM2_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM2_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM2_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM2_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM2_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM2_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM2_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON14_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON14_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON14_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec -#define mmDPP_TOP3_DPP_CONTROL_DEFAULT 0x70000000 -#define mmDPP_TOP3_DPP_SOFT_RESET_DEFAULT 0x00000000 -#define mmDPP_TOP3_DPP_CRC_VAL_R_G_DEFAULT 0x00000000 -#define mmDPP_TOP3_DPP_CRC_VAL_B_A_DEFAULT 0x00000000 -#define mmDPP_TOP3_DPP_CRC_CTRL_DEFAULT 0x00000000 -#define mmDPP_TOP3_HOST_READ_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec -#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x00000008 -#define mmCNVC_CFG3_FORMAT_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_DEFAULT 0x00003c00 -#define mmCNVC_CFG3_DENORM_CONTROL_DEFAULT 0x00002000 -#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_RED_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_GREEN_DEFAULT 0x00000000 -#define mmCNVC_CFG3_COLOR_KEYER_BLUE_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec -#define mmCNVC_CUR3_CURSOR0_CONTROL_DEFAULT 0x0003ff00 -#define mmCNVC_CUR3_CURSOR0_COLOR0_DEFAULT 0x00000000 -#define mmCNVC_CUR3_CURSOR0_COLOR1_DEFAULT 0x00000000 -#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_DEFAULT 0x00003c00 - - -// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec -#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_DEFAULT 0x00000000 -#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmDSCL3_SCL_MODE_DEFAULT 0x00000000 -#define mmDSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_CONTROL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_2TAP_CONTROL_DEFAULT 0x01000100 -#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmDSCL3_SCL_BLACK_OFFSET_DEFAULT 0x80000000 -#define mmDSCL3_DSCL_UPDATE_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_AUTOCAL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmDSCL3_OTG_H_BLANK_DEFAULT 0x00000000 -#define mmDSCL3_OTG_V_BLANK_DEFAULT 0x00000000 -#define mmDSCL3_RECOUT_START_DEFAULT 0x00000000 -#define mmDSCL3_RECOUT_SIZE_DEFAULT 0x00000000 -#define mmDSCL3_MPC_SIZE_DEFAULT 0x00000000 -#define mmDSCL3_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmDSCL3_LB_MEMORY_CTRL_DEFAULT 0x00003f00 -#define mmDSCL3_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDSCL3_DSCL_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDSCL3_OBUF_CONTROL_DEFAULT 0xe0000000 -#define mmDSCL3_OBUF_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec -#define mmCM3_CM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_COMA_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_COMA_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_COMA_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_COMB_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_COMB_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_COMB_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_COMB_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_COMB_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_COMB_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_IGAM_CONTROL_DEFAULT 0x08000002 -#define mmCM3_CM_IGAM_LUT_RW_CONTROL_DEFAULT 0x00011070 -#define mmCM3_CM_IGAM_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_DEFAULT 0xffff0000 -#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_DEFAULT 0xffff0000 -#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_DEFAULT 0xffff0000 -#define mmCM3_CM_ICSC_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_ICSC_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_ICSC_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_ICSC_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_OCSC_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C11_C12_DEFAULT 0x00002000 -#define mmCM3_CM_OCSC_C13_C14_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C21_C22_DEFAULT 0x20000000 -#define mmCM3_CM_OCSC_C23_C24_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C31_C32_DEFAULT 0x00000000 -#define mmCM3_CM_OCSC_C33_C34_DEFAULT 0x00002000 -#define mmCM3_CM_BNS_VALUES_R_DEFAULT 0x20000000 -#define mmCM3_CM_BNS_VALUES_G_DEFAULT 0x20000000 -#define mmCM3_CM_BNS_VALUES_B_DEFAULT 0x20000000 -#define mmCM3_CM_DGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_DGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_LUT_INDEX_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_LUT_DATA_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_16_17_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_18_19_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_20_21_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_22_23_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_24_25_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_26_27_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_28_29_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_30_31_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMA_REGION_32_33_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_0_1_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_2_3_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_4_5_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_6_7_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_8_9_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_10_11_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_12_13_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_14_15_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_16_17_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_18_19_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_20_21_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_22_23_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_24_25_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_26_27_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_28_29_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_30_31_DEFAULT 0x00000000 -#define mmCM3_CM_RGAM_RAMB_REGION_32_33_DEFAULT 0x00000000 -#define mmCM3_CM_HDR_MULT_COEF_DEFAULT 0x0001f000 -#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_DEFAULT 0xfbff7bff -#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_DEFAULT 0xfbff7bff -#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_DEFAULT 0xfbff7bff -#define mmCM3_CM_DENORM_CONTROL_DEFAULT 0x00000000 -#define mmCM3_CM_CMOUT_CONTROL_DEFAULT 0x0000000a -#define mmCM3_CM_CMOUT_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmCM3_CM_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmCM3_CM_MEM_PWR_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON15_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON15_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON15_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc0_dispdec -#define mmMPCC0_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC0_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC0_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC0_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC0_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc1_dispdec -#define mmMPCC1_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC1_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC1_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC1_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC1_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc2_dispdec -#define mmMPCC2_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC2_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC2_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC2_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC2_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpcc3_dispdec -#define mmMPCC3_MPCC_TOP_SEL_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BOT_SEL_DEFAULT 0x0000000f -#define mmMPCC3_MPCC_OPP_ID_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_CONTROL_DEFAULT 0xffff0061 -#define mmMPCC3_MPCC_SM_CONTROL_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_DEFAULT 0x0000000f -#define mmMPCC3_MPCC_TOP_OFFSET_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BOT_OFFSET_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_OFFSET_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BG_R_CR_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BG_G_Y_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_BG_B_CB_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_STALL_STATUS_DEFAULT 0x00000000 -#define mmMPCC3_MPCC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpc_cfg_dispdec -#define mmMPC_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmMPC_SOFT_RESET_DEFAULT 0x00000000 -#define mmMPC_CRC_CTRL_DEFAULT 0x00000000 -#define mmMPC_CRC_SEL_CONTROL_DEFAULT 0x00000000 -#define mmMPC_CRC_RESULT_AR_DEFAULT 0x00000000 -#define mmMPC_CRC_RESULT_GB_DEFAULT 0x00000000 -#define mmMPC_CRC_RESULT_C_DEFAULT 0x00000000 -#define mmMPC_PERFMON_EVENT_CTRL_DEFAULT 0x00000000 -#define mmMPC_BYPASS_BG_AR_DEFAULT 0x00000000 -#define mmMPC_BYPASS_BG_GB_DEFAULT 0x00000000 -#define mmMPC_OUT0_MUX_DEFAULT 0x0000000f -#define mmMPC_OUT1_MUX_DEFAULT 0x0000000f -#define mmMPC_OUT2_MUX_DEFAULT 0x0000000f -#define mmMPC_OUT3_MUX_DEFAULT 0x0000000f -#define mmMPC_STALL_GRACE_WINDOW_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET0_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET1_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET2_DEFAULT 0x00000000 -#define mmADR_CFG_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 -#define mmADR_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 -#define mmCUR0_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 -#define mmCUR1_VUPDATE_LOCK_SET3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON16_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON16_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON16_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_abm0_dispdec -#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM0_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_CNTL_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 -#define mmABM0_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 -#define mmABM0_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_abm1_dispdec -#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_USER_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_ABM_CNTL_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM1_BL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_CNTL_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 -#define mmABM1_DC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 -#define mmABM1_DC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt0_dispdec -#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf0_dispdec -#define mmOPPBUF0_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe0_dispdec -#define mmOPP_PIPE0_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt1_dispdec -#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf1_dispdec -#define mmOPPBUF1_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe1_dispdec -#define mmOPP_PIPE1_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt2_dispdec -#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf2_dispdec -#define mmOPPBUF2_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe2_dispdec -#define mmOPP_PIPE2_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt3_dispdec -#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf3_dispdec -#define mmOPPBUF3_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe3_dispdec -#define mmOPP_PIPE3_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt4_dispdec -#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf4_dispdec -#define mmOPPBUF4_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe4_dispdec -#define mmOPP_PIPE4_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_fmt5_dispdec -#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_oppbuf5_dispdec -#define mmOPPBUF5_OPPBUF_CONTROL_DEFAULT 0x00000000 -#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_DEFAULT 0x00000000 -#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe5_dispdec -#define mmOPP_PIPE5_OPP_PIPE_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_DEFAULT 0x0000ffff -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_DEFAULT 0x00000000 -#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_top_dispdec -#define mmOPP_TOP_CLK_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON17_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON17_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON17_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm0_dispdec -#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM0_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM0_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm1_dispdec -#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM1_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM1_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm2_dispdec -#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM2_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM2_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm3_dispdec -#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM3_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM3_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm4_dispdec -#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM4_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM4_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_odm5_dispdec -#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_DEFAULT 0x00000000 -#define mmODM5_OPTC_DATA_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmODM5_OPTC_INPUT_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg0_dispdec -#define mmOTG0_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG0_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG0_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG0_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG0_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG0_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG0_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG0_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG0_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG0_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG0_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG0_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG0_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG0_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG0_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG0_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG0_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG0_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG0_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG0_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG0_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG0_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG0_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg1_dispdec -#define mmOTG1_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG1_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG1_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG1_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG1_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG1_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG1_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG1_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG1_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG1_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG1_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG1_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG1_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG1_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG1_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG1_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG1_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG1_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG1_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG1_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG1_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG1_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG1_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg2_dispdec -#define mmOTG2_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG2_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG2_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG2_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG2_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG2_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG2_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG2_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG2_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG2_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG2_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG2_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG2_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG2_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG2_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG2_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG2_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG2_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG2_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG2_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG2_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG2_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG2_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg3_dispdec -#define mmOTG3_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG3_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG3_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG3_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG3_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG3_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG3_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG3_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG3_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG3_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG3_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG3_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG3_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG3_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG3_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG3_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG3_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG3_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG3_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG3_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG3_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG3_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG3_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg4_dispdec -#define mmOTG4_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG4_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG4_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG4_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG4_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG4_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG4_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG4_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG4_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG4_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG4_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG4_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG4_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG4_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG4_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG4_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG4_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG4_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG4_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG4_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG4_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG4_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG4_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_otg5_dispdec -#define mmOTG5_OTG_H_TOTAL_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_SYNC_A_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_H_TIMING_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_MID_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_SYNC_A_DEFAULT 0x00000000 -#define mmOTG5_OTG_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmOTG5_OTG_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmOTG5_OTG_CONTROL_DEFAULT 0x80000110 -#define mmOTG5_OTG_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_PIPE_ABORT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmOTG5_OTG_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmOTG5_OTG_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmOTG5_OTG_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_COUNT_RESET_DEFAULT 0x00000000 -#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_STEREO_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmOTG5_OTG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmOTG5_OTG_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmOTG5_OTG_MASTER_EN_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLACK_COLOR_DEFAULT 0x00000000 -#define mmOTG5_OTG_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC_CNTL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC2_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC2_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC3_DATA_RG_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC3_DATA_B_DEFAULT 0x00000000 -#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0xffffffff -#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmOTG5_OTG_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmOTG5_OTG_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_VSTARTUP_PARAM_DEFAULT 0x00000000 -#define mmOTG5_OTG_VUPDATE_PARAM_DEFAULT 0x00010000 -#define mmOTG5_OTG_VREADY_PARAM_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_MASTER_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmOTG5_OTG_GSL_CONTROL_DEFAULT 0x00020000 -#define mmOTG5_OTG_GSL_WINDOW_X_DEFAULT 0x00000000 -#define mmOTG5_OTG_GSL_WINDOW_Y_DEFAULT 0x00000000 -#define mmOTG5_OTG_VUPDATE_KEEPOUT_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL0_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL1_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL2_DEFAULT 0x00000000 -#define mmOTG5_OTG_GLOBAL_CONTROL3_DEFAULT 0x00000000 -#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmOTG5_OTG_DRR_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_REQUEST_CONTROL_DEFAULT 0x00000000 -#define mmOTG5_OTG_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_optc_misc_dispdec -#define mmDWB_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmGSL_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmOPTC_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmOPTC_MISC_SPARE_REGISTER_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON18_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON18_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON18_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dac_dispdec -#define mmDAC_ENABLE_DEFAULT 0x00000004 -#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmDAC_CRC_EN_DEFAULT 0x00000000 -#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f -#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f -#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000 -#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000 -#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b -#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519 -#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000 -#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000 -#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6 -#define mmDAC_POWERDOWN_DEFAULT 0x01010100 -#define mmDAC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000 -#define mmDAC_PWR_CNTL_DEFAULT 0x00000000 -#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000 -#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dout_i2c_dispdec -#define mmDC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001 -#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000 -#define mmDC_I2C_DATA_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4 -#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000 - - -// addressBlock: dce_dc_dio_generic_i2c_dispdec -#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000 -#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002 -#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000 -#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000 -#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000 -#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dio_misc_dispdec -#define mmDIO_SCRATCH0_DEFAULT 0x00000000 -#define mmDIO_SCRATCH1_DEFAULT 0x00000000 -#define mmDIO_SCRATCH2_DEFAULT 0x00000000 -#define mmDIO_SCRATCH3_DEFAULT 0x00000000 -#define mmDIO_SCRATCH4_DEFAULT 0x00000000 -#define mmDIO_SCRATCH5_DEFAULT 0x00000000 -#define mmDIO_SCRATCH6_DEFAULT 0x00000000 -#define mmDIO_SCRATCH7_DEFAULT 0x00000000 -#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000 -#define mmDIO_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDIO_MEM_PWR_CTRL_DEFAULT 0x6db6d800 -#define mmDIO_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDIO_CLK_CNTL_DEFAULT 0x00000000 -#define mmDIO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000 -#define mmDIO_STEREOSYNC_SEL_DEFAULT 0x00000000 -#define mmDIO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDIG_SOFT_RESET_DEFAULT 0x00000000 -#define mmDIO_MEM_PWR_STATUS1_DEFAULT 0x00000000 -#define mmDIO_CLK_CNTL2_DEFAULT 0x00000000 -#define mmDIO_CLK_CNTL3_DEFAULT 0x00000000 -#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000 -#define mmDIO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000 -#define mmDIO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000 -#define mmDIO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd0_dispdec -#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd1_dispdec -#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd2_dispdec -#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd3_dispdec -#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd4_dispdec -#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_hpd5_dispdec -#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec -#define mmDC_PERFMON19_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON19_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON19_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux0_dispdec -#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux1_dispdec -#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux2_dispdec -#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux3_dispdec -#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux4_dispdec -#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux5_dispdec -#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp_aux6_dispdec -#define mmDP_AUX6_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX6_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig0_dispdec -#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG0_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp0_dispdec -#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP0_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP0_DP_VID_N_DEFAULT 0x00002000 -#define mmDP0_DP_VID_M_DEFAULT 0x00000000 -#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP0_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP0_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP0_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP0_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig1_dispdec -#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG1_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp1_dispdec -#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP1_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP1_DP_VID_N_DEFAULT 0x00002000 -#define mmDP1_DP_VID_M_DEFAULT 0x00000000 -#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP1_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP1_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP1_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP1_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig2_dispdec -#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG2_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp2_dispdec -#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP2_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP2_DP_VID_N_DEFAULT 0x00002000 -#define mmDP2_DP_VID_M_DEFAULT 0x00000000 -#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP2_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP2_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP2_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP2_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig3_dispdec -#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG3_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp3_dispdec -#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP3_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP3_DP_VID_N_DEFAULT 0x00002000 -#define mmDP3_DP_VID_M_DEFAULT 0x00000000 -#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP3_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP3_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP3_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP3_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig4_dispdec -#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG4_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp4_dispdec -#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP4_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP4_DP_VID_N_DEFAULT 0x00002000 -#define mmDP4_DP_VID_M_DEFAULT 0x00000000 -#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP4_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP4_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP4_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP4_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig5_dispdec -#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG5_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp5_dispdec -#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP5_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP5_DP_VID_N_DEFAULT 0x00002000 -#define mmDP5_DP_VID_M_DEFAULT 0x00000000 -#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP5_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP5_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP5_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP5_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dig6_dispdec -#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_DEFAULT 0x00000000 -#define mmDIG6_HDMI_DB_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dio_dp6_dispdec -#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP6_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP6_DP_VID_N_DEFAULT 0x00002000 -#define mmDP6_DP_VID_M_DEFAULT 0x00000000 -#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM1_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM2_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM3_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_TIMING_PARAM4_DEFAULT 0x00000000 -#define mmDP6_DP_MSO_CNTL_DEFAULT 0xfffffff0 -#define mmDP6_DP_MSO_CNTL1_DEFAULT 0xffffffff -#define mmDP6_DP_DSC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL3_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL4_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL5_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL6_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL7_DEFAULT 0x00000000 -#define mmDP6_DP_DB_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_VBID_MISC_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_dcio_dispdec -#define mmDC_GENERICA_DEFAULT 0x00000000 -#define mmDC_GENERICB_DEFAULT 0x00000000 -#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000 -#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101 -#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01000100 -#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333 -#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000 -#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL2_DEFAULT 0x00000000 -#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001 -#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000 -#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmDIO_OTG_EXT_VSYNC_CNTL_DEFAULT 0x00000000 -#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4 -#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000 -#define mmAUXP_IMPCAL_DEFAULT 0x0a000000 -#define mmAUXN_IMPCAL_DEFAULT 0x04000000 -#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000 -#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000 -#define mmDCIO_USBC_FLIP_EN_SEL_DEFAULT 0x00543210 - - -// addressBlock: dce_dc_dcio_dcio_chip_dispdec -#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444 -#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040 -#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10 -#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440 -#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202 -#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040 -#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47fc470f -#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147 -#define mmPHY_AUX_CNTL_DEFAULT 0x00010001 -#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c -#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060 -#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000 -#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000 -#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202 -#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000 -#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000 -#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f -#define mmDC_GPIO_PULLUPEN_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_dcio_dac_dispdec -#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x1c010000 -#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_DEFAULT 0x00010520 - - -// addressBlock: dce_dc_dcio_dcio_zcal_dispdec -#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec -#define mmCOMP_EN_CTL_DEFAULT 0x00080000 -#define mmCOMP_EN_DFX_DEFAULT 0x00000000 -#define mmZCAL_FUSES_DEFAULT 0x00000000 - - -// addressBlock: vga_vgaseqind -#define ixSEQ00_DEFAULT 0x00000003 -#define ixSEQ01_DEFAULT 0x00000021 -#define ixSEQ02_DEFAULT 0x00000000 -#define ixSEQ03_DEFAULT 0x00000000 -#define ixSEQ04_DEFAULT 0x00000000 - - -// addressBlock: vga_vgacrtind -#define ixCRT00_DEFAULT 0x00000000 -#define ixCRT01_DEFAULT 0x00000000 -#define ixCRT02_DEFAULT 0x00000000 -#define ixCRT03_DEFAULT 0x00000000 -#define ixCRT04_DEFAULT 0x00000000 -#define ixCRT05_DEFAULT 0x00000000 -#define ixCRT06_DEFAULT 0x00000000 -#define ixCRT07_DEFAULT 0x00000000 -#define ixCRT08_DEFAULT 0x00000000 -#define ixCRT09_DEFAULT 0x00000000 -#define ixCRT0A_DEFAULT 0x00000000 -#define ixCRT0B_DEFAULT 0x00000000 -#define ixCRT0C_DEFAULT 0x00000000 -#define ixCRT0D_DEFAULT 0x00000000 -#define ixCRT0E_DEFAULT 0x00000000 -#define ixCRT0F_DEFAULT 0x00000000 -#define ixCRT10_DEFAULT 0x00000000 -#define ixCRT11_DEFAULT 0x00000000 -#define ixCRT12_DEFAULT 0x00000000 -#define ixCRT13_DEFAULT 0x00000000 -#define ixCRT14_DEFAULT 0x00000000 -#define ixCRT15_DEFAULT 0x00000000 -#define ixCRT16_DEFAULT 0x00000000 -#define ixCRT17_DEFAULT 0x00000000 -#define ixCRT18_DEFAULT 0x00000000 -#define ixCRT1E_DEFAULT 0x00000000 -#define ixCRT1F_DEFAULT 0x00000000 -#define ixCRT22_DEFAULT 0x00000000 - - -// addressBlock: vga_vgagrphind -#define ixGRA00_DEFAULT 0x00000000 -#define ixGRA01_DEFAULT 0x00000000 -#define ixGRA02_DEFAULT 0x00000000 -#define ixGRA03_DEFAULT 0x00000000 -#define ixGRA04_DEFAULT 0x00000000 -#define ixGRA05_DEFAULT 0x00000000 -#define ixGRA06_DEFAULT 0x00000000 -#define ixGRA07_DEFAULT 0x00000000 -#define ixGRA08_DEFAULT 0x00000000 - - -// addressBlock: vga_vgaattrind -#define ixATTR00_DEFAULT 0x00000000 -#define ixATTR01_DEFAULT 0x00000000 -#define ixATTR02_DEFAULT 0x00000000 -#define ixATTR03_DEFAULT 0x00000000 -#define ixATTR04_DEFAULT 0x00000000 -#define ixATTR05_DEFAULT 0x00000000 -#define ixATTR06_DEFAULT 0x00000000 -#define ixATTR07_DEFAULT 0x00000000 -#define ixATTR08_DEFAULT 0x00000000 -#define ixATTR09_DEFAULT 0x00000000 -#define ixATTR0A_DEFAULT 0x00000000 -#define ixATTR0B_DEFAULT 0x00000000 -#define ixATTR0C_DEFAULT 0x00000000 -#define ixATTR0D_DEFAULT 0x00000000 -#define ixATTR0E_DEFAULT 0x00000000 -#define ixATTR0F_DEFAULT 0x00000000 -#define ixATTR10_DEFAULT 0x00000000 -#define ixATTR11_DEFAULT 0x00000000 -#define ixATTR12_DEFAULT 0x00000000 -#define ixATTR13_DEFAULT 0x00000000 -#define ixATTR14_DEFAULT 0x00000000 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -// addressBlock: azendpoint_f2codecind -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000 - - -// addressBlock: azendpoint_descriptorind -#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000 - - -// addressBlock: azendpoint_sinkinfoind -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azinputcrc0resultind -#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azinputcrc1resultind -#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azcrc0resultind -#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azf0controller_azcrc1resultind -#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azinputendpoint_f2codecind -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 - - -// addressBlock: azroot_f2codecind -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000 - - -// addressBlock: azf0stream0_streamind -#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream1_streamind -#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream2_streamind -#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream3_streamind -#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream4_streamind -#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream5_streamind -#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream6_streamind -#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream7_streamind -#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream8_streamind -#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream9_streamind -#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream10_streamind -#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream11_streamind -#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream12_streamind -#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream13_streamind -#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream14_streamind -#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream15_streamind -#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint0_endpointind -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint1_endpointind -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint2_endpointind -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint3_endpointind -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint4_endpointind -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint5_endpointind -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint6_endpointind -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint7_endpointind -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint0_inputendpointind -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint1_inputendpointind -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint2_inputendpointind -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint3_inputendpointind -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint4_inputendpointind -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint5_inputendpointind -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint6_inputendpointind -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint7_inputendpointind -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h deleted file mode 100644 index 582f1a66e354..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_default.h +++ /dev/null @@ -1,4005 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _gc_9_1_DEFAULT_HEADER -#define _gc_9_1_DEFAULT_HEADER - - -// addressBlock: gc_grbmdec -#define mmGRBM_CNTL_DEFAULT 0x00000018 -#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020 -#define mmGRBM_STATUS2_DEFAULT 0x00000000 -#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000 -#define mmGRBM_STATUS_DEFAULT 0x00000000 -#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000 -#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000 -#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000 -#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100 -#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008 -#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030 -#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000 -#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000 -#define mmGRBM_READ_ERROR_DEFAULT 0x00000000 -#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000 -#define mmGRBM_INT_CNTL_DEFAULT 0x00000000 -#define mmGRBM_TRAP_OP_DEFAULT 0x00000000 -#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000 -#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff -#define mmGRBM_TRAP_WD_DEFAULT 0x00000000 -#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff -#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000 -#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000 -#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000 -#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000 -#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000 -#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000 -#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000 -#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000 -#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891 -#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea -#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000 -#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000 -#define mmGRBM_NOWHERE_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000 -#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000 - - -// addressBlock: gc_cpdec -#define mmCP_CPC_STATUS_DEFAULT 0x00000000 -#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000 -#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000 -#define mmCP_CPF_STATUS_DEFAULT 0x00000000 -#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000 -#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000 -#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008 -#define mmCP_MEC_CNTL_DEFAULT 0x50000000 -#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000 -#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004 -#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002 -#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000 -#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000 -#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000 -#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000 -#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000 -#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000 -#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000 -#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000 -#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000 -#define mmCP_STALLED_STAT3_DEFAULT 0x00000000 -#define mmCP_STALLED_STAT1_DEFAULT 0x00000000 -#define mmCP_STALLED_STAT2_DEFAULT 0x00000000 -#define mmCP_BUSY_STAT_DEFAULT 0x00000000 -#define mmCP_STAT_DEFAULT 0x00000000 -#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808 -#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000 -#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000 -#define mmCP_CSF_STAT_DEFAULT 0x00000000 -#define mmCP_ME_CNTL_DEFAULT 0x15000000 -#define mmCP_CNTX_STAT_DEFAULT 0x00000000 -#define mmCP_ME_PREEMPTION_DEFAULT 0x00000000 -#define mmCP_ROQ_THRESHOLDS_DEFAULT 0x00003010 -#define mmCP_MEQ_STQ_THRESHOLD_DEFAULT 0x00000010 -#define mmCP_RB2_RPTR_DEFAULT 0x00000000 -#define mmCP_RB1_RPTR_DEFAULT 0x00000000 -#define mmCP_RB0_RPTR_DEFAULT 0x00000000 -#define mmCP_RB_RPTR_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_DELAY_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_POLL_CNTL_DEFAULT 0x00400100 -#define mmCP_ROQ1_THRESHOLDS_DEFAULT 0x30101010 -#define mmCP_ROQ2_THRESHOLDS_DEFAULT 0x40403030 -#define mmCP_STQ_THRESHOLDS_DEFAULT 0x00804000 -#define mmCP_QUEUE_THRESHOLDS_DEFAULT 0x00002b16 -#define mmCP_MEQ_THRESHOLDS_DEFAULT 0x00008040 -#define mmCP_ROQ_AVAIL_DEFAULT 0x00000000 -#define mmCP_STQ_AVAIL_DEFAULT 0x00000000 -#define mmCP_ROQ2_AVAIL_DEFAULT 0x00000000 -#define mmCP_MEQ_AVAIL_DEFAULT 0x00000000 -#define mmCP_CMD_INDEX_DEFAULT 0x00000000 -#define mmCP_CMD_DATA_DEFAULT 0x00000000 -#define mmCP_ROQ_RB_STAT_DEFAULT 0x00000000 -#define mmCP_ROQ_IB1_STAT_DEFAULT 0x00000000 -#define mmCP_ROQ_IB2_STAT_DEFAULT 0x00000000 -#define mmCP_STQ_STAT_DEFAULT 0x00000000 -#define mmCP_STQ_WR_STAT_DEFAULT 0x00000000 -#define mmCP_MEQ_STAT_DEFAULT 0x00000000 -#define mmCP_CEQ1_AVAIL_DEFAULT 0x00000000 -#define mmCP_CEQ2_AVAIL_DEFAULT 0x00000000 -#define mmCP_CE_ROQ_RB_STAT_DEFAULT 0x00000000 -#define mmCP_CE_ROQ_IB1_STAT_DEFAULT 0x00000000 -#define mmCP_CE_ROQ_IB2_STAT_DEFAULT 0x00000000 - - -// addressBlock: gc_padec -#define mmVGT_VTX_VECT_EJECT_REG_DEFAULT 0x0000007d -#define mmVGT_DMA_DATA_FIFO_DEPTH_DEFAULT 0x00040180 -#define mmVGT_DMA_REQ_FIFO_DEPTH_DEFAULT 0x00000020 -#define mmVGT_DRAW_INIT_FIFO_DEPTH_DEFAULT 0x00000020 -#define mmVGT_LAST_COPY_STATE_DEFAULT 0x00000000 -#define mmVGT_CACHE_INVALIDATION_DEFAULT 0x09000000 -#define mmVGT_STRMOUT_DELAY_DEFAULT 0x00092410 -#define mmVGT_FIFO_DEPTHS_DEFAULT 0x08000040 -#define mmVGT_GS_VERTEX_REUSE_DEFAULT 0x00000010 -#define mmVGT_MC_LAT_CNTL_DEFAULT 0x000000fe -#define mmIA_CNTL_STATUS_DEFAULT 0x00000000 -#define mmVGT_CNTL_STATUS_DEFAULT 0x00000000 -#define mmWD_CNTL_STATUS_DEFAULT 0x00000000 -#define mmCC_GC_PRIM_CONFIG_DEFAULT 0x0e020000 -#define mmGC_USER_PRIM_CONFIG_DEFAULT 0x00000000 -#define mmWD_QOS_DEFAULT 0x00000000 -#define mmWD_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmWD_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmIA_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmIA_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmVGT_SYS_CONFIG_DEFAULT 0x00000011 -#define mmVGT_VS_MAX_WAVE_ID_DEFAULT 0x0000007f -#define mmVGT_GS_MAX_WAVE_ID_DEFAULT 0x000000ff -#define mmGFX_PIPE_CONTROL_DEFAULT 0x00000000 -#define mmCC_GC_SHADER_ARRAY_CONFIG_DEFAULT 0xf8000000 -#define mmGC_USER_SHADER_ARRAY_CONFIG_DEFAULT 0x00000000 -#define mmVGT_DMA_PRIMITIVE_TYPE_DEFAULT 0x00000000 -#define mmVGT_DMA_CONTROL_DEFAULT 0x000000ff -#define mmVGT_DMA_LS_HS_CONFIG_DEFAULT 0x00000000 -#define mmWD_BUF_RESOURCE_1_DEFAULT 0x00000000 -#define mmWD_BUF_RESOURCE_2_DEFAULT 0x00000000 -#define mmPA_CL_CNTL_STATUS_DEFAULT 0x00000000 -#define mmPA_CL_ENHANCE_DEFAULT 0x00000007 -#define mmPA_SU_CNTL_STATUS_DEFAULT 0x00000000 -#define mmPA_SC_FIFO_DEPTH_CNTL_DEFAULT 0x00000018 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_HV_LOCK_DEFAULT 0x00000000 -#define mmPA_SC_FORCE_EOV_MAX_CNTS_DEFAULT 0x00ffffff -#define mmPA_SC_BINNER_EVENT_CNTL_0_DEFAULT 0x842a4402 -#define mmPA_SC_BINNER_EVENT_CNTL_1_DEFAULT 0x8a000008 -#define mmPA_SC_BINNER_EVENT_CNTL_2_DEFAULT 0x9118aaa8 -#define mmPA_SC_BINNER_EVENT_CNTL_3_DEFAULT 0x82400025 -#define mmPA_SC_BINNER_TIMEOUT_COUNTER_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_0_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_1_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_2_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_PERF_CNTL_3_DEFAULT 0x00000000 -#define mmPA_SC_FIFO_SIZE_DEFAULT 0x00000000 -#define mmPA_SC_IF_FIFO_SIZE_DEFAULT 0x00000000 -#define mmPA_SC_PKR_WAVE_TABLE_CNTL_DEFAULT 0x00000000 -#define mmPA_UTCL1_CNTL1_DEFAULT 0x00000600 -#define mmPA_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmPA_SIDEBAND_REQUEST_DELAYS_DEFAULT 0x08000020 -#define mmPA_SC_ENHANCE_DEFAULT 0x00000001 -#define mmPA_SC_ENHANCE_1_DEFAULT 0x00040000 -#define mmPA_SC_DSM_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_DEFAULT 0x00000000 - - -// addressBlock: gc_sqdec -#define mmSQ_CONFIG_DEFAULT 0x01180000 -#define mmSQC_CONFIG_DEFAULT 0x010a2000 -#define mmLDS_CONFIG_DEFAULT 0x00000000 -#define mmSQ_RANDOM_WAVE_PRI_DEFAULT 0x0000007f -#define mmSQ_REG_CREDITS_DEFAULT 0x00000820 -#define mmSQ_FIFO_SIZES_DEFAULT 0x00000f01 -#define mmSQ_DSM_CNTL_DEFAULT 0x00000000 -#define mmSQ_DSM_CNTL2_DEFAULT 0x00000000 -#define mmSQ_RUNTIME_CONFIG_DEFAULT 0x00000000 -#define mmSH_MEM_BASES_DEFAULT 0x00000000 -#define mmSH_MEM_CONFIG_DEFAULT 0x00000000 -#define mmCC_GC_SHADER_RATE_CONFIG_DEFAULT 0x00000000 -#define mmGC_USER_SHADER_RATE_CONFIG_DEFAULT 0x00000000 -#define mmSQ_INTERRUPT_AUTO_MASK_DEFAULT 0x00ffffff -#define mmSQ_INTERRUPT_MSG_CTRL_DEFAULT 0x00000000 -#define mmSQ_UTCL1_CNTL1_DEFAULT 0x00000580 -#define mmSQ_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmSQ_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmSQ_SHADER_TBA_LO_DEFAULT 0x00000000 -#define mmSQ_SHADER_TBA_HI_DEFAULT 0x00000000 -#define mmSQ_SHADER_TMA_LO_DEFAULT 0x00000000 -#define mmSQ_SHADER_TMA_HI_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTLA_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTLB_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL2_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmSQC_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmSQC_EDC_FUE_CNTL_DEFAULT 0x00000000 -#define mmSQC_EDC_CNT2_DEFAULT 0x00000000 -#define mmSQC_EDC_CNT3_DEFAULT 0x00000000 -#define mmSQ_REG_TIMESTAMP_DEFAULT 0x00000000 -#define mmSQ_CMD_TIMESTAMP_DEFAULT 0x00000000 -#define mmSQ_IND_INDEX_DEFAULT 0x00000000 -#define mmSQ_IND_DATA_DEFAULT 0x00000000 -#define mmSQ_CMD_DEFAULT 0x00000000 -#define mmSQ_TIME_HI_DEFAULT 0x00000000 -#define mmSQ_TIME_LO_DEFAULT 0x00000000 -#define mmSQ_DS_0_DEFAULT 0x00000000 -#define mmSQ_DS_1_DEFAULT 0x00000000 -#define mmSQ_EXP_0_DEFAULT 0x00000000 -#define mmSQ_EXP_1_DEFAULT 0x00000000 -#define mmSQ_FLAT_0_DEFAULT 0x00000000 -#define mmSQ_FLAT_1_DEFAULT 0x00000000 -#define mmSQ_GLBL_0_DEFAULT 0x00000000 -#define mmSQ_GLBL_1_DEFAULT 0x00000000 -#define mmSQ_INST_DEFAULT 0x00000000 -#define mmSQ_MIMG_0_DEFAULT 0x00000000 -#define mmSQ_MIMG_1_DEFAULT 0x00000000 -#define mmSQ_MTBUF_0_DEFAULT 0x00000000 -#define mmSQ_MTBUF_1_DEFAULT 0x00000000 -#define mmSQ_MUBUF_0_DEFAULT 0x00000000 -#define mmSQ_MUBUF_1_DEFAULT 0x00000000 -#define mmSQ_SCRATCH_0_DEFAULT 0x00000000 -#define mmSQ_SCRATCH_1_DEFAULT 0x00000000 -#define mmSQ_SMEM_0_DEFAULT 0x00000000 -#define mmSQ_SMEM_1_DEFAULT 0x00000000 -#define mmSQ_SOP1_DEFAULT 0x00000000 -#define mmSQ_SOP2_DEFAULT 0x00000000 -#define mmSQ_SOPC_DEFAULT 0x00000000 -#define mmSQ_SOPK_DEFAULT 0x00000000 -#define mmSQ_SOPP_DEFAULT 0x00000000 -#define mmSQ_VINTRP_DEFAULT 0x00000000 -#define mmSQ_VOP1_DEFAULT 0x00000000 -#define mmSQ_VOP2_DEFAULT 0x00000000 -#define mmSQ_VOP3P_0_DEFAULT 0x00000000 -#define mmSQ_VOP3P_1_DEFAULT 0x00000000 -#define mmSQ_VOP3_0_DEFAULT 0x00000000 -#define mmSQ_VOP3_0_SDST_ENC_DEFAULT 0x00000000 -#define mmSQ_VOP3_1_DEFAULT 0x00000000 -#define mmSQ_VOPC_DEFAULT 0x00000000 -#define mmSQ_VOP_DPP_DEFAULT 0x00000000 -#define mmSQ_VOP_SDWA_DEFAULT 0x00000000 -#define mmSQ_VOP_SDWA_SDST_ENC_DEFAULT 0x00000000 -#define mmSQ_LB_CTR_CTRL_DEFAULT 0x00000000 -#define mmSQ_LB_DATA0_DEFAULT 0x00000000 -#define mmSQ_LB_DATA1_DEFAULT 0x00000000 -#define mmSQ_LB_DATA2_DEFAULT 0x00000000 -#define mmSQ_LB_DATA3_DEFAULT 0x00000000 -#define mmSQ_LB_CTR_SEL_DEFAULT 0x00000000 -#define mmSQ_LB_CTR0_CU_DEFAULT 0xffffffff -#define mmSQ_LB_CTR1_CU_DEFAULT 0xffffffff -#define mmSQ_LB_CTR2_CU_DEFAULT 0xffffffff -#define mmSQ_LB_CTR3_CU_DEFAULT 0xffffffff -#define mmSQC_EDC_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_SEC_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_DED_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_INFO_DEFAULT 0x00000000 -#define mmSQ_EDC_CNT_DEFAULT 0x00000000 -#define mmSQ_EDC_FUE_CNTL_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_CMN_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_EVENT_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_ISSUE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_MISC_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_WAVE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_WAVE_START_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_DEFAULT 0x00000000 -#define mmSQ_WREXEC_EXEC_HI_DEFAULT 0x00000000 -#define mmSQ_WREXEC_EXEC_LO_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD0_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD1_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD2_DEFAULT 0x00000000 -#define mmSQ_BUF_RSRC_WORD3_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD0_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD1_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD2_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD3_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD4_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD5_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD6_DEFAULT 0x00000000 -#define mmSQ_IMG_RSRC_WORD7_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD0_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD1_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD2_DEFAULT 0x00000000 -#define mmSQ_IMG_SAMP_WORD3_DEFAULT 0x00000000 -#define mmSQ_FLAT_SCRATCH_WORD0_DEFAULT 0x00000000 -#define mmSQ_FLAT_SCRATCH_WORD1_DEFAULT 0x00000000 -#define mmSQ_M0_GPR_IDX_WORD_DEFAULT 0x00000000 -#define mmSQC_ICACHE_UTCL1_CNTL1_DEFAULT 0x00000480 -#define mmSQC_ICACHE_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmSQC_DCACHE_UTCL1_CNTL1_DEFAULT 0x00000500 -#define mmSQC_DCACHE_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmSQC_ICACHE_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmSQC_DCACHE_UTCL1_STATUS_DEFAULT 0x00000000 - - -// addressBlock: gc_shsdec -#define mmSX_DEBUG_1_DEFAULT 0x00000020 -#define mmSPI_PS_MAX_WAVE_ID_DEFAULT 0x020000ff -#define mmSPI_START_PHASE_DEFAULT 0x00000000 -#define mmSPI_GFX_CNTL_DEFAULT 0x00000000 -#define mmSPI_DSM_CNTL_DEFAULT 0x00000000 -#define mmSPI_DSM_CNTL2_DEFAULT 0x00000000 -#define mmSPI_EDC_CNT_DEFAULT 0x00000000 -#define mmSPI_CONFIG_PS_CU_EN_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_CNTL_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_LIMIT_0_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_1_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_2_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_3_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_4_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_5_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_6_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_7_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_8_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_LIMIT_9_DEFAULT 0x00000100 -#define mmSPI_WF_LIFETIME_STATUS_0_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_1_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_2_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_3_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_4_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_5_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_6_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_7_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_8_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_9_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_10_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_11_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_12_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_13_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_14_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_15_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_16_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_17_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_18_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_19_DEFAULT 0x00000000 -#define mmSPI_WF_LIFETIME_STATUS_20_DEFAULT 0x00000000 -#define mmSPI_LB_CTR_CTRL_DEFAULT 0x00000000 -#define mmSPI_LB_CU_MASK_DEFAULT 0x0000ffff -#define mmSPI_LB_DATA_REG_DEFAULT 0x00000000 -#define mmSPI_PG_ENABLE_STATIC_CU_MASK_DEFAULT 0x0000ffff -#define mmSPI_GDS_CREDITS_DEFAULT 0x00001080 -#define mmSPI_SX_EXPORT_BUFFER_SIZES_DEFAULT 0x08000800 -#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_DEFAULT 0x00200040 -#define mmSPI_CSQ_WF_ACTIVE_STATUS_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_0_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_1_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_2_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_3_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_4_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_5_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_6_DEFAULT 0x00000000 -#define mmSPI_CSQ_WF_ACTIVE_COUNT_7_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_WAVES_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_PERCU_WAVE_HSGS_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_PERCU_WAVE_VSPS_DEFAULT 0x00000000 -#define mmSPI_LB_DATA_PERCU_WAVE_CS_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 -#define mmSPI_P0_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSBA_LO_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSBA_HI_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSMA_LO_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_PSMA_HI_DEFAULT 0x00000000 -#define mmSPI_P1_TRAP_SCREEN_GPR_MIN_DEFAULT 0x00000000 - - -// addressBlock: gc_tpdec -#define mmTD_CNTL_DEFAULT 0x00000000 -#define mmTD_STATUS_DEFAULT 0x00000000 -#define mmTD_DSM_CNTL_DEFAULT 0x00000000 -#define mmTD_DSM_CNTL2_DEFAULT 0x00000000 -#define mmTD_SCRATCH_DEFAULT 0x00000000 -#define mmTA_CNTL_DEFAULT 0x8004d850 -#define mmTA_CNTL_AUX_DEFAULT 0x00000000 -#define mmTA_RESERVED_010C_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_DEFAULT 0x40000040 -#define mmTA_STATUS_DEFAULT 0x00000000 -#define mmTA_SCRATCH_DEFAULT 0x00000000 - - -// addressBlock: gc_gdsdec -#define mmGDS_CONFIG_DEFAULT 0x00000000 -#define mmGDS_CNTL_STATUS_DEFAULT 0x00000000 -#define mmGDS_ENHANCE2_DEFAULT 0x00000000 -#define mmGDS_PROTECTION_FAULT_DEFAULT 0x00000000 -#define mmGDS_VM_PROTECTION_FAULT_DEFAULT 0x00000000 -#define mmGDS_EDC_CNT_DEFAULT 0x00000000 -#define mmGDS_EDC_GRBM_CNT_DEFAULT 0x00000000 -#define mmGDS_EDC_OA_DED_DEFAULT 0x00000000 -#define mmGDS_DSM_CNTL_DEFAULT 0x00000000 -#define mmGDS_EDC_OA_PHY_CNT_DEFAULT 0x00000000 -#define mmGDS_EDC_OA_PIPE_CNT_DEFAULT 0x00000000 -#define mmGDS_DSM_CNTL2_DEFAULT 0x00000000 -#define mmGDS_WD_GDS_CSB_DEFAULT 0x00000000 - - -// addressBlock: gc_rbdec -#define mmDB_DEBUG_DEFAULT 0x00000000 -#define mmDB_DEBUG2_DEFAULT 0x00000000 -#define mmDB_DEBUG3_DEFAULT 0x00000000 -#define mmDB_DEBUG4_DEFAULT 0x00000000 -#define mmDB_CREDIT_LIMIT_DEFAULT 0x00000000 -#define mmDB_WATERMARKS_DEFAULT 0x01020204 -#define mmDB_SUBTILE_CONTROL_DEFAULT 0x00000000 -#define mmDB_FREE_CACHELINES_DEFAULT 0x00000000 -#define mmDB_FIFO_DEPTH1_DEFAULT 0x00000000 -#define mmDB_FIFO_DEPTH2_DEFAULT 0x00000000 -#define mmDB_EXCEPTION_CONTROL_DEFAULT 0x00000000 -#define mmDB_RING_CONTROL_DEFAULT 0x00000001 -#define mmDB_MEM_ARB_WATERMARKS_DEFAULT 0x04040404 -#define mmDB_RMI_CACHE_POLICY_DEFAULT 0x0f0f0f07 -#define mmDB_DFSM_CONFIG_DEFAULT 0x00007f00 -#define mmDB_DFSM_WATERMARK_DEFAULT 0x00640064 -#define mmDB_DFSM_TILES_IN_FLIGHT_DEFAULT 0x05dc03e8 -#define mmDB_DFSM_PRIMS_IN_FLIGHT_DEFAULT 0x00fa00c8 -#define mmDB_DFSM_WATCHDOG_DEFAULT 0x000f4240 -#define mmDB_DFSM_FLUSH_ENABLE_DEFAULT 0x000003ff -#define mmDB_DFSM_FLUSH_AUX_EVENT_DEFAULT 0x00000000 -#define mmCC_RB_REDUNDANCY_DEFAULT 0x00000000 -#define mmCC_RB_BACKEND_DISABLE_DEFAULT 0x00000000 -#define mmGB_ADDR_CONFIG_DEFAULT 0x26010011 -#define mmGB_BACKEND_MAP_DEFAULT 0x33221100 -#define mmGB_GPU_ID_DEFAULT 0x00000000 -#define mmCC_RB_DAISY_CHAIN_DEFAULT 0x76543210 -#define mmGB_ADDR_CONFIG_READ_DEFAULT 0x26010011 -#define mmGB_TILE_MODE0_DEFAULT 0x00000000 -#define mmGB_TILE_MODE1_DEFAULT 0x00000000 -#define mmGB_TILE_MODE2_DEFAULT 0x00000000 -#define mmGB_TILE_MODE3_DEFAULT 0x00000000 -#define mmGB_TILE_MODE4_DEFAULT 0x00000000 -#define mmGB_TILE_MODE5_DEFAULT 0x00000000 -#define mmGB_TILE_MODE6_DEFAULT 0x00000000 -#define mmGB_TILE_MODE7_DEFAULT 0x00000000 -#define mmGB_TILE_MODE8_DEFAULT 0x00000000 -#define mmGB_TILE_MODE9_DEFAULT 0x00000000 -#define mmGB_TILE_MODE10_DEFAULT 0x00000000 -#define mmGB_TILE_MODE11_DEFAULT 0x00000000 -#define mmGB_TILE_MODE12_DEFAULT 0x00000000 -#define mmGB_TILE_MODE13_DEFAULT 0x00000000 -#define mmGB_TILE_MODE14_DEFAULT 0x00000000 -#define mmGB_TILE_MODE15_DEFAULT 0x00000000 -#define mmGB_TILE_MODE16_DEFAULT 0x00000000 -#define mmGB_TILE_MODE17_DEFAULT 0x00000000 -#define mmGB_TILE_MODE18_DEFAULT 0x00000000 -#define mmGB_TILE_MODE19_DEFAULT 0x00000000 -#define mmGB_TILE_MODE20_DEFAULT 0x00000000 -#define mmGB_TILE_MODE21_DEFAULT 0x00000000 -#define mmGB_TILE_MODE22_DEFAULT 0x00000000 -#define mmGB_TILE_MODE23_DEFAULT 0x00000000 -#define mmGB_TILE_MODE24_DEFAULT 0x00000000 -#define mmGB_TILE_MODE25_DEFAULT 0x00000000 -#define mmGB_TILE_MODE26_DEFAULT 0x00000000 -#define mmGB_TILE_MODE27_DEFAULT 0x00000000 -#define mmGB_TILE_MODE28_DEFAULT 0x00000000 -#define mmGB_TILE_MODE29_DEFAULT 0x00000000 -#define mmGB_TILE_MODE30_DEFAULT 0x00000000 -#define mmGB_TILE_MODE31_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE0_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE1_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE2_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE3_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE4_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE5_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE6_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE7_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE8_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE9_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE10_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE11_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE12_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE13_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE14_DEFAULT 0x00000000 -#define mmGB_MACROTILE_MODE15_DEFAULT 0x00000000 -#define mmCB_HW_CONTROL_DEFAULT 0x00014107 -#define mmCB_HW_CONTROL_1_DEFAULT 0x10000000 -#define mmCB_HW_CONTROL_2_DEFAULT 0x00000000 -#define mmCB_HW_CONTROL_3_DEFAULT 0x00000000 -#define mmCB_HW_MEM_ARBITER_RD_DEFAULT 0x00029000 -#define mmCB_HW_MEM_ARBITER_WR_DEFAULT 0x00029000 -#define mmCB_DCC_CONFIG_DEFAULT 0x04000000 -#define mmGC_USER_RB_REDUNDANCY_DEFAULT 0x00000000 -#define mmGC_USER_RB_BACKEND_DISABLE_DEFAULT 0x00000000 - - -// addressBlock: gc_ea_gceadec2 -#define mmGCEA_EDC_CNT_DEFAULT 0x00000000 -#define mmGCEA_EDC_CNT2_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTLA_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTLB_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL2_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmGCEA_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmGCEA_TCC_XBR_CREDITS_DEFAULT 0x637f637f -#define mmGCEA_TCC_XBR_MAXBURST_DEFAULT 0x00003333 -#define mmGCEA_PROBE_CNTL_DEFAULT 0x00000000 -#define mmGCEA_PROBE_MAP_DEFAULT 0x0000aaaa -#define mmGCEA_ERR_STATUS_DEFAULT 0x00000000 -#define mmGCEA_MISC2_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_DATACREDITS0_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_DATACREDITS1_DEFAULT 0x00000000 -#define mmGCEA_SDP_BACKDOOR_MISCCREDITS_DEFAULT 0x00000000 -#define mmGCEA_SDP_ENABLE_DEFAULT 0x00000000 - - -// addressBlock: gc_rmi_rmidec -#define mmRMI_GENERAL_CNTL_DEFAULT 0x00000000 -#define mmRMI_GENERAL_CNTL1_DEFAULT 0x00001a03 -#define mmRMI_GENERAL_STATUS_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS0_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS1_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS2_DEFAULT 0x00000000 -#define mmRMI_SUBBLOCK_STATUS3_DEFAULT 0x00000000 -#define mmRMI_XBAR_CONFIG_DEFAULT 0x00000f00 -#define mmRMI_PROBE_POP_LOGIC_CNTL_DEFAULT 0x000300c0 -#define mmRMI_UTC_XNACK_N_MISC_CNTL_DEFAULT 0x00000564 -#define mmRMI_DEMUX_CNTL_DEFAULT 0x02000200 -#define mmRMI_UTCL1_CNTL1_DEFAULT 0x00020000 -#define mmRMI_UTCL1_CNTL2_DEFAULT 0x00010000 -#define mmRMI_UTC_UNIT_CONFIG_DEFAULT 0x00000000 -#define mmRMI_TCIW_FORMATTER0_CNTL_DEFAULT 0x4404001e -#define mmRMI_TCIW_FORMATTER1_CNTL_DEFAULT 0x4404001e -#define mmRMI_SCOREBOARD_CNTL_DEFAULT 0x001ffe00 -#define mmRMI_SCOREBOARD_STATUS0_DEFAULT 0x00000000 -#define mmRMI_SCOREBOARD_STATUS1_DEFAULT 0x00000000 -#define mmRMI_SCOREBOARD_STATUS2_DEFAULT 0x00000000 -#define mmRMI_XBAR_ARBITER_CONFIG_DEFAULT 0x08000800 -#define mmRMI_XBAR_ARBITER_CONFIG_1_DEFAULT 0xffffffff -#define mmRMI_CLOCK_CNTRL_DEFAULT 0x04208822 -#define mmRMI_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmRMI_SPARE_DEFAULT 0x00000001 -#define mmRMI_SPARE_1_DEFAULT 0x00000000 -#define mmRMI_SPARE_2_DEFAULT 0x00000000 - - -// addressBlock: gc_dbgu_gfx_dbgudec -#define mmport_a_addr_DEFAULT 0x00000000 -#define mmport_a_data_lo_DEFAULT 0x00000000 -#define mmport_a_data_hi_DEFAULT 0x00000000 -#define mmport_b_addr_DEFAULT 0x00000000 -#define mmport_b_data_lo_DEFAULT 0x00000000 -#define mmport_b_data_hi_DEFAULT 0x00000000 -#define mmport_c_addr_DEFAULT 0x00000000 -#define mmport_c_data_lo_DEFAULT 0x00000000 -#define mmport_c_data_hi_DEFAULT 0x00000000 -#define mmport_d_addr_DEFAULT 0x00000000 -#define mmport_d_data_lo_DEFAULT 0x00000000 -#define mmport_d_data_hi_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_atcl2dec -#define mmATC_L2_CNTL_DEFAULT 0x000001c9 -#define mmATC_L2_CNTL2_DEFAULT 0x00000100 -#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 -#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 -#define mmATC_L2_STATUS_DEFAULT 0x00000000 -#define mmATC_L2_STATUS2_DEFAULT 0x00000000 -#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 -#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: gc_utcl2_vml2pfdec -#define mmVM_L2_CNTL_DEFAULT 0x00080602 -#define mmVM_L2_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_CNTL3_DEFAULT 0x80100007 -#define mmVM_L2_STATUS_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc -#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 -#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 -#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 -#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: gc_utcl2_vml2vcdec -#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_vmsharedpfdec -#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 -#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmMC_VM_STEERING_DEFAULT 0x00000001 -#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 -#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_vmsharedvcdec -#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 - - -// addressBlock: gc_ea_gceadec -#define mmGCEA_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000924 -#define mmGCEA_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000324 -#define mmGCEA_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmGCEA_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmGCEA_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmGCEA_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmGCEA_DRAM_PAGE_BURST_DEFAULT 0x20082008 -#define mmGCEA_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmGCEA_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmGCEA_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmGCEA_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmGCEA_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmGCEA_IO_RD_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_RD_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_WR_CLI2GRP_MAP0_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_WR_CLI2GRP_MAP1_DEFAULT 0xeaaa9580 -#define mmGCEA_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmGCEA_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmGCEA_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmGCEA_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmGCEA_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmGCEA_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmGCEA_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmGCEA_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmGCEA_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmGCEA_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmGCEA_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmGCEA_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmGCEA_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmGCEA_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmGCEA_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmGCEA_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmGCEA_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmGCEA_SDP_CREDITS_DEFAULT 0x000100bf -#define mmGCEA_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmGCEA_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmGCEA_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmGCEA_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmGCEA_MISC_DEFAULT 0x0de03ff0 -#define mmGCEA_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmGCEA_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: gc_tcdec -#define mmTCP_INVALIDATE_DEFAULT 0x00000000 -#define mmTCP_STATUS_DEFAULT 0x00000000 -#define mmTCP_CNTL_DEFAULT 0x2f9c0000 -#define mmTCP_CHAN_STEER_LO_DEFAULT 0x76543210 -#define mmTCP_CHAN_STEER_HI_DEFAULT 0xfedcba98 -#define mmTCP_ADDR_CONFIG_DEFAULT 0x000000f3 -#define mmTCP_CREDIT_DEFAULT 0x804001c0 -#define mmTCP_BUFFER_ADDR_HASH_CNTL_DEFAULT 0x00000000 -#define mmTCP_EDC_CNT_DEFAULT 0x00000000 -#define mmTC_CFG_L1_LOAD_POLICY0_DEFAULT 0x00000000 -#define mmTC_CFG_L1_LOAD_POLICY1_DEFAULT 0x00000000 -#define mmTC_CFG_L1_STORE_POLICY_DEFAULT 0x00000000 -#define mmTC_CFG_L2_LOAD_POLICY0_DEFAULT 0x00000000 -#define mmTC_CFG_L2_LOAD_POLICY1_DEFAULT 0x00000000 -#define mmTC_CFG_L2_STORE_POLICY0_DEFAULT 0x00000000 -#define mmTC_CFG_L2_STORE_POLICY1_DEFAULT 0x00000000 -#define mmTC_CFG_L2_ATOMIC_POLICY_DEFAULT 0x00000000 -#define mmTC_CFG_L1_VOLATILE_DEFAULT 0x00000000 -#define mmTC_CFG_L2_VOLATILE_DEFAULT 0x00000000 -#define mmTCI_STATUS_DEFAULT 0x00000000 -#define mmTCI_CNTL_1_DEFAULT 0x40080022 -#define mmTCI_CNTL_2_DEFAULT 0x00000041 -#define mmTCC_CTRL_DEFAULT 0xf30fff7f -#define mmTCC_CTRL2_DEFAULT 0x0000000f -#define mmTCC_EDC_CNT_DEFAULT 0x00000000 -#define mmTCC_EDC_CNT2_DEFAULT 0x00000000 -#define mmTCC_REDUNDANCY_DEFAULT 0x00000000 -#define mmTCC_EXE_DISABLE_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTLA_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL2_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmTCC_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmTCC_WBINVL2_DEFAULT 0x00000010 -#define mmTCC_SOFT_RESET_DEFAULT 0x00000000 -#define mmTCA_CTRL_DEFAULT 0x00000088 -#define mmTCA_BURST_MASK_DEFAULT 0xffffffff -#define mmTCA_BURST_CTRL_DEFAULT 0x00000007 -#define mmTCA_DSM_CNTL_DEFAULT 0x00000000 -#define mmTCA_DSM_CNTL2_DEFAULT 0x00000000 -#define mmTCA_EDC_CNT_DEFAULT 0x00000000 - - -// addressBlock: gc_shdec -#define mmSPI_SHADER_PGM_RSRC3_PS_DEFAULT 0x0000ffff -#define mmSPI_SHADER_PGM_LO_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_PS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_PS_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC3_VS_DEFAULT 0x0000ffff -#define mmSPI_SHADER_LATE_ALLOC_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_LO_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_VS_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_GS_VS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC4_GS_DEFAULT 0x00000800 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_LO_ES_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_ES_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC3_GS_DEFAULT 0x0000fffe -#define mmSPI_SHADER_PGM_LO_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_GS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ES_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC4_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_LO_LS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_LS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC3_HS_DEFAULT 0xffff0000 -#define mmSPI_SHADER_PGM_LO_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_HI_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC1_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_PGM_RSRC2_HS_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_LS_31_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_0_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_1_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_2_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_3_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_4_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_5_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_6_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_7_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_8_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_9_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_10_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_11_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_12_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_13_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_14_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_15_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_16_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_17_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_18_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_19_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_20_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_21_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_22_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_23_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_24_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_25_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_26_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_27_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_28_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_29_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_30_DEFAULT 0x00000000 -#define mmSPI_SHADER_USER_DATA_COMMON_31_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_INITIATOR_DEFAULT 0x00000000 -#define mmCOMPUTE_DIM_X_DEFAULT 0x00000000 -#define mmCOMPUTE_DIM_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_DIM_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_START_X_DEFAULT 0x00000000 -#define mmCOMPUTE_START_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_START_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_NUM_THREAD_X_DEFAULT 0x00000000 -#define mmCOMPUTE_NUM_THREAD_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_NUM_THREAD_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_PIPELINESTAT_ENABLE_DEFAULT 0x00000001 -#define mmCOMPUTE_PERFCOUNT_ENABLE_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_RSRC1_DEFAULT 0x00000000 -#define mmCOMPUTE_PGM_RSRC2_DEFAULT 0x00000000 -#define mmCOMPUTE_VMID_DEFAULT 0x00000000 -#define mmCOMPUTE_RESOURCE_LIMITS_DEFAULT 0x00000000 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_DEFAULT 0xffffffff -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_DEFAULT 0xffffffff -#define mmCOMPUTE_TMPRING_SIZE_DEFAULT 0x00000000 -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_DEFAULT 0xffffffff -#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_DEFAULT 0xffffffff -#define mmCOMPUTE_RESTART_X_DEFAULT 0x00000000 -#define mmCOMPUTE_RESTART_Y_DEFAULT 0x00000000 -#define mmCOMPUTE_RESTART_Z_DEFAULT 0x00000000 -#define mmCOMPUTE_THREAD_TRACE_ENABLE_DEFAULT 0x00000000 -#define mmCOMPUTE_MISC_RESERVED_DEFAULT 0x00000002 -#define mmCOMPUTE_DISPATCH_ID_DEFAULT 0x00000000 -#define mmCOMPUTE_THREADGROUP_ID_DEFAULT 0x00000000 -#define mmCOMPUTE_RELAUNCH_DEFAULT 0x00000000 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_DEFAULT 0x00000000 -#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_0_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_1_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_2_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_3_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_4_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_5_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_6_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_7_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_8_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_9_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_10_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_11_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_12_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_13_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_14_DEFAULT 0x00000000 -#define mmCOMPUTE_USER_DATA_15_DEFAULT 0x00000000 -#define mmCOMPUTE_NOWHERE_DEFAULT 0x00000000 - - -// addressBlock: gc_cppdec -#define mmCP_DFY_CNTL_DEFAULT 0x00000000 -#define mmCP_DFY_STAT_DEFAULT 0x00000000 -#define mmCP_DFY_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DFY_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_0_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_1_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_2_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_3_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_4_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_5_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_6_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_7_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_8_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_9_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_10_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_11_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_12_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_13_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_14_DEFAULT 0x00000000 -#define mmCP_DFY_DATA_15_DEFAULT 0x00000000 -#define mmCP_DFY_CMD_DEFAULT 0x00000000 -#define mmCP_EOPQ_WAIT_TIME_DEFAULT 0x0000052c -#define mmCP_CPC_MGCG_SYNC_CNTL_DEFAULT 0x00001020 -#define mmCPC_INT_INFO_DEFAULT 0x00000000 -#define mmCP_VIRT_STATUS_DEFAULT 0x00000000 -#define mmCPC_INT_ADDR_DEFAULT 0x00000000 -#define mmCPC_INT_PASID_DEFAULT 0x00000000 -#define mmCP_GFX_ERROR_DEFAULT 0x00000000 -#define mmCPG_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmCPC_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmCPF_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmCP_AQL_SMM_STATUS_DEFAULT 0x00000000 -#define mmCP_RB0_BASE_DEFAULT 0x00000000 -#define mmCP_RB_BASE_DEFAULT 0x00000000 -#define mmCP_RB0_CNTL_DEFAULT 0x00400000 -#define mmCP_RB_CNTL_DEFAULT 0x00400000 -#define mmCP_RB_RPTR_WR_DEFAULT 0x00000000 -#define mmCP_RB0_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB0_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB0_BUFSZ_MASK_DEFAULT 0x00000000 -#define mmCP_RB_BUFSZ_MASK_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmGC_PRIV_MODE_DEFAULT 0x00000000 -#define mmCP_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_DEVICE_ID_DEFAULT 0x00000000 -#define mmCP_ME0_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_RING_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_ME0_PIPE0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_RING0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME0_PIPE1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_RING1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME0_PIPE2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_RING2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_FATAL_ERROR_DEFAULT 0x00000000 -#define mmCP_RB_VMID_DEFAULT 0x00000000 -#define mmCP_ME0_PIPE0_VMID_DEFAULT 0x00000000 -#define mmCP_ME0_PIPE1_VMID_DEFAULT 0x00000000 -#define mmCP_RB0_WPTR_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_DEFAULT 0x00000000 -#define mmCP_RB0_WPTR_HI_DEFAULT 0x00000000 -#define mmCP_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmCP_RB1_WPTR_DEFAULT 0x00000000 -#define mmCP_RB1_WPTR_HI_DEFAULT 0x00000000 -#define mmCP_RB2_WPTR_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_RANGE_LOWER_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_RANGE_UPPER_DEFAULT 0x00000044 -#define mmCP_MEC_DOORBELL_RANGE_LOWER_DEFAULT 0x00000048 -#define mmCP_MEC_DOORBELL_RANGE_UPPER_DEFAULT 0x0ffffffc -#define mmCPG_UTCL1_ERROR_DEFAULT 0x00000000 -#define mmCPC_UTCL1_ERROR_DEFAULT 0x00000000 -#define mmCP_RB1_BASE_DEFAULT 0x00000000 -#define mmCP_RB1_CNTL_DEFAULT 0x00400000 -#define mmCP_RB1_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB1_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB2_BASE_DEFAULT 0x00000000 -#define mmCP_RB2_CNTL_DEFAULT 0x00400000 -#define mmCP_RB2_RPTR_ADDR_DEFAULT 0x00000000 -#define mmCP_RB2_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB0_ACTIVE_DEFAULT 0x00000001 -#define mmCP_RB_ACTIVE_DEFAULT 0x00000001 -#define mmCP_INT_CNTL_RING0_DEFAULT 0x00000000 -#define mmCP_INT_CNTL_RING1_DEFAULT 0x00000000 -#define mmCP_INT_CNTL_RING2_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_RING0_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_RING1_DEFAULT 0x00000000 -#define mmCP_INT_STATUS_RING2_DEFAULT 0x00000000 -#define mmCP_PWR_CNTL_DEFAULT 0x00000000 -#define mmCP_MEM_SLP_CNTL_DEFAULT 0x00020200 -#define mmCP_ECC_FIRSTOCCURRENCE_DEFAULT 0x00000000 -#define mmCP_ECC_FIRSTOCCURRENCE_RING0_DEFAULT 0x00000000 -#define mmCP_ECC_FIRSTOCCURRENCE_RING1_DEFAULT 0x00000000 -#define mmCP_ECC_FIRSTOCCURRENCE_RING2_DEFAULT 0x00000000 -#define mmGB_EDC_MODE_DEFAULT 0x00000000 -#define mmCP_PQ_WPTR_POLL_CNTL_DEFAULT 0x00000001 -#define mmCP_PQ_WPTR_POLL_CNTL1_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE0_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE1_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE2_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE3_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE0_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE1_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE2_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE3_INT_CNTL_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE0_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE1_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE2_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE3_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE0_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE1_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE2_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_ME2_PIPE3_INT_STATUS_DEFAULT 0x00000000 -#define mmCC_GC_EDC_CONFIG_DEFAULT 0x00000000 -#define mmCP_ME1_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_ME1_PIPE0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME1_PIPE1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME1_PIPE2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME1_PIPE3_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE_PRIORITY_CNTS_DEFAULT 0x08081020 -#define mmCP_ME2_PIPE0_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE1_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE2_PRIORITY_DEFAULT 0x00000002 -#define mmCP_ME2_PIPE3_PRIORITY_DEFAULT 0x00000002 -#define mmCP_CE_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_PFP_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_ME_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_MEC1_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_MEC2_PRGRM_CNTR_START_DEFAULT 0x00000000 -#define mmCP_CE_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_PFP_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_ME_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_MEC1_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_MEC2_INTR_ROUTINE_START_DEFAULT 0x00000002 -#define mmCP_CONTEXT_CNTL_DEFAULT 0x00750075 -#define mmCP_MAX_CONTEXT_DEFAULT 0x00000007 -#define mmCP_IQ_WAIT_TIME1_DEFAULT 0x40404040 -#define mmCP_IQ_WAIT_TIME2_DEFAULT 0x40404040 -#define mmCP_RB0_BASE_HI_DEFAULT 0x00000000 -#define mmCP_RB1_BASE_HI_DEFAULT 0x00000000 -#define mmCP_VMID_RESET_DEFAULT 0x00000000 -#define mmCPC_INT_CNTL_DEFAULT 0x00000000 -#define mmCPC_INT_STATUS_DEFAULT 0x00000000 -#define mmCP_VMID_PREEMPT_DEFAULT 0x00000000 -#define mmCPC_INT_CNTX_ID_DEFAULT 0x00000000 -#define mmCP_PQ_STATUS_DEFAULT 0x00000000 -#define mmCP_CPC_IC_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CPC_IC_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CPC_IC_BASE_CNTL_DEFAULT 0x00000000 -#define mmCP_CPC_IC_OP_CNTL_DEFAULT 0x00000000 -#define mmCP_MEC1_F32_INT_DIS_DEFAULT 0x00000000 -#define mmCP_MEC2_F32_INT_DIS_DEFAULT 0x00000000 -#define mmCP_VMID_STATUS_DEFAULT 0x00000000 - - -// addressBlock: gc_cppdec2 -#define mmCP_RB_DOORBELL_CONTROL_SCH_0_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_1_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_2_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_3_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_4_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_5_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_6_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CONTROL_SCH_7_DEFAULT 0x00000000 -#define mmCP_RB_DOORBELL_CLEAR_DEFAULT 0x00000000 -#define mmCP_GFX_MQD_CONTROL_DEFAULT 0x00000100 -#define mmCP_GFX_MQD_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_GFX_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_RB_STATUS_DEFAULT 0x00000000 -#define mmCPG_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmCPC_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmCPF_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmCP_SD_CNTL_DEFAULT 0x0000001f -#define mmCP_SOFT_RESET_CNTL_DEFAULT 0x00000000 -#define mmCP_CPC_GFX_CNTL_DEFAULT 0x00000000 - - -// addressBlock: gc_spipdec -#define mmSPI_ARB_PRIORITY_DEFAULT 0x00000000 -#define mmSPI_ARB_CYCLES_0_DEFAULT 0x00000000 -#define mmSPI_ARB_CYCLES_1_DEFAULT 0x00000000 -#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff -#define mmSPI_WCL_PIPE_PERCENT_HP3D_DEFAULT 0x07c1f07f -#define mmSPI_WCL_PIPE_PERCENT_CS0_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS1_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS2_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS3_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS4_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f -#define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f -#define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_2_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_3_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_4_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_5_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_6_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_7_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_8_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_9_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_0_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_1_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_2_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_3_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_4_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_5_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_6_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_7_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_8_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_9_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_10_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_11_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_10_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_11_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_12_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_13_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_14_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_CU_15_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_12_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_13_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_14_DEFAULT 0x00000000 -#define mmSPI_RESOURCE_RESERVE_EN_CU_15_DEFAULT 0x00000000 -#define mmSPI_COMPUTE_WF_CTX_SAVE_DEFAULT 0x00000000 -#define mmSPI_ARB_CNTL_0_DEFAULT 0x00000000 - - -// addressBlock: gc_cpphqddec -#define mmCP_HQD_GFX_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_GFX_STATUS_DEFAULT 0x00000000 -#define mmCP_HPD_ROQ_OFFSETS_DEFAULT 0x00200604 -#define mmCP_HPD_STATUS0_DEFAULT 0x01000000 -#define mmCP_HPD_UTCL1_CNTL_DEFAULT 0x00000000 -#define mmCP_HPD_UTCL1_ERROR_DEFAULT 0x00000000 -#define mmCP_HPD_UTCL1_ERROR_ADDR_DEFAULT 0x00000000 -#define mmCP_MQD_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_MQD_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_ACTIVE_DEFAULT 0x00000000 -#define mmCP_HQD_VMID_DEFAULT 0x00000000 -#define mmCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05301 -#define mmCP_HQD_PIPE_PRIORITY_DEFAULT 0x00000000 -#define mmCP_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000 -#define mmCP_HQD_QUANTUM_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_BASE_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_BASE_HI_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_RPTR_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 -#define mmCP_HQD_IB_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_IB_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_IB_RPTR_DEFAULT 0x00000000 -#define mmCP_HQD_IB_CONTROL_DEFAULT 0x00300000 -#define mmCP_HQD_IQ_TIMER_DEFAULT 0x00000000 -#define mmCP_HQD_IQ_RPTR_DEFAULT 0x00000000 -#define mmCP_HQD_DEQUEUE_REQUEST_DEFAULT 0x00000000 -#define mmCP_HQD_DMA_OFFLOAD_DEFAULT 0x00000000 -#define mmCP_HQD_OFFLOAD_DEFAULT 0x00000000 -#define mmCP_HQD_SEMA_CMD_DEFAULT 0x00000000 -#define mmCP_HQD_MSG_TYPE_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_HQD_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_SCHEDULER0_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_STATUS0_DEFAULT 0x40000000 -#define mmCP_HQD_HQ_CONTROL0_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_SCHEDULER1_DEFAULT 0x00000000 -#define mmCP_MQD_CONTROL_DEFAULT 0x00000100 -#define mmCP_HQD_HQ_STATUS1_DEFAULT 0x00000000 -#define mmCP_HQD_HQ_CONTROL1_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_CONTROL_DEFAULT 0x00000006 -#define mmCP_HQD_EOP_RPTR_DEFAULT 0x40000000 -#define mmCP_HQD_EOP_WPTR_DEFAULT 0x007f8000 -#define mmCP_HQD_EOP_EVENTS_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_CNTL_STACK_OFFSET_DEFAULT 0x00000000 -#define mmCP_HQD_CNTL_STACK_SIZE_DEFAULT 0x00000000 -#define mmCP_HQD_WG_STATE_OFFSET_DEFAULT 0x00000000 -#define mmCP_HQD_CTX_SAVE_SIZE_DEFAULT 0x00000000 -#define mmCP_HQD_GDS_RESOURCE_STATE_DEFAULT 0x00000000 -#define mmCP_HQD_ERROR_DEFAULT 0x00000000 -#define mmCP_HQD_EOP_WPTR_MEM_DEFAULT 0x00000000 -#define mmCP_HQD_AQL_CONTROL_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_LO_DEFAULT 0x00000000 -#define mmCP_HQD_PQ_WPTR_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_didtdec -#define mmDIDT_IND_INDEX_DEFAULT 0x00000000 -#define mmDIDT_IND_DATA_DEFAULT 0x00000000 - - -// addressBlock: gc_gccacdec -#define mmGC_CAC_CTRL_1_DEFAULT 0x01000000 -#define mmGC_CAC_CTRL_2_DEFAULT 0x00000000 -#define mmGC_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmGC_CAC_AGGR_LOWER_DEFAULT 0x00000000 -#define mmGC_CAC_AGGR_UPPER_DEFAULT 0x00000000 -#define mmGC_CAC_PG_AGGR_LOWER_DEFAULT 0x00000000 -#define mmGC_CAC_PG_AGGR_UPPER_DEFAULT 0x00000000 -#define mmGC_CAC_SOFT_CTRL_DEFAULT 0x00000000 -#define mmGC_DIDT_CTRL0_DEFAULT 0x00000000 -#define mmGC_DIDT_CTRL1_DEFAULT 0xffff0000 -#define mmGC_DIDT_CTRL2_DEFAULT 0x1880000f -#define mmGC_DIDT_WEIGHT_DEFAULT 0x00000000 -#define mmGC_EDC_CTRL_DEFAULT 0x00000000 -#define mmGC_EDC_THRESHOLD_DEFAULT 0x00000000 -#define mmGC_EDC_STATUS_DEFAULT 0x00000000 -#define mmGC_EDC_OVERFLOW_DEFAULT 0x00000000 -#define mmGC_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define mmGC_DIDT_DROOP_CTRL_DEFAULT 0x00000000 -#define mmGC_EDC_DROOP_CTRL_DEFAULT 0x00100000 -#define mmGC_CAC_IND_INDEX_DEFAULT 0x00000000 -#define mmGC_CAC_IND_DATA_DEFAULT 0x00000000 -#define mmSE_CAC_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmSE_CAC_IND_INDEX_DEFAULT 0x00000000 -#define mmSE_CAC_IND_DATA_DEFAULT 0x00000000 - - -// addressBlock: gc_tcpdec -#define mmTCP_WATCH0_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH0_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH0_CNTL_DEFAULT 0x00000000 -#define mmTCP_WATCH1_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH1_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH1_CNTL_DEFAULT 0x00000000 -#define mmTCP_WATCH2_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH2_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH2_CNTL_DEFAULT 0x00000000 -#define mmTCP_WATCH3_ADDR_H_DEFAULT 0x00000000 -#define mmTCP_WATCH3_ADDR_L_DEFAULT 0x00000000 -#define mmTCP_WATCH3_CNTL_DEFAULT 0x00000000 -#define mmTCP_GATCL1_CNTL_DEFAULT 0x00000000 -#define mmTCP_ATC_EDC_GATCL1_CNT_DEFAULT 0x00000000 -#define mmTCP_GATCL1_DSM_CNTL_DEFAULT 0x00000000 -#define mmTCP_CNTL2_DEFAULT 0x0000000a -#define mmTCP_UTCL1_CNTL1_DEFAULT 0x00800400 -#define mmTCP_UTCL1_CNTL2_DEFAULT 0x00000000 -#define mmTCP_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER_FILTER_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER_FILTER_EN_DEFAULT 0x00000000 - - -// addressBlock: gc_gdspdec -#define mmGDS_VMID0_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID0_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID1_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID1_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID2_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID2_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID3_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID3_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID4_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID4_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID5_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID5_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID6_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID6_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID7_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID7_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID8_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID8_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID9_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID9_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID10_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID10_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID11_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID11_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID12_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID12_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID13_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID13_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID14_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID14_SIZE_DEFAULT 0x00010000 -#define mmGDS_VMID15_BASE_DEFAULT 0x00000000 -#define mmGDS_VMID15_SIZE_DEFAULT 0x00010000 -#define mmGDS_GWS_VMID0_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID1_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID2_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID3_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID4_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID5_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID6_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID7_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID8_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID9_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID10_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID11_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID12_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID13_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID14_DEFAULT 0x00400000 -#define mmGDS_GWS_VMID15_DEFAULT 0x00400000 -#define mmGDS_OA_VMID0_DEFAULT 0x00000000 -#define mmGDS_OA_VMID1_DEFAULT 0x00000000 -#define mmGDS_OA_VMID2_DEFAULT 0x00000000 -#define mmGDS_OA_VMID3_DEFAULT 0x00000000 -#define mmGDS_OA_VMID4_DEFAULT 0x00000000 -#define mmGDS_OA_VMID5_DEFAULT 0x00000000 -#define mmGDS_OA_VMID6_DEFAULT 0x00000000 -#define mmGDS_OA_VMID7_DEFAULT 0x00000000 -#define mmGDS_OA_VMID8_DEFAULT 0x00000000 -#define mmGDS_OA_VMID9_DEFAULT 0x00000000 -#define mmGDS_OA_VMID10_DEFAULT 0x00000000 -#define mmGDS_OA_VMID11_DEFAULT 0x00000000 -#define mmGDS_OA_VMID12_DEFAULT 0x00000000 -#define mmGDS_OA_VMID13_DEFAULT 0x00000000 -#define mmGDS_OA_VMID14_DEFAULT 0x00000000 -#define mmGDS_OA_VMID15_DEFAULT 0x00000000 -#define mmGDS_GWS_RESET0_DEFAULT 0x00000000 -#define mmGDS_GWS_RESET1_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_RESET_DEFAULT 0x00000000 -#define mmGDS_COMPUTE_MAX_WAVE_ID_DEFAULT 0x0000015f -#define mmGDS_OA_RESET_MASK_DEFAULT 0x00000000 -#define mmGDS_OA_RESET_DEFAULT 0x00000000 -#define mmGDS_ENHANCE_DEFAULT 0x00000000 -#define mmGDS_OA_CGPG_RESTORE_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_STATUS_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_CS_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_GFX_CTXSW_STATUS_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_VS_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS0_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS1_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS2_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS3_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS4_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS5_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS6_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_PS7_CTXSW_CNT3_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT0_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT1_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT2_DEFAULT 0x00000000 -#define mmGDS_GS_CTXSW_CNT3_DEFAULT 0x00000000 - - -// addressBlock: gc_rasdec -#define mmRAS_SIGNATURE_CONTROL_DEFAULT 0x00000000 -#define mmRAS_SIGNATURE_MASK_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE2_DEFAULT 0x00000000 -#define mmRAS_SX_SIGNATURE3_DEFAULT 0x00000000 -#define mmRAS_DB_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_PA_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_VGT_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SQ_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE2_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE3_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE4_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE5_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE6_DEFAULT 0x00000000 -#define mmRAS_SC_SIGNATURE7_DEFAULT 0x00000000 -#define mmRAS_IA_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_IA_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_SPI_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_SPI_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_TA_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_TD_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_CB_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_BCI_SIGNATURE0_DEFAULT 0x00000000 -#define mmRAS_BCI_SIGNATURE1_DEFAULT 0x00000000 -#define mmRAS_TA_SIGNATURE1_DEFAULT 0x00000000 - - -// addressBlock: gc_gfxdec0 -#define mmDB_RENDER_CONTROL_DEFAULT 0x00000000 -#define mmDB_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmDB_DEPTH_VIEW_DEFAULT 0x00000000 -#define mmDB_RENDER_OVERRIDE_DEFAULT 0x00000000 -#define mmDB_RENDER_OVERRIDE2_DEFAULT 0x00000000 -#define mmDB_HTILE_DATA_BASE_DEFAULT 0x00000000 -#define mmDB_HTILE_DATA_BASE_HI_DEFAULT 0x00000000 -#define mmDB_DEPTH_SIZE_DEFAULT 0x00000000 -#define mmDB_DEPTH_BOUNDS_MIN_DEFAULT 0x00000000 -#define mmDB_DEPTH_BOUNDS_MAX_DEFAULT 0x00000000 -#define mmDB_STENCIL_CLEAR_DEFAULT 0x00000000 -#define mmDB_DEPTH_CLEAR_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_SCISSOR_TL_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_SCISSOR_BR_DEFAULT 0x00000000 -#define mmDB_Z_INFO_DEFAULT 0x00000000 -#define mmDB_STENCIL_INFO_DEFAULT 0x00000000 -#define mmDB_Z_READ_BASE_DEFAULT 0x00000000 -#define mmDB_Z_READ_BASE_HI_DEFAULT 0x00000000 -#define mmDB_STENCIL_READ_BASE_DEFAULT 0x00000000 -#define mmDB_STENCIL_READ_BASE_HI_DEFAULT 0x00000000 -#define mmDB_Z_WRITE_BASE_DEFAULT 0x00000000 -#define mmDB_Z_WRITE_BASE_HI_DEFAULT 0x00000000 -#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 -#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 -#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000 -#define mmDB_RENDER_FILTER_DEFAULT 0x00000000 -#define mmDB_Z_INFO2_DEFAULT 0x00000000 -#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000 -#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000 -#define mmTA_BC_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_0_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_1_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_2_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_HI_3_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_2_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_3_DEFAULT 0x00000000 -#define mmPA_SC_WINDOW_OFFSET_DEFAULT 0x00000000 -#define mmPA_SC_WINDOW_SCISSOR_TL_DEFAULT 0x00000000 -#define mmPA_SC_WINDOW_SCISSOR_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_RULE_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_0_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_0_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_1_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_1_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_2_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_2_BR_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_3_TL_DEFAULT 0x00000000 -#define mmPA_SC_CLIPRECT_3_BR_DEFAULT 0x00000000 -#define mmPA_SC_EDGERULE_DEFAULT 0x00000000 -#define mmPA_SU_HARDWARE_SCREEN_OFFSET_DEFAULT 0x00000000 -#define mmCB_TARGET_MASK_DEFAULT 0x00000000 -#define mmCB_SHADER_MASK_DEFAULT 0x00000000 -#define mmPA_SC_GENERIC_SCISSOR_TL_DEFAULT 0x00000000 -#define mmPA_SC_GENERIC_SCISSOR_BR_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_0_DEFAULT 0x00000000 -#define mmCOHER_DEST_BASE_1_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_0_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_0_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_1_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_1_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_2_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_2_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_3_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_3_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_4_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_4_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_5_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_5_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_6_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_6_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_7_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_7_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_8_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_8_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_9_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_9_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_10_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_10_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_11_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_11_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_12_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_12_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_13_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_13_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_14_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_14_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_15_TL_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_SCISSOR_15_BR_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_0_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_0_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_1_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_1_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_2_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_2_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_3_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_3_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_4_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_4_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_5_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_5_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_6_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_6_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_7_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_7_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_8_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_8_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_9_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_9_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_10_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_10_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_11_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_11_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_12_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_12_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_13_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_13_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_14_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_14_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMIN_15_DEFAULT 0x00000000 -#define mmPA_SC_VPORT_ZMAX_15_DEFAULT 0x00000000 -#define mmPA_SC_RASTER_CONFIG_DEFAULT 0x00000000 -#define mmPA_SC_RASTER_CONFIG_1_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_EXTENT_CONTROL_DEFAULT 0x00000000 -#define mmPA_SC_TILE_STEERING_OVERRIDE_DEFAULT 0x00000000 -#define mmCP_PERFMON_CNTX_CNTL_DEFAULT 0x00000000 -#define mmCP_PIPEID_DEFAULT 0x00000000 -#define mmCP_RINGID_DEFAULT 0x00000000 -#define mmCP_VMID_DEFAULT 0x00000000 -#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000 -#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000 -#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000 -#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 -#define mmCB_BLEND_RED_DEFAULT 0x00000000 -#define mmCB_BLEND_GREEN_DEFAULT 0x00000000 -#define mmCB_BLEND_BLUE_DEFAULT 0x00000000 -#define mmCB_BLEND_ALPHA_DEFAULT 0x00000000 -#define mmCB_DCC_CONTROL_DEFAULT 0x00000000 -#define mmDB_STENCIL_CONTROL_DEFAULT 0x00000000 -#define mmDB_STENCILREFMASK_DEFAULT 0x00000000 -#define mmDB_STENCILREFMASK_BF_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_1_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_2_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_3_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_4_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_5_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_6_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_7_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_8_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_9_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_10_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_11_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_12_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_13_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_14_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XSCALE_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_XOFFSET_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YSCALE_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_YOFFSET_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZSCALE_15_DEFAULT 0x00000000 -#define mmPA_CL_VPORT_ZOFFSET_15_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_0_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_1_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_2_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_3_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_4_W_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_X_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_Y_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_Z_DEFAULT 0x00000000 -#define mmPA_CL_UCP_5_W_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_0_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_1_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_2_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_3_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_4_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_5_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_6_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_7_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_8_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_9_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_10_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_11_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_12_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_13_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_14_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_15_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_16_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_17_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_18_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_19_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_20_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_21_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_22_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_23_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_24_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_25_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_26_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_27_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_28_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_29_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_30_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_CNTL_31_DEFAULT 0x00000000 -#define mmSPI_VS_OUT_CONFIG_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_ENA_DEFAULT 0x00000000 -#define mmSPI_PS_INPUT_ADDR_DEFAULT 0x00000000 -#define mmSPI_INTERP_CONTROL_0_DEFAULT 0x00000000 -#define mmSPI_PS_IN_CONTROL_DEFAULT 0x00000000 -#define mmSPI_BARYC_CNTL_DEFAULT 0x00000000 -#define mmSPI_TMPRING_SIZE_DEFAULT 0x00000000 -#define mmSPI_SHADER_POS_FORMAT_DEFAULT 0x00000000 -#define mmSPI_SHADER_Z_FORMAT_DEFAULT 0x00000000 -#define mmSPI_SHADER_COL_FORMAT_DEFAULT 0x00000000 -#define mmSX_PS_DOWNCONVERT_DEFAULT 0x00000000 -#define mmSX_BLEND_OPT_EPSILON_DEFAULT 0x00000000 -#define mmSX_BLEND_OPT_CONTROL_DEFAULT 0x00000000 -#define mmSX_MRT0_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT1_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT2_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT3_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT4_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT5_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT6_BLEND_OPT_DEFAULT 0x00000000 -#define mmSX_MRT7_BLEND_OPT_DEFAULT 0x00000000 -#define mmCB_BLEND0_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND1_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND2_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND3_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND4_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND5_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND6_CONTROL_DEFAULT 0x00000000 -#define mmCB_BLEND7_CONTROL_DEFAULT 0x00000000 -#define mmCB_MRT0_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT1_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT2_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT3_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT4_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT5_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT6_EPITCH_DEFAULT 0x00000000 -#define mmCB_MRT7_EPITCH_DEFAULT 0x00000000 -#define mmCS_COPY_STATE_DEFAULT 0x00000000 -#define mmGFX_COPY_STATE_DEFAULT 0x00000000 -#define mmPA_CL_POINT_X_RAD_DEFAULT 0x00000000 -#define mmPA_CL_POINT_Y_RAD_DEFAULT 0x00000000 -#define mmPA_CL_POINT_SIZE_DEFAULT 0x00000000 -#define mmPA_CL_POINT_CULL_RAD_DEFAULT 0x00000000 -#define mmVGT_DMA_BASE_HI_DEFAULT 0x00000000 -#define mmVGT_DMA_BASE_DEFAULT 0x00000000 -#define mmVGT_DRAW_INITIATOR_DEFAULT 0x00000000 -#define mmVGT_IMMED_DATA_DEFAULT 0x00000000 -#define mmVGT_EVENT_ADDRESS_REG_DEFAULT 0x00000000 -#define mmDB_DEPTH_CONTROL_DEFAULT 0x00000000 -#define mmDB_EQAA_DEFAULT 0x00000000 -#define mmCB_COLOR_CONTROL_DEFAULT 0x00000000 -#define mmDB_SHADER_CONTROL_DEFAULT 0x00000000 -#define mmPA_CL_CLIP_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_SC_MODE_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_VTE_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_VS_OUT_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_NANINF_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_LINE_STIPPLE_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_LINE_STIPPLE_SCALE_DEFAULT 0x00000000 -#define mmPA_SU_PRIM_FILTER_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_SMALL_PRIM_FILTER_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_OBJPRIM_ID_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_NGG_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_OVER_RASTERIZATION_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_POINT_SIZE_DEFAULT 0x00000000 -#define mmPA_SU_POINT_MINMAX_DEFAULT 0x00000000 -#define mmPA_SU_LINE_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_LINE_STIPPLE_DEFAULT 0x00000000 -#define mmVGT_OUTPUT_PATH_CNTL_DEFAULT 0x00000000 -#define mmVGT_HOS_CNTL_DEFAULT 0x00000000 -#define mmVGT_HOS_MAX_TESS_LEVEL_DEFAULT 0x00000000 -#define mmVGT_HOS_MIN_TESS_LEVEL_DEFAULT 0x00000000 -#define mmVGT_HOS_REUSE_DEPTH_DEFAULT 0x00000000 -#define mmVGT_GROUP_PRIM_TYPE_DEFAULT 0x00000000 -#define mmVGT_GROUP_FIRST_DECR_DEFAULT 0x00000000 -#define mmVGT_GROUP_DECR_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_0_CNTL_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_1_CNTL_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_0_FMT_CNTL_DEFAULT 0x00000000 -#define mmVGT_GROUP_VECT_1_FMT_CNTL_DEFAULT 0x00000000 -#define mmVGT_GS_MODE_DEFAULT 0x00000000 -#define mmVGT_GS_ONCHIP_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_MODE_CNTL_0_DEFAULT 0x00000000 -#define mmPA_SC_MODE_CNTL_1_DEFAULT 0x06000000 -#define mmVGT_ENHANCE_DEFAULT 0x00000000 -#define mmVGT_GS_PER_ES_DEFAULT 0x00000000 -#define mmVGT_ES_PER_GS_DEFAULT 0x00000000 -#define mmVGT_GS_PER_VS_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_OFFSET_1_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_OFFSET_2_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_OFFSET_3_DEFAULT 0x00000000 -#define mmVGT_GS_OUT_PRIM_TYPE_DEFAULT 0x00000000 -#define mmIA_ENHANCE_DEFAULT 0x00000000 -#define mmVGT_DMA_SIZE_DEFAULT 0x00000000 -#define mmVGT_DMA_MAX_SIZE_DEFAULT 0x00000000 -#define mmVGT_DMA_INDEX_TYPE_DEFAULT 0x00000000 -#define mmWD_ENHANCE_DEFAULT 0x00000000 -#define mmVGT_PRIMITIVEID_EN_DEFAULT 0x00000000 -#define mmVGT_DMA_NUM_INSTANCES_DEFAULT 0x00000000 -#define mmVGT_PRIMITIVEID_RESET_DEFAULT 0x00000000 -#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000 -#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000 -#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 -#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000 -#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000 -#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000 -#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 -#define mmVGT_GSVS_RING_ITEMSIZE_DEFAULT 0x00000000 -#define mmVGT_REUSE_OFF_DEFAULT 0x00000000 -#define mmVGT_VTX_CNT_EN_DEFAULT 0x00000000 -#define mmDB_HTILE_SURFACE_DEFAULT 0x00000000 -#define mmDB_SRESULTS_COMPARE_STATE0_DEFAULT 0x00000000 -#define mmDB_SRESULTS_COMPARE_STATE1_DEFAULT 0x00000000 -#define mmDB_PRELOAD_CONTROL_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_SIZE_3_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_VTX_STRIDE_3_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_OFFSET_3_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_DEFAULT 0x00000000 -#define mmVGT_GS_MAX_VERT_OUT_DEFAULT 0x00000000 -#define mmVGT_TESS_DISTRIBUTION_DEFAULT 0x00000000 -#define mmVGT_SHADER_STAGES_EN_DEFAULT 0x00000000 -#define mmVGT_LS_HS_CONFIG_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_1_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_2_DEFAULT 0x00000000 -#define mmVGT_GS_VERT_ITEMSIZE_3_DEFAULT 0x00000000 -#define mmVGT_TF_PARAM_DEFAULT 0x00000000 -#define mmDB_ALPHA_TO_MASK_DEFAULT 0x00000000 -#define mmVGT_DISPATCH_DRAW_INDEX_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_CLAMP_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_FRONT_SCALE_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_BACK_SCALE_DEFAULT 0x00000000 -#define mmPA_SU_POLY_OFFSET_BACK_OFFSET_DEFAULT 0x00000000 -#define mmVGT_GS_INSTANCE_CNT_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_CONFIG_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_CONFIG_DEFAULT 0x00000000 -#define mmVGT_DMA_EVENT_INITIATOR_DEFAULT 0x00000000 -#define mmPA_SC_CENTROID_PRIORITY_0_DEFAULT 0x00000000 -#define mmPA_SC_CENTROID_PRIORITY_1_DEFAULT 0x00000000 -#define mmPA_SC_LINE_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_AA_CONFIG_DEFAULT 0x00000000 -#define mmPA_SU_VTX_CNTL_DEFAULT 0x00000000 -#define mmPA_CL_GB_VERT_CLIP_ADJ_DEFAULT 0x00000000 -#define mmPA_CL_GB_VERT_DISC_ADJ_DEFAULT 0x00000000 -#define mmPA_CL_GB_HORZ_CLIP_ADJ_DEFAULT 0x00000000 -#define mmPA_CL_GB_HORZ_DISC_ADJ_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_DEFAULT 0x00000000 -#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_DEFAULT 0x00000000 -#define mmPA_SC_AA_MASK_X0Y0_X1Y0_DEFAULT 0x00000000 -#define mmPA_SC_AA_MASK_X0Y1_X1Y1_DEFAULT 0x00000000 -#define mmPA_SC_SHADER_CONTROL_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_CNTL_0_DEFAULT 0x00000000 -#define mmPA_SC_BINNER_CNTL_1_DEFAULT 0x00000000 -#define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_DEFAULT 0x00000000 -#define mmPA_SC_NGG_MODE_CNTL_DEFAULT 0x00000000 -#define mmVGT_VERTEX_REUSE_BLOCK_CNTL_DEFAULT 0x00000000 -#define mmVGT_OUT_DEALLOC_CNTL_DEFAULT 0x00000000 -#define mmCB_COLOR0_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR0_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR0_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR0_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR0_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR0_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR0_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR0_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR0_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR0_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR0_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR0_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR0_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR0_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR0_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR1_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR1_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR1_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR1_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR1_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR1_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR1_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR1_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR1_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR1_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR1_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR1_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR2_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR2_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR2_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR2_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR2_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR2_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR2_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR2_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR2_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR2_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR2_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR2_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR3_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR3_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR3_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR3_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR3_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR3_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR3_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR3_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR3_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR3_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR3_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR3_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR4_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR4_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR4_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR4_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR4_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR4_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR4_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR4_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR4_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR4_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR4_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR4_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR5_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR5_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR5_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR5_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR5_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR5_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR5_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR5_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR5_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR5_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR5_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR5_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR6_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR6_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR6_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR6_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR6_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR6_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR6_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR6_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR6_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR6_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR6_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR6_DCC_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR7_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_ATTRIB2_DEFAULT 0x00000000 -#define mmCB_COLOR7_VIEW_DEFAULT 0x00000000 -#define mmCB_COLOR7_INFO_DEFAULT 0x00000000 -#define mmCB_COLOR7_ATTRIB_DEFAULT 0x00000000 -#define mmCB_COLOR7_DCC_CONTROL_DEFAULT 0x00000000 -#define mmCB_COLOR7_CMASK_DEFAULT 0x00000000 -#define mmCB_COLOR7_CMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_FMASK_DEFAULT 0x00000000 -#define mmCB_COLOR7_FMASK_BASE_EXT_DEFAULT 0x00000000 -#define mmCB_COLOR7_CLEAR_WORD0_DEFAULT 0x00000000 -#define mmCB_COLOR7_CLEAR_WORD1_DEFAULT 0x00000000 -#define mmCB_COLOR7_DCC_BASE_DEFAULT 0x00000000 -#define mmCB_COLOR7_DCC_BASE_EXT_DEFAULT 0x00000000 - - -// addressBlock: gc_gfxudec -#define mmCP_EOP_DONE_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_DATA_LO_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_DATA_HI_DEFAULT 0x00000000 -#define mmCP_EOP_LAST_FENCE_LO_DEFAULT 0x00000000 -#define mmCP_EOP_LAST_FENCE_HI_DEFAULT 0x00000000 -#define mmCP_STREAM_OUT_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_STREAM_OUT_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_DEFAULT 0x00000000 -#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_DEFAULT 0x00000000 -#define mmCP_PIPE_STATS_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_PIPE_STATS_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_VGT_IAVERT_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_IAVERT_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_IAPRIM_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_IAPRIM_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_GSPRIM_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_GSPRIM_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_VSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_VSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_GSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_GSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_HSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_HSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_VGT_DSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_DSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_PA_CINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_PA_CINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_PA_CPRIM_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_PA_CPRIM_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT0_LO_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT0_HI_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT1_LO_DEFAULT 0x00000000 -#define mmCP_SC_PSINVOC_COUNT1_HI_DEFAULT 0x00000000 -#define mmCP_VGT_CSINVOC_COUNT_LO_DEFAULT 0x00000000 -#define mmCP_VGT_CSINVOC_COUNT_HI_DEFAULT 0x00000000 -#define mmCP_PIPE_STATS_CONTROL_DEFAULT 0x00000000 -#define mmCP_STREAM_OUT_CONTROL_DEFAULT 0x00000000 -#define mmCP_STRMOUT_CNTL_DEFAULT 0x00000000 -#define mmSCRATCH_REG0_DEFAULT 0x00000000 -#define mmSCRATCH_REG1_DEFAULT 0x00000000 -#define mmSCRATCH_REG2_DEFAULT 0x00000000 -#define mmSCRATCH_REG3_DEFAULT 0x00000000 -#define mmSCRATCH_REG4_DEFAULT 0x00000000 -#define mmSCRATCH_REG5_DEFAULT 0x00000000 -#define mmSCRATCH_REG6_DEFAULT 0x00000000 -#define mmSCRATCH_REG7_DEFAULT 0x00000000 -#define mmCP_APPEND_DATA_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_CS_FENCE_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_PS_FENCE_HI_DEFAULT 0x00000000 -#define mmSCRATCH_UMSK_DEFAULT 0x00000000 -#define mmSCRATCH_ADDR_DEFAULT 0x00000000 -#define mmCP_PFP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_PFP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_APPEND_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_APPEND_DATA_LO_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_CS_FENCE_LO_DEFAULT 0x00000000 -#define mmCP_APPEND_LAST_PS_FENCE_LO_DEFAULT 0x00000000 -#define mmCP_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ME_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC0_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC0_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC1_PREOP_LO_DEFAULT 0x00000000 -#define mmCP_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_GDS_ATOMIC1_PREOP_HI_DEFAULT 0x00000000 -#define mmCP_ME_MC_WADDR_LO_DEFAULT 0x00000000 -#define mmCP_ME_MC_WADDR_HI_DEFAULT 0x00000000 -#define mmCP_ME_MC_WDATA_LO_DEFAULT 0x00000000 -#define mmCP_ME_MC_WDATA_HI_DEFAULT 0x00000000 -#define mmCP_ME_MC_RADDR_LO_DEFAULT 0x00000000 -#define mmCP_ME_MC_RADDR_HI_DEFAULT 0x00000000 -#define mmCP_SEM_WAIT_TIMER_DEFAULT 0x00000000 -#define mmCP_SIG_SEM_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_SIG_SEM_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_WAIT_REG_MEM_TIMEOUT_DEFAULT 0x00000000 -#define mmCP_WAIT_SEM_ADDR_LO_DEFAULT 0x00000000 -#define mmCP_WAIT_SEM_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_CONTROL_DEFAULT 0x00000000 -#define mmCP_DMA_ME_CONTROL_DEFAULT 0x00000000 -#define mmCP_COHER_BASE_HI_DEFAULT 0x00000000 -#define mmCP_COHER_START_DELAY_DEFAULT 0x00000020 -#define mmCP_COHER_CNTL_DEFAULT 0x00000000 -#define mmCP_COHER_SIZE_DEFAULT 0x00000000 -#define mmCP_COHER_BASE_DEFAULT 0x00000000 -#define mmCP_COHER_STATUS_DEFAULT 0x00000000 -#define mmCP_DMA_ME_SRC_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_ME_SRC_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_ME_DST_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_ME_DST_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_ME_COMMAND_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_SRC_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_SRC_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_DST_ADDR_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_DST_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DMA_PFP_COMMAND_DEFAULT 0x00000000 -#define mmCP_DMA_CNTL_DEFAULT 0x00080030 -#define mmCP_DMA_READ_TAGS_DEFAULT 0x00000000 -#define mmCP_COHER_SIZE_HI_DEFAULT 0x00000000 -#define mmCP_PFP_IB_CONTROL_DEFAULT 0x00000000 -#define mmCP_PFP_LOAD_CONTROL_DEFAULT 0x00000000 -#define mmCP_SCRATCH_INDEX_DEFAULT 0x00000000 -#define mmCP_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmCP_RB_OFFSET_DEFAULT 0x00000000 -#define mmCP_IB1_OFFSET_DEFAULT 0x00000000 -#define mmCP_IB2_OFFSET_DEFAULT 0x00000000 -#define mmCP_IB1_PREAMBLE_BEGIN_DEFAULT 0x00000000 -#define mmCP_IB1_PREAMBLE_END_DEFAULT 0x00000000 -#define mmCP_IB2_PREAMBLE_BEGIN_DEFAULT 0x00000000 -#define mmCP_IB2_PREAMBLE_END_DEFAULT 0x00000000 -#define mmCP_CE_IB1_OFFSET_DEFAULT 0x00000000 -#define mmCP_CE_IB2_OFFSET_DEFAULT 0x00000000 -#define mmCP_CE_COUNTER_DEFAULT 0x00000000 -#define mmCP_CE_RB_OFFSET_DEFAULT 0x00000000 -#define mmCP_CE_INIT_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB1_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB2_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB1_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB2_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_ST_CMD_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_INIT_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CE_INIT_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CE_INIT_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB1_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CE_IB1_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CE_IB1_BUFSZ_DEFAULT 0x00000000 -#define mmCP_CE_IB2_BASE_LO_DEFAULT 0x00000000 -#define mmCP_CE_IB2_BASE_HI_DEFAULT 0x00000000 -#define mmCP_CE_IB2_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB1_BASE_LO_DEFAULT 0x00000000 -#define mmCP_IB1_BASE_HI_DEFAULT 0x00000000 -#define mmCP_IB1_BUFSZ_DEFAULT 0x00000000 -#define mmCP_IB2_BASE_LO_DEFAULT 0x00000000 -#define mmCP_IB2_BASE_HI_DEFAULT 0x00000000 -#define mmCP_IB2_BUFSZ_DEFAULT 0x00000000 -#define mmCP_ST_BASE_LO_DEFAULT 0x00000000 -#define mmCP_ST_BASE_HI_DEFAULT 0x00000000 -#define mmCP_ST_BUFSZ_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_EVENT_CNTL_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_DATA_CNTL_DEFAULT 0x00000000 -#define mmCP_EOP_DONE_CNTX_ID_DEFAULT 0x00000000 -#define mmCP_PFP_COMPLETION_STATUS_DEFAULT 0x00000000 -#define mmCP_CE_COMPLETION_STATUS_DEFAULT 0x00000000 -#define mmCP_PRED_NOT_VISIBLE_DEFAULT 0x00000000 -#define mmCP_PFP_METADATA_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_PFP_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_CE_METADATA_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_CE_METADATA_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DRAW_INDX_INDR_ADDR_DEFAULT 0x00000000 -#define mmCP_DRAW_INDX_INDR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_DISPATCH_INDR_ADDR_DEFAULT 0x00000000 -#define mmCP_DISPATCH_INDR_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_INDEX_BASE_ADDR_DEFAULT 0x00000000 -#define mmCP_INDEX_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_INDEX_TYPE_DEFAULT 0x00000000 -#define mmCP_GDS_BKUP_ADDR_DEFAULT 0x00000000 -#define mmCP_GDS_BKUP_ADDR_HI_DEFAULT 0x00000000 -#define mmCP_SAMPLE_STATUS_DEFAULT 0x00000000 -#define mmCP_ME_COHER_CNTL_DEFAULT 0x00000000 -#define mmCP_ME_COHER_SIZE_DEFAULT 0x00000000 -#define mmCP_ME_COHER_SIZE_HI_DEFAULT 0x00000000 -#define mmCP_ME_COHER_BASE_DEFAULT 0x00000000 -#define mmCP_ME_COHER_BASE_HI_DEFAULT 0x00000000 -#define mmCP_ME_COHER_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPM_PERF_COUNT_0_DEFAULT 0x00000000 -#define mmRLC_GPM_PERF_COUNT_1_DEFAULT 0x00000000 -#define mmGRBM_GFX_INDEX_DEFAULT 0xe0000000 -#define mmVGT_GSVS_RING_SIZE_DEFAULT 0x00000000 -#define mmVGT_PRIMITIVE_TYPE_DEFAULT 0x00000000 -#define mmVGT_INDEX_TYPE_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_DEFAULT 0x00000000 -#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_DEFAULT 0x00000000 -#define mmVGT_MAX_VTX_INDX_DEFAULT 0x00000000 -#define mmVGT_MIN_VTX_INDX_DEFAULT 0x00000000 -#define mmVGT_INDX_OFFSET_DEFAULT 0x00000000 -#define mmVGT_MULTI_PRIM_IB_RESET_EN_DEFAULT 0x00000000 -#define mmVGT_NUM_INDICES_DEFAULT 0x00000000 -#define mmVGT_NUM_INSTANCES_DEFAULT 0x00000000 -#define mmVGT_TF_RING_SIZE_DEFAULT 0x00002000 -#define mmVGT_HS_OFFCHIP_PARAM_DEFAULT 0x00000000 -#define mmVGT_TF_MEMORY_BASE_DEFAULT 0x00000000 -#define mmVGT_TF_MEMORY_BASE_HI_DEFAULT 0x00000000 -#define mmWD_POS_BUF_BASE_DEFAULT 0x00000000 -#define mmWD_POS_BUF_BASE_HI_DEFAULT 0x00000000 -#define mmWD_CNTL_SB_BUF_BASE_DEFAULT 0x00000000 -#define mmWD_CNTL_SB_BUF_BASE_HI_DEFAULT 0x00000000 -#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000 -#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000 -#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff -#define mmVGT_OBJECT_ID_DEFAULT 0x00000000 -#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 -#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 -#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 -#define mmPA_SC_SCREEN_EXTENT_MIN_0_DEFAULT 0x7fff7fff -#define mmPA_SC_SCREEN_EXTENT_MAX_0_DEFAULT 0x80008000 -#define mmPA_SC_SCREEN_EXTENT_MIN_1_DEFAULT 0x7fff7fff -#define mmPA_SC_SCREEN_EXTENT_MAX_1_DEFAULT 0x80008000 -#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_H_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_V_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 -#define mmPA_SC_P3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_H_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_V_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 -#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_HV_EN_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_H_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_V_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_OCCURRENCE_DEFAULT 0x00000000 -#define mmPA_SC_TRAP_SCREEN_COUNT_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_BASE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_SIZE_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_MASK_DEFAULT 0x0000cf80 -#define mmSQ_THREAD_TRACE_TOKEN_MASK_DEFAULT 0x00ffffff -#define mmSQ_THREAD_TRACE_PERF_MASK_DEFAULT 0xffffffff -#define mmSQ_THREAD_TRACE_CTRL_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_MODE_DEFAULT 0x02049249 -#define mmSQ_THREAD_TRACE_BASE2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_TOKEN_MASK2_DEFAULT 0xffffffff -#define mmSQ_THREAD_TRACE_WPTR_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_STATUS_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_HIWATER_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_CNTR_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_0_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_1_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_2_DEFAULT 0x00000000 -#define mmSQ_THREAD_TRACE_USERDATA_3_DEFAULT 0x00000000 -#define mmSQC_CACHES_DEFAULT 0x00000000 -#define mmSQC_WRITEBACK_DEFAULT 0x00000000 -#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 -#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040 -#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT1_HI_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT2_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT2_HI_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT3_LOW_DEFAULT 0x00000000 -#define mmDB_OCCLUSION_COUNT3_HI_DEFAULT 0x00000000 -#define mmDB_ZPASS_COUNT_LOW_DEFAULT 0x00000000 -#define mmDB_ZPASS_COUNT_HI_DEFAULT 0x00000000 -#define mmGDS_RD_ADDR_DEFAULT 0x00000000 -#define mmGDS_RD_DATA_DEFAULT 0x00000000 -#define mmGDS_RD_BURST_ADDR_DEFAULT 0x00000000 -#define mmGDS_RD_BURST_COUNT_DEFAULT 0x00000000 -#define mmGDS_RD_BURST_DATA_DEFAULT 0x00000000 -#define mmGDS_WR_ADDR_DEFAULT 0x00000000 -#define mmGDS_WR_DATA_DEFAULT 0x00000000 -#define mmGDS_WR_BURST_ADDR_DEFAULT 0x00000000 -#define mmGDS_WR_BURST_DATA_DEFAULT 0x00000000 -#define mmGDS_WRITE_COMPLETE_DEFAULT 0x00000000 -#define mmGDS_ATOM_CNTL_DEFAULT 0x00000000 -#define mmGDS_ATOM_COMPLETE_DEFAULT 0x00000001 -#define mmGDS_ATOM_BASE_DEFAULT 0x00000000 -#define mmGDS_ATOM_SIZE_DEFAULT 0x00000000 -#define mmGDS_ATOM_OFFSET0_DEFAULT 0x00000000 -#define mmGDS_ATOM_OFFSET1_DEFAULT 0x00000000 -#define mmGDS_ATOM_DST_DEFAULT 0x00000000 -#define mmGDS_ATOM_OP_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC0_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC0_U_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC1_DEFAULT 0x00000000 -#define mmGDS_ATOM_SRC1_U_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ0_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ0_U_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ1_DEFAULT 0x00000000 -#define mmGDS_ATOM_READ1_U_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_CNTL_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_DEFAULT 0x00000000 -#define mmGDS_GWS_RESOURCE_CNT_DEFAULT 0x00000000 -#define mmGDS_OA_CNTL_DEFAULT 0x00000000 -#define mmGDS_OA_COUNTER_DEFAULT 0x00000000 -#define mmGDS_OA_ADDRESS_DEFAULT 0x00000000 -#define mmGDS_OA_INCDEC_DEFAULT 0x00000000 -#define mmGDS_OA_RING_SIZE_DEFAULT 0x00000000 -#define mmSPI_CONFIG_CNTL_DEFAULT 0x0062c688 -#define mmSPI_CONFIG_CNTL_1_DEFAULT 0x01000104 -#define mmSPI_CONFIG_CNTL_2_DEFAULT 0x00000011 - - -// addressBlock: gc_perfddec -#define mmCPG_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCPG_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCPG_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCPG_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCPF_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCPF_LATENCY_STATS_DATA_DEFAULT 0x00000000 -#define mmCPG_LATENCY_STATS_DATA_DEFAULT 0x00000000 -#define mmCPC_LATENCY_STATS_DATA_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmGRBM_SE0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGRBM_SE1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE1_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGRBM_SE2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE2_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmGRBM_SE3_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmGRBM_SE3_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER4_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER4_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER5_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER5_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER6_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER6_HI_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER7_LO_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER7_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER4_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER4_LO_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER5_HI_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER5_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER4_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER4_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER5_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER5_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER6_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER6_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER7_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER7_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER8_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER8_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER9_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER9_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER10_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER10_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER11_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER11_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER12_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER12_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER13_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER13_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER14_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER14_HI_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER15_LO_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER15_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmTCC_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmTCA_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER3_HI_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER1_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER1_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_HI_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER3_LO_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER3_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_atcl2pfcntrdec -#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_utcl2_vml2prdec -#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: gc_perfsdec -#define mmCPG_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 -#define mmCPG_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 -#define mmCPG_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 -#define mmCPC_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 -#define mmCPC_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 -#define mmCPF_PERFCOUNTER1_SELECT_DEFAULT 0x11000401 -#define mmCPF_PERFCOUNTER0_SELECT1_DEFAULT 0x11000401 -#define mmCPF_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 -#define mmCP_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmCPC_PERFCOUNTER0_SELECT_DEFAULT 0x11000401 -#define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 -#define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_DEFAULT 0x00000000 -#define mmCPF_LATENCY_STATS_SELECT_DEFAULT 0x00000000 -#define mmCPG_LATENCY_STATS_SELECT_DEFAULT 0x00000000 -#define mmCPC_LATENCY_STATS_SELECT_DEFAULT 0x00000000 -#define mmCP_DRAW_OBJECT_DEFAULT 0x00000000 -#define mmCP_DRAW_OBJECT_COUNTER_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_MASK_HI_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_HI_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_LO_DEFAULT 0x00000000 -#define mmCP_DRAW_WINDOW_CNTL_DEFAULT 0x00000007 -#define mmGRBM_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmGRBM_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE0_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE1_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE2_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmGRBM_SE3_PERFCOUNTER_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmWD_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmIA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmVGT_PERFCOUNTER_SEID_MASK_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmPA_SU_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER4_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER5_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER6_SELECT_DEFAULT 0x00000000 -#define mmPA_SC_PERFCOUNTER7_SELECT_DEFAULT 0x00000000 -#define mmSPI_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER2_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER3_SELECT_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER2_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER3_SELECT1_DEFAULT 0x000fffff -#define mmSPI_PERFCOUNTER4_SELECT_DEFAULT 0x000000ff -#define mmSPI_PERFCOUNTER5_SELECT_DEFAULT 0x000000ff -#define mmSPI_PERFCOUNTER_BINS_DEFAULT 0xfcb87430 -#define mmSQ_PERFCOUNTER0_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER1_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER2_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER3_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER4_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER5_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER6_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER7_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER8_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER9_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER10_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER11_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER12_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER13_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER14_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER15_SELECT_DEFAULT 0x0f0ff000 -#define mmSQ_PERFCOUNTER_CTRL_DEFAULT 0x00000000 -#define mmSQ_PERFCOUNTER_MASK_DEFAULT 0xffffffff -#define mmSQ_PERFCOUNTER_CTRL2_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmSX_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmGDS_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmTA_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmTD_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmTCP_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmTCP_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff -#define mmTCP_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff -#define mmTCC_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmTCC_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff -#define mmTCC_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff -#define mmTCA_PERFCOUNTER0_SELECT_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER0_SELECT1_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER1_SELECT_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER1_SELECT1_DEFAULT 0x000fffff -#define mmTCA_PERFCOUNTER2_SELECT_DEFAULT 0x000003ff -#define mmTCA_PERFCOUNTER3_SELECT_DEFAULT 0x000003ff -#define mmCB_PERFCOUNTER_FILTER_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmCB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER1_SELECT1_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmDB_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_RING_BASE_LO_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_RING_BASE_HI_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_RING_SIZE_DEFAULT 0x00000000 -#define mmRLC_SPM_PERFMON_SEGMENT_SIZE_DEFAULT 0x00000000 -#define mmRLC_SPM_SE_MUXSEL_ADDR_DEFAULT 0x00000000 -#define mmRLC_SPM_SE_MUXSEL_DATA_DEFAULT 0x00000000 -#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_DEFAULT 0x00000000 -#define mmRLC_SPM_GLOBAL_MUXSEL_DATA_DEFAULT 0x00000000 -#define mmRLC_SPM_RING_RDPTR_DEFAULT 0x00000000 -#define mmRLC_SPM_SEGMENT_THRESHOLD_DEFAULT 0x00000000 -#define mmRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_DEFAULT 0x00000000 -#define mmRLC_PERFMON_CLK_CNTL_DEFAULT 0x00000001 -#define mmRLC_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmRLC_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER0_SELECT1_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER1_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER2_SELECT1_DEFAULT 0x00000000 -#define mmRMI_PERFCOUNTER3_SELECT_DEFAULT 0x00000000 -#define mmRMI_PERF_COUNTER_CNTL_DEFAULT 0x00080240 - - -// addressBlock: gc_utcl2_atcl2pfcntldec -#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: gc_utcl2_vml2pldec -#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: gc_rlcpdec -#define mmRLC_CNTL_DEFAULT 0x00000001 -#define mmRLC_STAT_DEFAULT 0x00000000 -#define mmRLC_SAFE_MODE_DEFAULT 0x00000000 -#define mmRLC_MEM_SLP_CNTL_DEFAULT 0x00020200 -#define mmSMU_RLC_RESPONSE_DEFAULT 0x00000000 -#define mmRLC_RLCV_SAFE_MODE_DEFAULT 0x00000000 -#define mmRLC_SMU_SAFE_MODE_DEFAULT 0x00000000 -#define mmRLC_RLCV_COMMAND_DEFAULT 0x00000000 -#define mmRLC_REFCLOCK_TIMESTAMP_LSB_DEFAULT 0x00000000 -#define mmRLC_REFCLOCK_TIMESTAMP_MSB_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_0_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_1_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_2_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_CTRL_DEFAULT 0x00000000 -#define mmRLC_LB_CNTR_MAX_DEFAULT 0xffffffff -#define mmRLC_GPM_TIMER_STAT_DEFAULT 0x00000000 -#define mmRLC_GPM_TIMER_INT_3_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_1_DEFAULT 0x00000000 -#define mmRLC_SERDES_NONCU_MASTER_BUSY_1_DEFAULT 0x00000000 -#define mmRLC_INT_STAT_DEFAULT 0x00000000 -#define mmRLC_LB_CNTL_DEFAULT 0x00000010 -#define mmRLC_MGCG_CTRL_DEFAULT 0x00018800 -#define mmRLC_LB_CNTR_INIT_DEFAULT 0x00000000 -#define mmRLC_LOAD_BALANCE_CNTR_DEFAULT 0x00000000 -#define mmRLC_JUMP_TABLE_RESTORE_DEFAULT 0x00000000 -#define mmRLC_PG_DELAY_2_DEFAULT 0x00000004 -#define mmRLC_GPU_CLOCK_COUNT_LSB_DEFAULT 0x00000000 -#define mmRLC_GPU_CLOCK_COUNT_MSB_DEFAULT 0x00000000 -#define mmRLC_CAPTURE_GPU_CLOCK_COUNT_DEFAULT 0x00000000 -#define mmRLC_UCODE_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPM_THREAD_RESET_DEFAULT 0x0000000f -#define mmRLC_GPM_CP_DMA_COMPLETE_T0_DEFAULT 0x00000000 -#define mmRLC_GPM_CP_DMA_COMPLETE_T1_DEFAULT 0x00000000 -#define mmRLC_FIREWALL_VIOLATION_DEFAULT 0x00000000 -#define mmRLC_GPM_STAT_DEFAULT 0x00100016 -#define mmRLC_GPU_CLOCK_32_RES_SEL_DEFAULT 0x00000000 -#define mmRLC_GPU_CLOCK_32_DEFAULT 0x00000000 -#define mmRLC_PG_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPM_THREAD_PRIORITY_DEFAULT 0x08080808 -#define mmRLC_GPM_THREAD_ENABLE_DEFAULT 0x00000001 -#define mmRLC_CGTT_MGCG_OVERRIDE_DEFAULT 0xffffffff -#define mmRLC_CGCG_CGLS_CTRL_DEFAULT 0x0001003c -#define mmRLC_CGCG_RAMP_CTRL_DEFAULT 0x00021711 -#define mmRLC_DYN_PG_STATUS_DEFAULT 0xffffffff -#define mmRLC_DYN_PG_REQUEST_DEFAULT 0xffffffff -#define mmRLC_PG_DELAY_DEFAULT 0x00101010 -#define mmRLC_CU_STATUS_DEFAULT 0x00000000 -#define mmRLC_LB_INIT_CU_MASK_DEFAULT 0xffffffff -#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK_DEFAULT 0x00000001 -#define mmRLC_LB_PARAMS_DEFAULT 0x00601008 -#define mmRLC_THREAD1_DELAY_DEFAULT 0x00400401 -#define mmRLC_PG_ALWAYS_ON_CU_MASK_DEFAULT 0x00000003 -#define mmRLC_MAX_PG_CU_DEFAULT 0x0000000b -#define mmRLC_AUTO_PG_CTRL_DEFAULT 0x00000000 -#define mmRLC_SMU_GRBM_REG_SAVE_CTRL_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_MASTER_INDEX_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_DATA_0_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_DATA_1_DEFAULT 0x00000000 -#define mmRLC_SERDES_RD_DATA_2_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_CU_MASTER_MASK_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_NONCU_MASTER_MASK_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_CTRL_DEFAULT 0x00000000 -#define mmRLC_SERDES_WR_DATA_DEFAULT 0x00000000 -#define mmRLC_SERDES_CU_MASTER_BUSY_DEFAULT 0x00000000 -#define mmRLC_SERDES_NONCU_MASTER_BUSY_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_0_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_1_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_2_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_3_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_4_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_5_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_6_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_7_DEFAULT 0x00000000 -#define mmRLC_GPM_SCRATCH_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPM_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmRLC_STATIC_PG_STATUS_DEFAULT 0xffffffff -#define mmRLC_SPM_MC_CNTL_DEFAULT 0x00000000 -#define mmRLC_SPM_INT_CNTL_DEFAULT 0x00000000 -#define mmRLC_SPM_INT_STATUS_DEFAULT 0x00000000 -#define mmRLC_SMU_MESSAGE_DEFAULT 0x00000000 -#define mmRLC_GPM_LOG_SIZE_DEFAULT 0x00000000 -#define mmRLC_PG_DELAY_3_DEFAULT 0x00000000 -#define mmRLC_GPR_REG1_DEFAULT 0x00000000 -#define mmRLC_GPR_REG2_DEFAULT 0x00000000 -#define mmRLC_GPM_LOG_CONT_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_DISABLE_TH0_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_DISABLE_TH1_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_FORCE_TH0_DEFAULT 0x00000000 -#define mmRLC_GPM_INT_FORCE_TH1_DEFAULT 0x00000000 -#define mmRLC_SRM_CNTL_DEFAULT 0x00000002 -#define mmRLC_SRM_ARAM_ADDR_DEFAULT 0x00000000 -#define mmRLC_SRM_ARAM_DATA_DEFAULT 0x00000000 -#define mmRLC_SRM_DRAM_ADDR_DEFAULT 0x00000000 -#define mmRLC_SRM_DRAM_DATA_DEFAULT 0x00000000 -#define mmRLC_SRM_GPM_COMMAND_DEFAULT 0x00000000 -#define mmRLC_SRM_GPM_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmRLC_SRM_RLCV_COMMAND_DEFAULT 0x00000000 -#define mmRLC_SRM_RLCV_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_0_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_1_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_2_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_3_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_4_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_5_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_6_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_ADDR_7_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_0_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_1_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_2_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_3_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_4_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_5_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_6_DEFAULT 0x00000000 -#define mmRLC_SRM_INDEX_CNTL_DATA_7_DEFAULT 0x00000000 -#define mmRLC_SRM_STAT_DEFAULT 0x00000000 -#define mmRLC_SRM_GPM_ABORT_DEFAULT 0x00000000 -#define mmRLC_CSIB_ADDR_LO_DEFAULT 0x00000000 -#define mmRLC_CSIB_ADDR_HI_DEFAULT 0x00000000 -#define mmRLC_CSIB_LENGTH_DEFAULT 0x00000000 -#define mmRLC_SMU_COMMAND_DEFAULT 0x00000000 -#define mmRLC_CP_SCHEDULERS_DEFAULT 0x58504840 -#define mmRLC_SMU_ARGUMENT_1_DEFAULT 0x00000000 -#define mmRLC_SMU_ARGUMENT_2_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_8_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_9_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_10_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_11_DEFAULT 0x00000000 -#define mmRLC_GPM_GENERAL_12_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_CNTL_0_DEFAULT 0x00000080 -#define mmRLC_GPM_UTCL1_CNTL_1_DEFAULT 0x00000080 -#define mmRLC_GPM_UTCL1_CNTL_2_DEFAULT 0x00000080 -#define mmRLC_SPM_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmRLC_UTCL1_STATUS_2_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_2_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_3_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_4_DEFAULT 0x00000000 -#define mmRLC_SPM_UTCL1_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_SPM_UTCL1_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH0_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_LB_THR_CONFIG_1_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH0_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH1_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH1_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH2_ERROR_1_DEFAULT 0x00000000 -#define mmRLC_GPM_UTCL1_TH2_ERROR_2_DEFAULT 0x00000000 -#define mmRLC_CGCG_CGLS_CTRL_3D_DEFAULT 0x0001003c -#define mmRLC_CGCG_RAMP_CTRL_3D_DEFAULT 0x00021711 -#define mmRLC_SEMAPHORE_0_DEFAULT 0x00000000 -#define mmRLC_SEMAPHORE_1_DEFAULT 0x00000000 -#define mmRLC_CP_EOF_INT_DEFAULT 0x00000000 -#define mmRLC_CP_EOF_INT_CNT_DEFAULT 0x00000000 -#define mmRLC_SPARE_INT_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_CNTL_DEFAULT 0x00000080 -#define mmRLC_PREWALKER_UTCL1_TRIG_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_ADDR_LSB_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_ADDR_MSB_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_SIZE_LSB_DEFAULT 0x00000000 -#define mmRLC_PREWALKER_UTCL1_SIZE_MSB_DEFAULT 0x00000000 -#define mmRLC_DSM_TRIG_DEFAULT 0x00000000 -#define mmRLC_UTCL1_STATUS_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_0_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_1_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_2_DEFAULT 0x00000000 -#define mmRLC_R2I_CNTL_3_DEFAULT 0x00000000 -#define mmRLC_UTCL2_CNTL_DEFAULT 0x00000000 -#define mmRLC_LBPW_CU_STAT_DEFAULT 0x00000000 -#define mmRLC_DS_CNTL_DEFAULT 0x00030003 -#define mmRLC_RLCV_SPARE_INT_DEFAULT 0x00000000 - - -// addressBlock: gc_pwrdec -#define mmCGTS_SM_CTRL_REG_DEFAULT 0x00600200 -#define mmCGTS_RD_CTRL_REG_DEFAULT 0x00000000 -#define mmCGTS_RD_REG_DEFAULT 0x00000000 -#define mmCGTS_TCC_DISABLE_DEFAULT 0x00000000 -#define mmCGTS_USER_TCC_DISABLE_DEFAULT 0x00000000 -#define mmCGTS_CU0_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU0_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU0_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU0_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU0_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU1_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU1_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU1_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU1_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU1_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU2_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU2_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU2_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU2_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU2_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU3_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU3_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU3_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU3_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU3_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU4_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU4_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU4_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU4_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU4_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU5_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU5_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU5_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU5_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU5_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU6_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU6_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU6_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU6_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU6_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU7_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU7_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU7_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU7_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU7_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU8_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU8_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU8_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU8_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU8_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU9_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU9_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU9_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU9_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU9_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU10_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU10_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU10_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU10_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU10_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU11_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU11_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU11_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU11_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU11_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU12_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU12_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU12_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU12_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU12_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU13_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU13_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU13_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU13_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU13_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU14_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU14_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU14_TA_SQC_CTRL_REG_DEFAULT 0x00000007 -#define mmCGTS_CU14_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU14_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU15_SP0_CTRL_REG_DEFAULT 0x00010000 -#define mmCGTS_CU15_LDS_SQ_CTRL_REG_DEFAULT 0x00030002 -#define mmCGTS_CU15_TA_SQC_CTRL_REG_DEFAULT 0x00040007 -#define mmCGTS_CU15_SP1_CTRL_REG_DEFAULT 0x00060005 -#define mmCGTS_CU15_TD_TCP_CTRL_REG_DEFAULT 0x00090008 -#define mmCGTS_CU0_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU1_TCPI_CTRL_REG_DEFAULT 0x00000001 -#define mmCGTS_CU2_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU3_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU4_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU5_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU6_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU7_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU8_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU9_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU10_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU11_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU12_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU13_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU14_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTS_CU15_TCPI_CTRL_REG_DEFAULT 0x0000000a -#define mmCGTT_SPI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_PC_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_BCI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_VGT_CLK_CTRL_DEFAULT 0x00018100 -#define mmCGTT_IA_CLK_CTRL_DEFAULT 0x06000100 -#define mmCGTT_WD_CLK_CTRL_DEFAULT 0x00018100 -#define mmCGTT_PA_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_SC_CLK_CTRL0_DEFAULT 0x00000100 -#define mmCGTT_SC_CLK_CTRL1_DEFAULT 0x00000100 -#define mmCGTT_SQ_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_SQG_CLK_CTRL_DEFAULT 0x00000100 -#define mmSQ_ALU_CLK_CTRL_DEFAULT 0x00000000 -#define mmSQ_TEX_CLK_CTRL_DEFAULT 0x00000000 -#define mmSQ_LDS_CLK_CTRL_DEFAULT 0x00000000 -#define mmSQ_POWER_THROTTLE_DEFAULT 0x3fff3fff -#define mmSQ_POWER_THROTTLE2_DEFAULT 0x18800004 -#define mmCGTT_SX_CLK_CTRL0_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL1_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL2_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL3_DEFAULT 0x00000100 -#define mmCGTT_SX_CLK_CTRL4_DEFAULT 0x00000100 -#define mmTD_CGTT_CTRL_DEFAULT 0x00000100 -#define mmTA_CGTT_CTRL_DEFAULT 0x00000100 -#define mmCGTT_TCPI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_TCI_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_GDS_CLK_CTRL_DEFAULT 0x00000100 -#define mmDB_CGTT_CLK_CTRL_0_DEFAULT 0x00000100 -#define mmCB_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmTCC_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmTCA_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_CP_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_CPF_CLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_CPC_CLK_CTRL_DEFAULT 0x00000100 -#define mmRLC_PWR_CTRL_DEFAULT 0x00000000 -#define mmCGTT_RLC_CLK_CTRL_DEFAULT 0x00000100 -#define mmRLC_GFX_RM_CNTL_DEFAULT 0x00000000 -#define mmRMI_CGTT_SCLK_CTRL_DEFAULT 0x00000100 -#define mmCGTT_TCPF_CLK_CTRL_DEFAULT 0x00000100 - - -// addressBlock: gc_ea_pwrdec -#define mmGCEA_CGTT_CLK_CTRL_DEFAULT 0x00000100 - - -// addressBlock: gc_utcl2_vmsharedhvdec -#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 -#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 -#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 -#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: gc_hypdec -#define mmCP_HYP_PFP_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_PFP_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_PFP_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_PFP_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_ME_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_ME_RAM_RADDR_DEFAULT 0x00000000 -#define mmCP_ME_RAM_WADDR_DEFAULT 0x00000000 -#define mmCP_HYP_ME_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_ME_RAM_DATA_DEFAULT 0x00000000 -#define mmCP_CE_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_CE_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_CE_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_CE_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_MEC1_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_MEC_ME1_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_MEC1_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_MEC_ME1_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_HYP_MEC2_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_MEC_ME2_UCODE_ADDR_DEFAULT 0x00000000 -#define mmCP_HYP_MEC2_UCODE_DATA_DEFAULT 0x00000000 -#define mmCP_MEC_ME2_UCODE_DATA_DEFAULT 0x00000000 -#define mmRLC_GPM_UCODE_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPM_UCODE_DATA_DEFAULT 0x00000000 -#define mmGRBM_GFX_INDEX_SR_SELECT_DEFAULT 0x00000000 -#define mmGRBM_GFX_INDEX_SR_DATA_DEFAULT 0xe0000000 -#define mmGRBM_GFX_CNTL_SR_SELECT_DEFAULT 0x00000000 -#define mmGRBM_GFX_CNTL_SR_DATA_DEFAULT 0x00000000 -#define mmGRBM_CAM_INDEX_DEFAULT 0x00000000 -#define mmGRBM_HYP_CAM_INDEX_DEFAULT 0x00000000 -#define mmGRBM_CAM_DATA_DEFAULT 0x00000000 -#define mmGRBM_HYP_CAM_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_ENABLE_DEFAULT 0x00000000 -#define mmRLC_GFX_RM_CNTL_ADJ_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG6_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG8_DEFAULT 0x00000000 -#define mmRLC_RLCV_TIMER_INT_0_DEFAULT 0x00000000 -#define mmRLC_RLCV_TIMER_CTRL_DEFAULT 0x00000000 -#define mmRLC_RLCV_TIMER_STAT_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_DEFAULT 0x0000ffff -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VF_MASK_DEFAULT 0x00010001 -#define mmRLC_HYP_SEMAPHORE_2_DEFAULT 0x00000000 -#define mmRLC_HYP_SEMAPHORE_3_DEFAULT 0x00000000 -#define mmRLC_CLK_CNTL_DEFAULT 0x00000003 -#define mmRLC_GPU_IOV_SCH_BLOCK_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG1_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_CFG_REG2_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VM_BUSY_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_0_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_3_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_1_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCH_2_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_UCODE_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_UCODE_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCRATCH_ADDR_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SCRATCH_DATA_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_F32_CNTL_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_F32_RESET_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA0_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA1_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SMU_RESPONSE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_RLC_RESPONSE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_INT_DISABLE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_INT_FORCE_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_DEFAULT 0x00000000 -#define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_DEFAULT 0x00000000 - - -// addressBlock: gccacind -#define ixGC_CAC_CNTL_DEFAULT 0x000001fe -#define ixGC_CAC_OVR_SEL_DEFAULT 0x00000000 -#define ixGC_CAC_OVR_VAL_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_BCI_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CB_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CB_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CP_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CP_1_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_DB_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_DB_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_GDS_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_GDS_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_IA_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_LDS_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_LDS_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_PA_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_PC_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SC_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SPI_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SPI_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SPI_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_3_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_SQ_4_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SX_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_SXRB_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TA_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_TCC_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCC_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCC_2_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_TCP_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCP_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TCP_2_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_TD_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TD_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_TD_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_VGT_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_VGT_1_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_WD_0_DEFAULT 0x00000001 -#define ixGC_CAC_WEIGHT_CU_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_3_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_4_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_CU_5_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_BCI0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CB3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CP0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CP1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CP2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_DB3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_GDS3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_IA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_LDS3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_PA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_PA1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_PC0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SC0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SPI5_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_PG_0_DEFAULT 0x00000001 -#define ixGC_CAC_ACC_PG0_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_PG_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_EA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ATCL20_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_EA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_ATCL2_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_EA_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_EA_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_RMI_0_DEFAULT 0x00000001 -#define ixGC_CAC_ACC_RMI0_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_RMI_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_UTCL2_ATCL21_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ATCL22_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ATCL23_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_EA5_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_EA_2_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_SQ0_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ0_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ1_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ1_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ2_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ2_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ3_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ3_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ4_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ4_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ5_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ5_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ6_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ6_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ7_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ7_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ8_LOWER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SQ8_UPPER_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SX0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SXRB0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_SXRB1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TA0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCC4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TCP4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_TD5_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_VGT0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_VGT1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_VGT2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_WD0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU5_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU6_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU7_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU8_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU9_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_CU10_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_BCI_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_CB_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_CP_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_DB_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_GDS_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_IA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_LDS_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_PA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_PC_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SC_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SPI_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_CU_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SQ_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SX_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_SXRB_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TA_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TCC_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TCP_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_TD_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_VGT_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_WD_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_BCI1_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_VML2_2_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_UTCL2_ATCL24_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER4_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER5_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER6_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER7_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER8_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_ROUTER9_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML20_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML21_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML22_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML23_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_VML24_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_ROUTER_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_VML2_DEFAULT 0x00000000 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_0_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_1_DEFAULT 0x00010001 -#define ixGC_CAC_WEIGHT_UTCL2_WALKER_2_DEFAULT 0x00010001 -#define ixGC_CAC_ACC_UTCL2_WALKER0_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER1_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER2_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER3_DEFAULT 0x00000000 -#define ixGC_CAC_ACC_UTCL2_WALKER4_DEFAULT 0x00000000 -#define ixGC_CAC_OVRD_UTCL2_WALKER_DEFAULT 0x00000000 - - -// addressBlock: secacind -#define ixSE_CAC_CNTL_DEFAULT 0x000001fe -#define ixSE_CAC_OVR_SEL_DEFAULT 0x00000000 -#define ixSE_CAC_OVR_VAL_DEFAULT 0x00000000 - - -// addressBlock: sqind -#define ixSQ_WAVE_MODE_DEFAULT 0x00000000 -#define ixSQ_WAVE_STATUS_DEFAULT 0x00000000 -#define ixSQ_WAVE_TRAPSTS_DEFAULT 0x00000000 -#define ixSQ_WAVE_HW_ID_DEFAULT 0x00000000 -#define ixSQ_WAVE_GPR_ALLOC_DEFAULT 0x00000000 -#define ixSQ_WAVE_LDS_ALLOC_DEFAULT 0x00000000 -#define ixSQ_WAVE_IB_STS_DEFAULT 0x00000000 -#define ixSQ_WAVE_PC_LO_DEFAULT 0x00000000 -#define ixSQ_WAVE_PC_HI_DEFAULT 0x00000000 -#define ixSQ_WAVE_INST_DW0_DEFAULT 0x00000000 -#define ixSQ_WAVE_INST_DW1_DEFAULT 0x00000000 -#define ixSQ_WAVE_IB_DBG0_DEFAULT 0x00000000 -#define ixSQ_WAVE_IB_DBG1_DEFAULT 0x00000000 -#define ixSQ_WAVE_FLUSH_IB_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP0_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP1_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP2_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP3_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP4_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP5_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP6_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP7_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP8_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP9_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP10_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP11_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP12_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP13_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP14_DEFAULT 0x00000000 -#define ixSQ_WAVE_TTMP15_DEFAULT 0x00000000 -#define ixSQ_WAVE_M0_DEFAULT 0x00000000 -#define ixSQ_WAVE_EXEC_LO_DEFAULT 0x00000000 -#define ixSQ_WAVE_EXEC_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_AUTO_CTXID_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_AUTO_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_AUTO_LO_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_CMN_CTXID_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_CMN_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_WAVE_CTXID_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_WAVE_HI_DEFAULT 0x00000000 -#define ixSQ_INTERRUPT_WORD_WAVE_LO_DEFAULT 0x00000000 - - - - - - - - -// addressBlock: didtind -#define ixDIDT_SQ_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_SQ_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_SQ_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_SQ_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_SQ_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_SQ_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_SQ_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_SQ_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_SQ_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_SQ_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_SQ_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_SQ_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_SQ_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_SQ_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_SQ_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_SQ_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_DELAY_2_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_STALL_DELAY_3_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_DB_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_DB_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_DB_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_DB_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_DB_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_DB_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_DB_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DB_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DB_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DB_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DB_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_DB_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_DB_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_DB_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DB_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DB_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DB_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DB_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_TD_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_TD_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_TD_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_TD_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_TD_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_TD_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_TD_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TD_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TD_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TD_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TD_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_TD_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_TD_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_TD_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TD_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TD_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TD_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TD_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_DELAY_2_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_STALL_DELAY_3_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_TD_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_TCP_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_TCP_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_TCP_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_TCP_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_TCP_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_TCP_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_TCP_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TCP_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TCP_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TCP_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TCP_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_TCP_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_TCP_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_TCP_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_TCP_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_TCP_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_TCP_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_TCP_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_DELAY_2_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_STALL_DELAY_3_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_DBR_CTRL0_DEFAULT 0x0000ff00 -#define ixDIDT_DBR_CTRL1_DEFAULT 0x00ff00ff -#define ixDIDT_DBR_CTRL2_DEFAULT 0x18800004 -#define ixDIDT_DBR_STALL_CTRL_DEFAULT 0x00fff000 -#define ixDIDT_DBR_TUNING_CTRL_DEFAULT 0x00010004 -#define ixDIDT_DBR_STALL_AUTO_RELEASE_CTRL_DEFAULT 0x00ffffff -#define ixDIDT_DBR_CTRL3_DEFAULT 0x00038000 -#define ixDIDT_DBR_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DBR_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DBR_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DBR_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DBR_WEIGHT0_3_DEFAULT 0x00000000 -#define ixDIDT_DBR_WEIGHT4_7_DEFAULT 0x00000000 -#define ixDIDT_DBR_WEIGHT8_11_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_CTRL_DEFAULT 0x00001c00 -#define ixDIDT_DBR_EDC_THRESHOLD_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_STALL_PATTERN_1_2_DEFAULT 0x01010001 -#define ixDIDT_DBR_EDC_STALL_PATTERN_3_4_DEFAULT 0x11110421 -#define ixDIDT_DBR_EDC_STALL_PATTERN_5_6_DEFAULT 0x25291249 -#define ixDIDT_DBR_EDC_STALL_PATTERN_7_DEFAULT 0x00002aaa -#define ixDIDT_DBR_EDC_STATUS_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_STALL_DELAY_1_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_OVERFLOW_DEFAULT 0x00000000 -#define ixDIDT_DBR_EDC_ROLLING_POWER_DELTA_DEFAULT 0x00000000 -#define ixDIDT_SQ_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_DB_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_TD_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_TCP_STALL_EVENT_COUNTER_DEFAULT 0x00000000 -#define ixDIDT_DBR_STALL_EVENT_COUNTER_DEFAULT 0x00000000 - - - - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h deleted file mode 100644 index ab0a25eba483..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/GC/gc_9_1_sh_mask.h +++ /dev/null @@ -1,31191 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _gc_9_1_SH_MASK_HEADER -#define _gc_9_1_SH_MASK_HEADER - - -// addressBlock: gc_grbmdec -//GRBM_CNTL -#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 -#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f -#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL -#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L -//GRBM_SKEW_CNTL -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 -#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 -#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL -#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L -//GRBM_STATUS2 -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd -#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe -#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf -#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 -#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 -#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 -#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 -#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 -#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 -#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 -#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a -#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c -#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d -#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e -#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f -#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL -#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L -#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L -#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L -#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L -#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L -#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L -#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L -#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L -#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L -#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L -#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L -#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L -#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L -#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L -#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L -#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L -#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L -#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L -#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L -#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L -#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L -#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L -//GRBM_PWR_CNTL -#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 -#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 -#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 -#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 -#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe -#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf -#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L -#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL -#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L -#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L -#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L -#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L -//GRBM_STATUS -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 -#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 -#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 -#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc -#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd -#define GRBM_STATUS__TA_BUSY__SHIFT 0xe -#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf -#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 -#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 -#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 -#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 -#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 -#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 -#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 -#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 -#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 -#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 -#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a -#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c -#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d -#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e -#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f -#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL -#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L -#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L -#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L -#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L -#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L -#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L -#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L -#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L -#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L -#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L -#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L -#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L -#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L -#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L -#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L -#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L -#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L -#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L -#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L -#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L -#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L -#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L -#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L -//GRBM_STATUS_SE0 -#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L -//GRBM_STATUS_SE1 -#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L -//GRBM_SOFT_RESET -#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 -#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 -#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 -#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 -#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 -#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 -#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 -#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 -#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 -#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L -#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L -#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L -#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L -#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L -#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L -//GRBM_CGTT_CLK_CNTL -#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL -#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -//GRBM_GFX_CLKEN_CNTL -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 -#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL -#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L -//GRBM_WAIT_IDLE_CLOCKS -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 -#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL -//GRBM_STATUS_SE2 -#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L -//GRBM_STATUS_SE3 -#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 -#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 -#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 -#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 -#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 -#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 -#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 -#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a -#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b -#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d -#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e -#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f -#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L -#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L -#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L -#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L -#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L -#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L -#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L -#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L -#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L -#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L -#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L -#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L -//GRBM_READ_ERROR -#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 -#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 -#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 -#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f -#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL -#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L -#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L -#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L -//GRBM_READ_ERROR2 -#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 -#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f -#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L -#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L -#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L -#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L -//GRBM_INT_CNTL -#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 -#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L -#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L -//GRBM_TRAP_OP -#define GRBM_TRAP_OP__RW__SHIFT 0x0 -#define GRBM_TRAP_OP__RW_MASK 0x00000001L -//GRBM_TRAP_ADDR -#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 -#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL -//GRBM_TRAP_ADDR_MSK -#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 -#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL -//GRBM_TRAP_WD -#define GRBM_TRAP_WD__DATA__SHIFT 0x0 -#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL -//GRBM_TRAP_WD_MSK -#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 -#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL -//GRBM_DSM_BYPASS -#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 -#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 -#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L -#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L -//GRBM_WRITE_ERROR -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 -#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 -#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 -#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc -#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd -#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 -#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 -#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L -#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L -#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL -#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L -#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L -#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L -#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L -#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L -#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L -//GRBM_IOV_ERROR -#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 -#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 -#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a -#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b -#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f -#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL -#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L -#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L -#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L -#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L -//GRBM_CHIP_REVISION -#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 -#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL -//GRBM_GFX_CNTL -#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 -#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 -#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 -#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 -#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L -#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL -#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L -#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L -//GRBM_RSMU_CFG -#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 -#define GRBM_RSMU_CFG__QOS__SHIFT 0xc -#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 -#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL -#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L -#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L -//GRBM_IH_CREDIT -#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 -#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L -//GRBM_PWR_CNTL2 -#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 -#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 -#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L -#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L -//GRBM_UTCL2_INVAL_RANGE_START -#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 -#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL -//GRBM_UTCL2_INVAL_RANGE_END -#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 -#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL -//GRBM_RSMU_READ_ERROR -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L -#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L -//GRBM_CHICKEN_BITS -#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 -#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L -//GRBM_NOWHERE -#define GRBM_NOWHERE__DATA__SHIFT 0x0 -#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG0 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 -#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG1 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 -#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG2 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 -#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG3 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 -#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG4 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 -#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG5 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 -#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG6 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 -#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL -//GRBM_SCRATCH_REG7 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 -#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL - - -// addressBlock: gc_cpdec -//CP_CPC_STATUS -#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 -#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 -#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 -#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 -#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 -#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 -#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 -#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 -#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb -#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc -#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd -#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe -#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d -#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e -#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f -#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L -#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L -#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L -#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L -#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L -#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L -#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L -#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L -#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L -#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L -#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L -#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L -#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L -#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L -#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L -#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L -//CP_CPC_BUSY_STAT -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d -#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L -#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L -#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L -#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L -#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L -#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L -#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L -#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L -#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L -#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L -#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L -#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L -#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L -#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L -#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L -#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L -#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L -#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L -#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L -#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L -#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L -#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L -#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L -#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L -#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L -//CP_CPC_STALLED_STAT1 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 -#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 -#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L -#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L -#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L -#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L -#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L -#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L -#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L -#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L -#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L -//CP_CPF_STATUS -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 -#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 -#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 -#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb -#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc -#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd -#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe -#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf -#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 -#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 -#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a -#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c -#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e -#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f -#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L -#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L -#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L -#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L -#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L -#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L -#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L -#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L -#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L -#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L -#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L -#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L -#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L -#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L -#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L -#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L -#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L -#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L -//CP_CPF_BUSY_STAT -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f -#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L -#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L -#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L -#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L -#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L -#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L -#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L -#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L -#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L -#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L -#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L -#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L -#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L -#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L -#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L -#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L -#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L -#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L -#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L -#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L -#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L -#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L -#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L -#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L -//CP_CPF_STALLED_STAT1 -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 -#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 -#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa -#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb -#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L -#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L -#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L -#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L -#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L -#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L -#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L -#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L -#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L -//CP_CPC_GRBM_FREE_COUNT -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 -#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL -//CP_MEC_CNTL -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 -#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c -#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d -#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e -#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f -#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L -#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L -#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L -#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L -#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L -#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L -#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L -#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L -#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L -#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L -#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L -//CP_MEC_ME1_HEADER_DUMP -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 -#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_MEC_ME2_HEADER_DUMP -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 -#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_CPC_SCRATCH_INDEX -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 -#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL -//CP_CPC_SCRATCH_DATA -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 -#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL -//CP_CPF_GRBM_FREE_COUNT -#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 -#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L -//CP_CPC_HALT_HYST_COUNT -#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 -#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL -//CP_PRT_LOD_STATS_CNTL0 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 -#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL -//CP_PRT_LOD_STATS_CNTL1 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 -#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL -//CP_PRT_LOD_STATS_CNTL2 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 -#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL -//CP_PRT_LOD_STATS_CNTL3 -#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2 -#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa -#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12 -#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13 -#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17 -#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c -#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL -#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L -#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L -#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L -#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L -#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L -//CP_CE_COMPARE_COUNT -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 -#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL -//CP_CE_DE_COUNT -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 -#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_DE_CE_COUNT -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 -#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_DE_LAST_INVAL_COUNT -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 -#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL -//CP_DE_DE_COUNT -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 -#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_STALLED_STAT3 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 -#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 -#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L -#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L -#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L -#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L -#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L -#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L -#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L -#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L -#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L -#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L -#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L -#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L -#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L -#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L -//CP_STALLED_STAT1 -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d -#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L -#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L -#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L -#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L -#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L -#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L -#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L -#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L -#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L -//CP_STALLED_STAT2 -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f -#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L -#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L -#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L -#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L -#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L -#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L -#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L -#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L -#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L -#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L -#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L -#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L -#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L -#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L -#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L -#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L -#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L -#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L -#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L -#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L -#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L -#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L -#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L -#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L -//CP_BUSY_STAT -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 -#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 -#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 -#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 -#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf -#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 -#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 -#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 -#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 -#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 -#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 -#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L -#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L -#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L -#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L -#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L -#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L -#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L -#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L -#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L -#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L -#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L -#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L -#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L -#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L -#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L -#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L -//CP_STAT -#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 -#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa -#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb -#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc -#define CP_STAT__DC_BUSY__SHIFT 0xd -#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe -#define CP_STAT__PFP_BUSY__SHIFT 0xf -#define CP_STAT__MEQ_BUSY__SHIFT 0x10 -#define CP_STAT__ME_BUSY__SHIFT 0x11 -#define CP_STAT__QUERY_BUSY__SHIFT 0x12 -#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 -#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 -#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 -#define CP_STAT__DMA_BUSY__SHIFT 0x16 -#define CP_STAT__RCIU_BUSY__SHIFT 0x17 -#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 -#define CP_STAT__CE_BUSY__SHIFT 0x1a -#define CP_STAT__TCIU_BUSY__SHIFT 0x1b -#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e -#define CP_STAT__CP_BUSY__SHIFT 0x1f -#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L -#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L -#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L -#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L -#define CP_STAT__DC_BUSY_MASK 0x00002000L -#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L -#define CP_STAT__PFP_BUSY_MASK 0x00008000L -#define CP_STAT__MEQ_BUSY_MASK 0x00010000L -#define CP_STAT__ME_BUSY_MASK 0x00020000L -#define CP_STAT__QUERY_BUSY_MASK 0x00040000L -#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L -#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L -#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L -#define CP_STAT__DMA_BUSY_MASK 0x00400000L -#define CP_STAT__RCIU_BUSY_MASK 0x00800000L -#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L -#define CP_STAT__CE_BUSY_MASK 0x04000000L -#define CP_STAT__TCIU_BUSY_MASK 0x08000000L -#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L -#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L -#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L -#define CP_STAT__CP_BUSY_MASK 0x80000000L -//CP_ME_HEADER_DUMP -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 -#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_PFP_HEADER_DUMP -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 -#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_GRBM_FREE_COUNT -#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 -#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL -#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L -#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L -//CP_CE_HEADER_DUMP -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 -#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL -//CP_PFP_INSTR_PNTR -#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_ME_INSTR_PNTR -#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_CE_INSTR_PNTR -#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_MEC1_INSTR_PNTR -#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_MEC2_INSTR_PNTR -#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 -#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL -//CP_CSF_STAT -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 -#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L -//CP_ME_CNTL -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 -#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 -#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 -#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 -#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 -#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 -#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 -#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 -#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 -#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a -#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b -#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c -#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d -#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L -#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L -#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L -#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L -#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L -#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L -#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L -#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L -#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L -#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L -#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L -#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L -#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L -#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L -#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L -//CP_CNTX_STAT -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c -#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL -#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L -#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L -#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L -//CP_ME_PREEMPTION -#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 -#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L -//CP_ROQ_THRESHOLDS -#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 -#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 -#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL -#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L -//CP_MEQ_STQ_THRESHOLD -#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 -#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL -//CP_RB2_RPTR -#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB1_RPTR -#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB0_RPTR -#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB_RPTR -#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 -#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL -//CP_RB_WPTR_DELAY -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c -#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL -#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L -//CP_RB_WPTR_POLL_CNTL -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL -#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//CP_ROQ1_THRESHOLDS -#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 -#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 -#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 -#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 -#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL -#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L -#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L -#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L -//CP_ROQ2_THRESHOLDS -#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 -#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 -#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 -#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 -#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL -#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L -#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L -#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L -//CP_STQ_THRESHOLDS -#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 -#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 -#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 -#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL -#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L -#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L -//CP_QUEUE_THRESHOLDS -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 -#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL -#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L -//CP_MEQ_THRESHOLDS -#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 -#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 -#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL -#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L -//CP_ROQ_AVAIL -#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 -#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 -#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL -#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L -//CP_STQ_AVAIL -#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 -#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL -//CP_ROQ2_AVAIL -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 -#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL -//CP_MEQ_AVAIL -#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 -#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL -//CP_CMD_INDEX -#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 -#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc -#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 -#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL -#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L -#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L -//CP_CMD_DATA -#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 -#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL -//CP_ROQ_RB_STAT -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 -#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL -#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L -//CP_ROQ_IB1_STAT -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 -#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL -#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L -//CP_ROQ_IB2_STAT -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 -#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL -#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L -//CP_STQ_STAT -#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 -#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL -//CP_STQ_WR_STAT -#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 -#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL -//CP_MEQ_STAT -#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 -#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 -#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL -#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L -//CP_CEQ1_AVAIL -#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 -#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL -#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L -//CP_CEQ2_AVAIL -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 -#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL -//CP_CE_ROQ_RB_STAT -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 -#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL -#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L -//CP_CE_ROQ_IB1_STAT -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 -#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL -#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L -//CP_CE_ROQ_IB2_STAT -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 -#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL -#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 -#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L -#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L - - -// addressBlock: gc_padec -//VGT_VTX_VECT_EJECT_REG -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 -#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL -//VGT_DMA_DATA_FIFO_DEPTH -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 -#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL -#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L -//VGT_DMA_REQ_FIFO_DEPTH -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 -#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL -//VGT_DRAW_INIT_FIFO_DEPTH -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 -#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL -//VGT_LAST_COPY_STATE -#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 -#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 -#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L -//VGT_CACHE_INVALIDATION -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 -#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd -#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 -#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d -#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L -#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L -#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L -#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L -#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L -#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L -#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L -#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L -#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L -#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L -#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L -#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L -//VGT_STRMOUT_DELAY -#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 -#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL -#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L -#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L -#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L -#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L -//VGT_FIFO_DEPTHS -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 -#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 -#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL -#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L -#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L -#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L -//VGT_GS_VERTEX_REUSE -#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 -#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL -//VGT_MC_LAT_CNTL -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 -#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL -//IA_CNTL_STATUS -#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 -#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 -#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 -#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 -#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L -#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L -#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L -#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L -#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L -//VGT_CNTL_STATUS -#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 -#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 -#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 -#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 -#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 -#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 -#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 -#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 -#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 -#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa -#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L -#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L -#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L -#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L -#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L -#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L -#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L -#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L -#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L -#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L -#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L -//WD_CNTL_STATUS -#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 -#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 -#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L -#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L -#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L -#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L -//CC_GC_PRIM_CONFIG -#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 -#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L -#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L -//GC_USER_PRIM_CONFIG -#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 -#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L -#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L -//WD_QOS -#define WD_QOS__DRAW_STALL__SHIFT 0x0 -#define WD_QOS__DRAW_STALL_MASK 0x00000001L -//WD_UTCL1_CNTL -#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -//WD_UTCL1_STATUS -#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//IA_UTCL1_CNTL -#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -//IA_UTCL1_STATUS -#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//VGT_SYS_CONFIG -#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 -#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L -#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL -#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L -//VGT_VS_MAX_WAVE_ID -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -//VGT_GS_MAX_WAVE_ID -#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -//GFX_PIPE_CONTROL -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 -#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 -#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL -#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L -#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L -//CC_GC_SHADER_ARRAY_CONFIG -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 -#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L -//GC_USER_SHADER_ARRAY_CONFIG -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 -#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L -//VGT_DMA_PRIMITIVE_TYPE -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 -#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL -//VGT_DMA_CONTROL -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 -#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 -#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 -#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 -#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 -#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL -#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L -#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L -#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L -#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L -#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L -#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L -//VGT_DMA_LS_HS_CONFIG -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 -#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L -//WD_BUF_RESOURCE_1 -#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 -#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 -#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL -#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L -//WD_BUF_RESOURCE_2 -#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 -#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf -#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 -#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL -#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L -#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L -//PA_CL_CNTL_STATUS -#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 -#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 -#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 -#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L -#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L -#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L -//PA_CL_ENHANCE -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 -#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 -#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 -#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 -#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 -#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 -#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb -#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc -#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe -#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c -#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d -#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e -#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f -#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L -#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L -#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L -#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L -#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L -#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L -#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L -#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L -#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L -#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L -#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L -#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L -#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L -#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L -#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L -//PA_SU_CNTL_STATUS -#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f -#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L -//PA_SC_FIFO_DEPTH_CNTL -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 -#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL -//PA_SC_P3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L -//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L -//PA_SC_TRAP_SCREEN_HV_LOCK -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L -//PA_SC_FORCE_EOV_MAX_CNTS -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL -#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L -//PA_SC_BINNER_EVENT_CNTL_0 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L -//PA_SC_BINNER_EVENT_CNTL_1 -#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L -//PA_SC_BINNER_EVENT_CNTL_2 -#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L -//PA_SC_BINNER_EVENT_CNTL_3 -#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 -#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 -#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 -#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 -#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c -#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e -#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L -#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL -#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L -#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L -#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L -#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L -#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L -#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L -#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L -//PA_SC_BINNER_TIMEOUT_COUNTER -#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL -//PA_SC_BINNER_PERF_CNTL_0 -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L -#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L -#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L -//PA_SC_BINNER_PERF_CNTL_1 -#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa -#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L -#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L -//PA_SC_BINNER_PERF_CNTL_2 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL -#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L -//PA_SC_BINNER_PERF_CNTL_3 -#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 -#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL -//PA_SC_FIFO_SIZE -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 -#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL -#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L -#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L -#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L -//PA_SC_IF_FIFO_SIZE -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 -#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL -#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L -#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L -#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L -//PA_SC_PKR_WAVE_TABLE_CNTL -#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 -#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL -//PA_UTCL1_CNTL1 -#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 -#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 -#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 -#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 -#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 -#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 -#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L -#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L -#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L -#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//PA_UTCL1_CNTL2 -#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 -#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 -#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb -#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd -#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 -#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 -#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b -#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL -#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L -#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L -#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L -#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L -#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L -#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L -//PA_SIDEBAND_REQUEST_DELAYS -#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 -#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 -#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL -#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L -//PA_SC_ENHANCE -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b -#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c -#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d -#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L -#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L -#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L -#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L -#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L -#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L -#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L -#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L -#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L -#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L -#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L -#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L -#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L -#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L -#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L -#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L -#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L -#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L -#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L -//PA_SC_ENHANCE_1 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 -#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 -#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 -#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 -#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 -#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 -#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 -#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa -#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb -#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd -#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe -#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf -#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 -#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 -#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 -#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 -#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 -#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 -#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17 -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L -#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L -#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L -#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L -#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L -#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L -#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L -#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L -#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L -#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L -#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L -#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L -#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L -#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L -#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L -#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L -#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L -#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L -#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L -//PA_SC_DSM_CNTL -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L -#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L -//PA_SC_TILE_STEERING_CREST_OVERRIDE -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L -#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L - - -// addressBlock: gc_sqdec -//SQ_CONFIG -#define SQ_CONFIG__UNUSED__SHIFT 0x0 -#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 -#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 -#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 -#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c -#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d -#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e -#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f -#define SQ_CONFIG__UNUSED_MASK 0x0000007FL -#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L -#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L -#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L -#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L -#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L -#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L -#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L -#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L -#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L -#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L -#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L -#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L -#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L -#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L -#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L -//SQC_CONFIG -#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 -#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 -#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 -#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 -#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 -#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 -#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 -#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa -#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb -#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc -#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe -#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf -#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 -#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 -#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a -#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L -#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL -#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L -#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L -#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L -#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L -#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L -#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L -#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L -#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L -#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L -#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L -#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L -#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L -#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L -//LDS_CONFIG -#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 -#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L -//SQ_RANDOM_WAVE_PRI -#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 -#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 -#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa -#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL -#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L -#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L -//SQ_REG_CREDITS -#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 -#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 -#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c -#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d -#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e -#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f -#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL -#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L -#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L -#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L -#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L -#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L -//SQ_FIFO_SIZES -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 -#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL -#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L -#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L -#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L -//SQ_DSM_CNTL -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a -#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L -#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L -#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L -#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L -#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L -#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L -#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L -#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L -#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L -//SQ_DSM_CNTL2 -#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe -#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 -#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a -#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L -#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L -#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L -//SQ_RUNTIME_CONFIG -#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 -#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L -//SH_MEM_BASES -#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 -#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 -#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL -#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L -//SH_MEM_CONFIG -#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 -#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 -#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc -#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd -#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L -#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L -#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L -#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L -//CC_GC_SHADER_RATE_CONFIG -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 -#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L -#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L -#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L -//GC_USER_SHADER_RATE_CONFIG -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 -#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L -#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L -#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L -//SQ_INTERRUPT_AUTO_MASK -#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 -#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL -//SQ_INTERRUPT_MSG_CTRL -#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 -#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L -//SQ_UTCL1_CNTL1 -#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 -#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 -#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L -#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L -#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//SQ_UTCL1_CNTL2 -#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 -#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 -#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c -#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L -#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L -//SQ_UTCL1_STATUS -#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 -#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 -#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L -#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L -//SQ_SHADER_TBA_LO -#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 -#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL -//SQ_SHADER_TBA_HI -#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 -#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL -//SQ_SHADER_TMA_LO -#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 -#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL -//SQ_SHADER_TMA_HI -#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 -#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL -//SQC_DSM_CNTL -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -//SQC_DSM_CNTLA -#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 -#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a -#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L -#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L -//SQC_DSM_CNTLB -#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 -#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a -#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L -#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L -//SQC_DSM_CNTL2 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 -#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//SQC_DSM_CNTL2A -#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a -#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -//SQC_DSM_CNTL2B -#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a -#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -//SQC_EDC_FUE_CNTL -#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 -#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 -#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL -#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L -//SQC_EDC_CNT2 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe -#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 -#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12 -#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14 -#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16 -#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L -#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L -#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L -#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L -#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L -//SQC_EDC_CNT3 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe -#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 -#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12 -#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14 -#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16 -#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L -#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L -#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L -#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L -//SQ_REG_TIMESTAMP -#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 -#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL -//SQ_CMD_TIMESTAMP -#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 -#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL -//SQ_IND_INDEX -#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 -#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 -#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 -#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc -#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd -#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe -#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf -#define SQ_IND_INDEX__INDEX__SHIFT 0x10 -#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL -#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L -#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L -#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L -#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L -#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L -#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L -#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L -//SQ_IND_DATA -#define SQ_IND_DATA__DATA__SHIFT 0x0 -#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL -//SQ_CMD -#define SQ_CMD__CMD__SHIFT 0x0 -#define SQ_CMD__MODE__SHIFT 0x4 -#define SQ_CMD__CHECK_VMID__SHIFT 0x7 -#define SQ_CMD__DATA__SHIFT 0x8 -#define SQ_CMD__WAVE_ID__SHIFT 0x10 -#define SQ_CMD__SIMD_ID__SHIFT 0x14 -#define SQ_CMD__QUEUE_ID__SHIFT 0x18 -#define SQ_CMD__VM_ID__SHIFT 0x1c -#define SQ_CMD__CMD_MASK 0x00000007L -#define SQ_CMD__MODE_MASK 0x00000070L -#define SQ_CMD__CHECK_VMID_MASK 0x00000080L -#define SQ_CMD__DATA_MASK 0x00000F00L -#define SQ_CMD__WAVE_ID_MASK 0x000F0000L -#define SQ_CMD__SIMD_ID_MASK 0x00300000L -#define SQ_CMD__QUEUE_ID_MASK 0x07000000L -#define SQ_CMD__VM_ID_MASK 0xF0000000L -//SQ_TIME_HI -#define SQ_TIME_HI__TIME__SHIFT 0x0 -#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL -//SQ_TIME_LO -#define SQ_TIME_LO__TIME__SHIFT 0x0 -#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL -//SQ_DS_0 -#define SQ_DS_0__OFFSET0__SHIFT 0x0 -#define SQ_DS_0__OFFSET1__SHIFT 0x8 -#define SQ_DS_0__GDS__SHIFT 0x10 -#define SQ_DS_0__OP__SHIFT 0x11 -#define SQ_DS_0__ENCODING__SHIFT 0x1a -#define SQ_DS_0__OFFSET0_MASK 0x000000FFL -#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L -#define SQ_DS_0__GDS_MASK 0x00010000L -#define SQ_DS_0__OP_MASK 0x01FE0000L -#define SQ_DS_0__ENCODING_MASK 0xFC000000L -//SQ_DS_1 -#define SQ_DS_1__ADDR__SHIFT 0x0 -#define SQ_DS_1__DATA0__SHIFT 0x8 -#define SQ_DS_1__DATA1__SHIFT 0x10 -#define SQ_DS_1__VDST__SHIFT 0x18 -#define SQ_DS_1__ADDR_MASK 0x000000FFL -#define SQ_DS_1__DATA0_MASK 0x0000FF00L -#define SQ_DS_1__DATA1_MASK 0x00FF0000L -#define SQ_DS_1__VDST_MASK 0xFF000000L -//SQ_EXP_0 -#define SQ_EXP_0__EN__SHIFT 0x0 -#define SQ_EXP_0__TGT__SHIFT 0x4 -#define SQ_EXP_0__COMPR__SHIFT 0xa -#define SQ_EXP_0__DONE__SHIFT 0xb -#define SQ_EXP_0__VM__SHIFT 0xc -#define SQ_EXP_0__ENCODING__SHIFT 0x1a -#define SQ_EXP_0__EN_MASK 0x0000000FL -#define SQ_EXP_0__TGT_MASK 0x000003F0L -#define SQ_EXP_0__COMPR_MASK 0x00000400L -#define SQ_EXP_0__DONE_MASK 0x00000800L -#define SQ_EXP_0__VM_MASK 0x00001000L -#define SQ_EXP_0__ENCODING_MASK 0xFC000000L -//SQ_EXP_1 -#define SQ_EXP_1__VSRC0__SHIFT 0x0 -#define SQ_EXP_1__VSRC1__SHIFT 0x8 -#define SQ_EXP_1__VSRC2__SHIFT 0x10 -#define SQ_EXP_1__VSRC3__SHIFT 0x18 -#define SQ_EXP_1__VSRC0_MASK 0x000000FFL -#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L -#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L -#define SQ_EXP_1__VSRC3_MASK 0xFF000000L -//SQ_FLAT_0 -#define SQ_FLAT_0__OFFSET__SHIFT 0x0 -#define SQ_FLAT_0__LDS__SHIFT 0xd -#define SQ_FLAT_0__SEG__SHIFT 0xe -#define SQ_FLAT_0__GLC__SHIFT 0x10 -#define SQ_FLAT_0__SLC__SHIFT 0x11 -#define SQ_FLAT_0__OP__SHIFT 0x12 -#define SQ_FLAT_0__ENCODING__SHIFT 0x1a -#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL -#define SQ_FLAT_0__LDS_MASK 0x00002000L -#define SQ_FLAT_0__SEG_MASK 0x0000C000L -#define SQ_FLAT_0__GLC_MASK 0x00010000L -#define SQ_FLAT_0__SLC_MASK 0x00020000L -#define SQ_FLAT_0__OP_MASK 0x01FC0000L -#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L -//SQ_FLAT_1 -#define SQ_FLAT_1__ADDR__SHIFT 0x0 -#define SQ_FLAT_1__DATA__SHIFT 0x8 -#define SQ_FLAT_1__SADDR__SHIFT 0x10 -#define SQ_FLAT_1__NV__SHIFT 0x17 -#define SQ_FLAT_1__VDST__SHIFT 0x18 -#define SQ_FLAT_1__ADDR_MASK 0x000000FFL -#define SQ_FLAT_1__DATA_MASK 0x0000FF00L -#define SQ_FLAT_1__SADDR_MASK 0x007F0000L -#define SQ_FLAT_1__NV_MASK 0x00800000L -#define SQ_FLAT_1__VDST_MASK 0xFF000000L -//SQ_GLBL_0 -#define SQ_GLBL_0__OFFSET__SHIFT 0x0 -#define SQ_GLBL_0__LDS__SHIFT 0xd -#define SQ_GLBL_0__SEG__SHIFT 0xe -#define SQ_GLBL_0__GLC__SHIFT 0x10 -#define SQ_GLBL_0__SLC__SHIFT 0x11 -#define SQ_GLBL_0__OP__SHIFT 0x12 -#define SQ_GLBL_0__ENCODING__SHIFT 0x1a -#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL -#define SQ_GLBL_0__LDS_MASK 0x00002000L -#define SQ_GLBL_0__SEG_MASK 0x0000C000L -#define SQ_GLBL_0__GLC_MASK 0x00010000L -#define SQ_GLBL_0__SLC_MASK 0x00020000L -#define SQ_GLBL_0__OP_MASK 0x01FC0000L -#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L -//SQ_GLBL_1 -#define SQ_GLBL_1__ADDR__SHIFT 0x0 -#define SQ_GLBL_1__DATA__SHIFT 0x8 -#define SQ_GLBL_1__SADDR__SHIFT 0x10 -#define SQ_GLBL_1__NV__SHIFT 0x17 -#define SQ_GLBL_1__VDST__SHIFT 0x18 -#define SQ_GLBL_1__ADDR_MASK 0x000000FFL -#define SQ_GLBL_1__DATA_MASK 0x0000FF00L -#define SQ_GLBL_1__SADDR_MASK 0x007F0000L -#define SQ_GLBL_1__NV_MASK 0x00800000L -#define SQ_GLBL_1__VDST_MASK 0xFF000000L -//SQ_INST -#define SQ_INST__ENCODING__SHIFT 0x0 -#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL -//SQ_MIMG_0 -#define SQ_MIMG_0__OPM__SHIFT 0x0 -#define SQ_MIMG_0__DMASK__SHIFT 0x8 -#define SQ_MIMG_0__UNORM__SHIFT 0xc -#define SQ_MIMG_0__GLC__SHIFT 0xd -#define SQ_MIMG_0__DA__SHIFT 0xe -#define SQ_MIMG_0__A16__SHIFT 0xf -#define SQ_MIMG_0__TFE__SHIFT 0x10 -#define SQ_MIMG_0__LWE__SHIFT 0x11 -#define SQ_MIMG_0__OP__SHIFT 0x12 -#define SQ_MIMG_0__SLC__SHIFT 0x19 -#define SQ_MIMG_0__ENCODING__SHIFT 0x1a -#define SQ_MIMG_0__OPM_MASK 0x00000001L -#define SQ_MIMG_0__DMASK_MASK 0x00000F00L -#define SQ_MIMG_0__UNORM_MASK 0x00001000L -#define SQ_MIMG_0__GLC_MASK 0x00002000L -#define SQ_MIMG_0__DA_MASK 0x00004000L -#define SQ_MIMG_0__A16_MASK 0x00008000L -#define SQ_MIMG_0__TFE_MASK 0x00010000L -#define SQ_MIMG_0__LWE_MASK 0x00020000L -#define SQ_MIMG_0__OP_MASK 0x01FC0000L -#define SQ_MIMG_0__SLC_MASK 0x02000000L -#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L -//SQ_MIMG_1 -#define SQ_MIMG_1__VADDR__SHIFT 0x0 -#define SQ_MIMG_1__VDATA__SHIFT 0x8 -#define SQ_MIMG_1__SRSRC__SHIFT 0x10 -#define SQ_MIMG_1__SSAMP__SHIFT 0x15 -#define SQ_MIMG_1__D16__SHIFT 0x1f -#define SQ_MIMG_1__VADDR_MASK 0x000000FFL -#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L -#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L -#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L -#define SQ_MIMG_1__D16_MASK 0x80000000L -//SQ_MTBUF_0 -#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 -#define SQ_MTBUF_0__OFFEN__SHIFT 0xc -#define SQ_MTBUF_0__IDXEN__SHIFT 0xd -#define SQ_MTBUF_0__GLC__SHIFT 0xe -#define SQ_MTBUF_0__OP__SHIFT 0xf -#define SQ_MTBUF_0__DFMT__SHIFT 0x13 -#define SQ_MTBUF_0__NFMT__SHIFT 0x17 -#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a -#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL -#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MTBUF_0__GLC_MASK 0x00004000L -#define SQ_MTBUF_0__OP_MASK 0x00078000L -#define SQ_MTBUF_0__DFMT_MASK 0x00780000L -#define SQ_MTBUF_0__NFMT_MASK 0x03800000L -#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L -//SQ_MTBUF_1 -#define SQ_MTBUF_1__VADDR__SHIFT 0x0 -#define SQ_MTBUF_1__VDATA__SHIFT 0x8 -#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 -#define SQ_MTBUF_1__SLC__SHIFT 0x16 -#define SQ_MTBUF_1__TFE__SHIFT 0x17 -#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 -#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL -#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L -#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L -#define SQ_MTBUF_1__SLC_MASK 0x00400000L -#define SQ_MTBUF_1__TFE_MASK 0x00800000L -#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L -//SQ_MUBUF_0 -#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 -#define SQ_MUBUF_0__OFFEN__SHIFT 0xc -#define SQ_MUBUF_0__IDXEN__SHIFT 0xd -#define SQ_MUBUF_0__GLC__SHIFT 0xe -#define SQ_MUBUF_0__LDS__SHIFT 0x10 -#define SQ_MUBUF_0__SLC__SHIFT 0x11 -#define SQ_MUBUF_0__OP__SHIFT 0x12 -#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a -#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL -#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L -#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L -#define SQ_MUBUF_0__GLC_MASK 0x00004000L -#define SQ_MUBUF_0__LDS_MASK 0x00010000L -#define SQ_MUBUF_0__SLC_MASK 0x00020000L -#define SQ_MUBUF_0__OP_MASK 0x01FC0000L -#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L -//SQ_MUBUF_1 -#define SQ_MUBUF_1__VADDR__SHIFT 0x0 -#define SQ_MUBUF_1__VDATA__SHIFT 0x8 -#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 -#define SQ_MUBUF_1__TFE__SHIFT 0x17 -#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 -#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL -#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L -#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L -#define SQ_MUBUF_1__TFE_MASK 0x00800000L -#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L -//SQ_SCRATCH_0 -#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 -#define SQ_SCRATCH_0__LDS__SHIFT 0xd -#define SQ_SCRATCH_0__SEG__SHIFT 0xe -#define SQ_SCRATCH_0__GLC__SHIFT 0x10 -#define SQ_SCRATCH_0__SLC__SHIFT 0x11 -#define SQ_SCRATCH_0__OP__SHIFT 0x12 -#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a -#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL -#define SQ_SCRATCH_0__LDS_MASK 0x00002000L -#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L -#define SQ_SCRATCH_0__GLC_MASK 0x00010000L -#define SQ_SCRATCH_0__SLC_MASK 0x00020000L -#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L -#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L -//SQ_SCRATCH_1 -#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 -#define SQ_SCRATCH_1__DATA__SHIFT 0x8 -#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 -#define SQ_SCRATCH_1__NV__SHIFT 0x17 -#define SQ_SCRATCH_1__VDST__SHIFT 0x18 -#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL -#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L -#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L -#define SQ_SCRATCH_1__NV_MASK 0x00800000L -#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L -//SQ_SMEM_0 -#define SQ_SMEM_0__SBASE__SHIFT 0x0 -#define SQ_SMEM_0__SDATA__SHIFT 0x6 -#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe -#define SQ_SMEM_0__NV__SHIFT 0xf -#define SQ_SMEM_0__GLC__SHIFT 0x10 -#define SQ_SMEM_0__IMM__SHIFT 0x11 -#define SQ_SMEM_0__OP__SHIFT 0x12 -#define SQ_SMEM_0__ENCODING__SHIFT 0x1a -#define SQ_SMEM_0__SBASE_MASK 0x0000003FL -#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L -#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L -#define SQ_SMEM_0__NV_MASK 0x00008000L -#define SQ_SMEM_0__GLC_MASK 0x00010000L -#define SQ_SMEM_0__IMM_MASK 0x00020000L -#define SQ_SMEM_0__OP_MASK 0x03FC0000L -#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L -//SQ_SMEM_1 -#define SQ_SMEM_1__OFFSET__SHIFT 0x0 -#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 -#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL -#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L -//SQ_SOP1 -#define SQ_SOP1__SSRC0__SHIFT 0x0 -#define SQ_SOP1__OP__SHIFT 0x8 -#define SQ_SOP1__SDST__SHIFT 0x10 -#define SQ_SOP1__ENCODING__SHIFT 0x17 -#define SQ_SOP1__SSRC0_MASK 0x000000FFL -#define SQ_SOP1__OP_MASK 0x0000FF00L -#define SQ_SOP1__SDST_MASK 0x007F0000L -#define SQ_SOP1__ENCODING_MASK 0xFF800000L -//SQ_SOP2 -#define SQ_SOP2__SSRC0__SHIFT 0x0 -#define SQ_SOP2__SSRC1__SHIFT 0x8 -#define SQ_SOP2__SDST__SHIFT 0x10 -#define SQ_SOP2__OP__SHIFT 0x17 -#define SQ_SOP2__ENCODING__SHIFT 0x1e -#define SQ_SOP2__SSRC0_MASK 0x000000FFL -#define SQ_SOP2__SSRC1_MASK 0x0000FF00L -#define SQ_SOP2__SDST_MASK 0x007F0000L -#define SQ_SOP2__OP_MASK 0x3F800000L -#define SQ_SOP2__ENCODING_MASK 0xC0000000L -//SQ_SOPC -#define SQ_SOPC__SSRC0__SHIFT 0x0 -#define SQ_SOPC__SSRC1__SHIFT 0x8 -#define SQ_SOPC__OP__SHIFT 0x10 -#define SQ_SOPC__ENCODING__SHIFT 0x17 -#define SQ_SOPC__SSRC0_MASK 0x000000FFL -#define SQ_SOPC__SSRC1_MASK 0x0000FF00L -#define SQ_SOPC__OP_MASK 0x007F0000L -#define SQ_SOPC__ENCODING_MASK 0xFF800000L -//SQ_SOPK -#define SQ_SOPK__SIMM16__SHIFT 0x0 -#define SQ_SOPK__SDST__SHIFT 0x10 -#define SQ_SOPK__OP__SHIFT 0x17 -#define SQ_SOPK__ENCODING__SHIFT 0x1c -#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL -#define SQ_SOPK__SDST_MASK 0x007F0000L -#define SQ_SOPK__OP_MASK 0x0F800000L -#define SQ_SOPK__ENCODING_MASK 0xF0000000L -//SQ_SOPP -#define SQ_SOPP__SIMM16__SHIFT 0x0 -#define SQ_SOPP__OP__SHIFT 0x10 -#define SQ_SOPP__ENCODING__SHIFT 0x17 -#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL -#define SQ_SOPP__OP_MASK 0x007F0000L -#define SQ_SOPP__ENCODING_MASK 0xFF800000L -//SQ_VINTRP -#define SQ_VINTRP__VSRC__SHIFT 0x0 -#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 -#define SQ_VINTRP__ATTR__SHIFT 0xa -#define SQ_VINTRP__OP__SHIFT 0x10 -#define SQ_VINTRP__VDST__SHIFT 0x12 -#define SQ_VINTRP__ENCODING__SHIFT 0x1a -#define SQ_VINTRP__VSRC_MASK 0x000000FFL -#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L -#define SQ_VINTRP__ATTR_MASK 0x0000FC00L -#define SQ_VINTRP__OP_MASK 0x00030000L -#define SQ_VINTRP__VDST_MASK 0x03FC0000L -#define SQ_VINTRP__ENCODING_MASK 0xFC000000L -//SQ_VOP1 -#define SQ_VOP1__SRC0__SHIFT 0x0 -#define SQ_VOP1__OP__SHIFT 0x9 -#define SQ_VOP1__VDST__SHIFT 0x11 -#define SQ_VOP1__ENCODING__SHIFT 0x19 -#define SQ_VOP1__SRC0_MASK 0x000001FFL -#define SQ_VOP1__OP_MASK 0x0001FE00L -#define SQ_VOP1__VDST_MASK 0x01FE0000L -#define SQ_VOP1__ENCODING_MASK 0xFE000000L -//SQ_VOP2 -#define SQ_VOP2__SRC0__SHIFT 0x0 -#define SQ_VOP2__VSRC1__SHIFT 0x9 -#define SQ_VOP2__VDST__SHIFT 0x11 -#define SQ_VOP2__OP__SHIFT 0x19 -#define SQ_VOP2__ENCODING__SHIFT 0x1f -#define SQ_VOP2__SRC0_MASK 0x000001FFL -#define SQ_VOP2__VSRC1_MASK 0x0001FE00L -#define SQ_VOP2__VDST_MASK 0x01FE0000L -#define SQ_VOP2__OP_MASK 0x7E000000L -#define SQ_VOP2__ENCODING_MASK 0x80000000L -//SQ_VOP3P_0 -#define SQ_VOP3P_0__VDST__SHIFT 0x0 -#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 -#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb -#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe -#define SQ_VOP3P_0__CLAMP__SHIFT 0xf -#define SQ_VOP3P_0__OP__SHIFT 0x10 -#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 -#define SQ_VOP3P_0__VDST_MASK 0x000000FFL -#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L -#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L -#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L -#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L -#define SQ_VOP3P_0__OP_MASK 0x007F0000L -#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L -//SQ_VOP3P_1 -#define SQ_VOP3P_1__SRC0__SHIFT 0x0 -#define SQ_VOP3P_1__SRC1__SHIFT 0x9 -#define SQ_VOP3P_1__SRC2__SHIFT 0x12 -#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b -#define SQ_VOP3P_1__NEG__SHIFT 0x1d -#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL -#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L -#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L -#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L -#define SQ_VOP3P_1__NEG_MASK 0xE0000000L -//SQ_VOP3_0 -#define SQ_VOP3_0__VDST__SHIFT 0x0 -#define SQ_VOP3_0__ABS__SHIFT 0x8 -#define SQ_VOP3_0__OP_SEL__SHIFT 0xb -#define SQ_VOP3_0__CLAMP__SHIFT 0xf -#define SQ_VOP3_0__OP__SHIFT 0x10 -#define SQ_VOP3_0__ENCODING__SHIFT 0x1a -#define SQ_VOP3_0__VDST_MASK 0x000000FFL -#define SQ_VOP3_0__ABS_MASK 0x00000700L -#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L -#define SQ_VOP3_0__CLAMP_MASK 0x00008000L -#define SQ_VOP3_0__OP_MASK 0x03FF0000L -#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L -//SQ_VOP3_0_SDST_ENC -#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 -#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 -#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf -#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 -#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a -#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL -#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L -#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L -#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L -#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L -//SQ_VOP3_1 -#define SQ_VOP3_1__SRC0__SHIFT 0x0 -#define SQ_VOP3_1__SRC1__SHIFT 0x9 -#define SQ_VOP3_1__SRC2__SHIFT 0x12 -#define SQ_VOP3_1__OMOD__SHIFT 0x1b -#define SQ_VOP3_1__NEG__SHIFT 0x1d -#define SQ_VOP3_1__SRC0_MASK 0x000001FFL -#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L -#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L -#define SQ_VOP3_1__OMOD_MASK 0x18000000L -#define SQ_VOP3_1__NEG_MASK 0xE0000000L -//SQ_VOPC -#define SQ_VOPC__SRC0__SHIFT 0x0 -#define SQ_VOPC__VSRC1__SHIFT 0x9 -#define SQ_VOPC__OP__SHIFT 0x11 -#define SQ_VOPC__ENCODING__SHIFT 0x19 -#define SQ_VOPC__SRC0_MASK 0x000001FFL -#define SQ_VOPC__VSRC1_MASK 0x0001FE00L -#define SQ_VOPC__OP_MASK 0x01FE0000L -#define SQ_VOPC__ENCODING_MASK 0xFE000000L -//SQ_VOP_DPP -#define SQ_VOP_DPP__SRC0__SHIFT 0x0 -#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 -#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 -#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 -#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 -#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 -#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 -#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 -#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c -#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL -#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L -#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L -#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L -#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L -#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L -#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L -//SQ_VOP_SDWA -#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 -#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 -#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb -#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd -#define SQ_VOP_SDWA__OMOD__SHIFT 0xe -#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 -#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 -#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 -#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 -#define SQ_VOP_SDWA__S0__SHIFT 0x17 -#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 -#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b -#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c -#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d -#define SQ_VOP_SDWA__S1__SHIFT 0x1f -#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL -#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L -#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L -#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L -#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L -#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L -#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L -#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_SDWA__S0_MASK 0x00800000L -#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L -#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L -#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L -#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L -#define SQ_VOP_SDWA__S1_MASK 0x80000000L -//SQ_VOP_SDWA_SDST_ENC -#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 -#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 -#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 -#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 -#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b -#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c -#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d -#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f -#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL -#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L -#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L -#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L -#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L -#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L -#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L -//SQ_LB_CTR_CTRL -#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 -#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 -#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 -#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L -#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L -#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L -//SQ_LB_DATA0 -#define SQ_LB_DATA0__DATA__SHIFT 0x0 -#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL -//SQ_LB_DATA1 -#define SQ_LB_DATA1__DATA__SHIFT 0x0 -#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL -//SQ_LB_DATA2 -#define SQ_LB_DATA2__DATA__SHIFT 0x0 -#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL -//SQ_LB_DATA3 -#define SQ_LB_DATA3__DATA__SHIFT 0x0 -#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL -//SQ_LB_CTR_SEL -#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 -#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 -#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 -#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc -#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL -#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L -#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L -#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L -//SQ_LB_CTR0_CU -#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L -//SQ_LB_CTR1_CU -#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L -//SQ_LB_CTR2_CU -#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L -//SQ_LB_CTR3_CU -#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 -#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 -#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL -#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L -//SQC_EDC_CNT -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L -#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L -#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L -#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L -#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L -#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L -#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L -#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L -#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L -//SQ_EDC_SEC_CNT -#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 -#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 -#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 -#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL -#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L -#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L -//SQ_EDC_DED_CNT -#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 -#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 -#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 -#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL -#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L -#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L -//SQ_EDC_INFO -#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 -#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 -#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 -#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 -#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL -#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L -#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L -#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L -//SQ_EDC_CNT -#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 -#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 -#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 -#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 -#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 -#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa -#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc -#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe -#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 -#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 -#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 -#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 -#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 -#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a -#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L -#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL -#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L -#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L -#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L -#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L -#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L -#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L -#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L -#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L -#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L -#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L -#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L -#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L -//SQ_EDC_FUE_CNTL -#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 -#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 -#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL -#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_CMN -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L -//SQ_THREAD_TRACE_WORD_EVENT -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L -#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L -#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L -#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L -//SQ_THREAD_TRACE_WORD_INST -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb -#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L -#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L -#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L -#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L -//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_ISSUE -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a -#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L -#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L -//SQ_THREAD_TRACE_WORD_MISC -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd -#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L -#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L -#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L -//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L -#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L -//SQ_THREAD_TRACE_WORD_REG_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L -#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_REG_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L -#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL -//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_WORD_WAVE -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL -#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L -#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L -#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L -#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L -#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L -//SQ_THREAD_TRACE_WORD_WAVE_START -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d -#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL -#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L -#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L -#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L -#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L -#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L -//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL -//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL -//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L -#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L -//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL -//SQ_WREXEC_EXEC_HI -#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a -#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b -#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c -#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f -#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL -#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L -#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L -#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L -#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L -//SQ_WREXEC_EXEC_LO -#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 -#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL -//SQ_BUF_RSRC_WORD0 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL -//SQ_BUF_RSRC_WORD1 -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f -#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL -#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L -#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L -#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L -//SQ_BUF_RSRC_WORD2 -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL -//SQ_BUF_RSRC_WORD3 -#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 -#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf -#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 -#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 -#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b -#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e -#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L -#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L -#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L -#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L -#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L -#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L -#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L -#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L -#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L -#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L -//SQ_IMG_RSRC_WORD0 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL -//SQ_IMG_RSRC_WORD1 -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a -#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e -#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f -#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL -#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L -#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L -#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L -#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L -#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L -//SQ_IMG_RSRC_WORD2 -#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe -#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL -#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L -#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L -//SQ_IMG_RSRC_WORD3 -#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 -#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 -#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 -#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L -#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L -#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L -#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L -#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L -#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L -#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L -//SQ_IMG_RSRC_WORD4 -#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd -#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d -#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL -#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L -#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L -//SQ_IMG_RSRC_WORD5 -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd -#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 -#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 -#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a -#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b -#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL -#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L -#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L -#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L -#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L -#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L -#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L -//SQ_IMG_RSRC_WORD6 -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c -#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL -#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L -#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L -#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L -#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L -#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L -#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L -#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L -//SQ_IMG_RSRC_WORD7 -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 -#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL -//SQ_IMG_SAMP_WORD0 -#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 -#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c -#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f -#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L -#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L -#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L -#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L -#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L -#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L -#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L -#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L -#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L -#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L -#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L -#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L -#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L -//SQ_IMG_SAMP_WORD1 -#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc -#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 -#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c -#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL -#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L -#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L -#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L -//SQ_IMG_SAMP_WORD2 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 -#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 -#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c -#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL -#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L -#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L -#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L -#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L -#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L -#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L -#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L -#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L -#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L -//SQ_IMG_SAMP_WORD3 -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 -#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL -#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L -#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L -//SQ_FLAT_SCRATCH_WORD0 -#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 -#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL -//SQ_FLAT_SCRATCH_WORD1 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 -#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL -//SQ_M0_GPR_IDX_WORD -#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe -#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf -#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL -#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L -#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L -#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L -#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L -//SQC_ICACHE_UTCL1_CNTL1 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 -#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//SQC_ICACHE_UTCL1_CNTL2 -#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 -#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L -#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//SQC_DCACHE_UTCL1_CNTL1 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 -#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L -#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L -#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//SQC_DCACHE_UTCL1_CNTL2 -#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 -#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L -#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L -#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L -#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//SQC_ICACHE_UTCL1_STATUS -#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -//SQC_DCACHE_UTCL1_STATUS -#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L - - -// addressBlock: gc_shsdec -//SX_DEBUG_1 -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc -#define SX_DEBUG_1__PC_CFG__SHIFT 0xd -#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe -#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L -#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L -#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L -#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L -#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L -#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L -//SPI_PS_MAX_WAVE_ID -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 -#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L -//SPI_START_PHASE -#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 -#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 -#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 -#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L -#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL -#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L -//SPI_GFX_CNTL -#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 -#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L -//SPI_DSM_CNTL -#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 -#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L -//SPI_DSM_CNTL2 -#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 -#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa -#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L -#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L -//SPI_EDC_CNT -#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 -#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L -//SPI_CONFIG_PS_CU_EN -#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 -#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 -#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 -#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L -#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL -#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L -//SPI_WF_LIFETIME_CNTL -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 -#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 -#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL -#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L -//SPI_WF_LIFETIME_LIMIT_0 -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_1 -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_2 -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_3 -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_4 -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_5 -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_6 -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_7 -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_8 -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_LIMIT_9 -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f -#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_0 -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_1 -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_2 -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_3 -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_4 -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_5 -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_6 -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_7 -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_8 -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_9 -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_10 -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_11 -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_12 -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_13 -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_14 -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_15 -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_16 -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_17 -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_18 -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_19 -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L -//SPI_WF_LIFETIME_STATUS_20 -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f -#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL -#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L -//SPI_LB_CTR_CTRL -#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 -#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 -#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 -#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 -#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L -#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L -#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L -#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L -//SPI_LB_CU_MASK -#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 -#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL -//SPI_LB_DATA_REG -#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 -#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL -//SPI_PG_ENABLE_STATIC_CU_MASK -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 -#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL -//SPI_GDS_CREDITS -#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 -#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 -#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 -#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL -#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L -#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L -//SPI_SX_EXPORT_BUFFER_SIZES -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 -#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL -#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L -//SPI_SX_SCOREBOARD_BUFFER_SIZES -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL -#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L -//SPI_CSQ_WF_ACTIVE_STATUS -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL -//SPI_CSQ_WF_ACTIVE_COUNT_0 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_1 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_2 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_3 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_4 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_5 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_6 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L -//SPI_CSQ_WF_ACTIVE_COUNT_7 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 -#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL -#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L -//SPI_LB_DATA_WAVES -#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 -#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 -#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL -#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L -//SPI_LB_DATA_PERCU_WAVE_HSGS -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL -#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L -//SPI_LB_DATA_PERCU_WAVE_VSPS -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL -#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L -//SPI_LB_DATA_PERCU_WAVE_CS -#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 -#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL -//SPI_P0_TRAP_SCREEN_PSBA_LO -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P0_TRAP_SCREEN_PSBA_HI -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL -//SPI_P0_TRAP_SCREEN_PSMA_LO -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P0_TRAP_SCREEN_PSMA_HI -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL -//SPI_P0_TRAP_SCREEN_GPR_MIN -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 -#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL -#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L -//SPI_P1_TRAP_SCREEN_PSBA_LO -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P1_TRAP_SCREEN_PSBA_HI -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL -//SPI_P1_TRAP_SCREEN_PSMA_LO -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_P1_TRAP_SCREEN_PSMA_HI -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL -//SPI_P1_TRAP_SCREEN_GPR_MIN -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 -#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL -#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L - - -// addressBlock: gc_tpdec -//TD_CNTL -#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 -#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 -#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 -#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 -#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb -#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf -#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 -#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 -#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 -#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 -#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 -#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18 -#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L -#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L -#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L -#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L -#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L -#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L -#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L -#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L -#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L -#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L -#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L -#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L -#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L -//TD_STATUS -#define TD_STATUS__BUSY__SHIFT 0x1f -#define TD_STATUS__BUSY_MASK 0x80000000L -//TD_DSM_CNTL -#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L -//TD_DSM_CNTL2 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 -#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L -//TD_SCRATCH -#define TD_SCRATCH__SCRATCH__SHIFT 0x0 -#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL -//TA_CNTL -#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 -#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 -#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd -#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 -#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 -#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL -#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L -#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L -#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L -#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L -//TA_CNTL_AUX -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 -#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 -#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 -#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 -#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 -#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 -#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa -#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc -#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd -#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe -#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 -#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 -#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 -#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 -#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 -#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 -#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 -#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 -#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 -#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a -#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b -#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c -#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d -#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e -#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L -#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL -#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L -#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L -#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L -#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L -#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L -#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L -#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L -#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L -#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L -#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L -#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L -#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L -#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L -#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L -#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L -#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L -#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L -#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L -#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L -#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L -#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L -#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L -#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L -#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L -//TA_RESERVED_010C -#define TA_RESERVED_010C__Unused__SHIFT 0x0 -#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL -//TA_GRAD_ADJ -#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L -//TA_STATUS -#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc -#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd -#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe -#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 -#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 -#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 -#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 -#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 -#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 -#define TA_STATUS__IN_BUSY__SHIFT 0x18 -#define TA_STATUS__FG_BUSY__SHIFT 0x19 -#define TA_STATUS__LA_BUSY__SHIFT 0x1a -#define TA_STATUS__FL_BUSY__SHIFT 0x1b -#define TA_STATUS__TA_BUSY__SHIFT 0x1c -#define TA_STATUS__FA_BUSY__SHIFT 0x1d -#define TA_STATUS__AL_BUSY__SHIFT 0x1e -#define TA_STATUS__BUSY__SHIFT 0x1f -#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L -#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L -#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L -#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L -#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L -#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L -#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L -#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L -#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L -#define TA_STATUS__IN_BUSY_MASK 0x01000000L -#define TA_STATUS__FG_BUSY_MASK 0x02000000L -#define TA_STATUS__LA_BUSY_MASK 0x04000000L -#define TA_STATUS__FL_BUSY_MASK 0x08000000L -#define TA_STATUS__TA_BUSY_MASK 0x10000000L -#define TA_STATUS__FA_BUSY_MASK 0x20000000L -#define TA_STATUS__AL_BUSY_MASK 0x40000000L -#define TA_STATUS__BUSY_MASK 0x80000000L -//TA_SCRATCH -#define TA_SCRATCH__SCRATCH__SHIFT 0x0 -#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL - - -// addressBlock: gc_gdsdec -//GDS_CONFIG -#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 -#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 -#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 -#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 -#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L -#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L -#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L -#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L -//GDS_CNTL_STATUS -#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 -#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 -#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 -#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 -#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 -#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa -#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb -#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc -#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd -#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe -#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L -#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L -#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L -#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L -#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L -#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L -#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L -#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L -#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L -#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L -#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L -#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L -#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L -#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L -#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L -//GDS_ENHANCE2 -#define GDS_ENHANCE2__MISC__SHIFT 0x0 -#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 -#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL -#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L -//GDS_PROTECTION_FAULT -#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 -#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 -#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 -#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 -#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 -#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa -#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc -#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 -#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L -#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L -#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L -#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L -#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L -#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L -#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L -#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L -//GDS_VM_PROTECTION_FAULT -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 -#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 -#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 -#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 -#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 -#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 -#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 -#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L -#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L -#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L -#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L -#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L -#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L -#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L -#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L -//GDS_EDC_CNT -#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 -#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 -#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 -#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 -#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L -#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL -#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L -//GDS_EDC_GRBM_CNT -#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 -#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 -#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 -#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L -#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL -#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L -//GDS_EDC_OA_DED -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 -#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 -#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 -#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 -#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 -#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 -#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 -#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 -#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 -#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa -#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb -#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc -#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L -#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L -#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L -#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L -#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L -#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L -#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L -#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L -#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L -#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L -#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L -#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L -//GDS_DSM_CNTL -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 -#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 -#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 -#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa -#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd -#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L -#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L -#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L -#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L -#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L -#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L -#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L -#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L -#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L -//GDS_EDC_OA_PHY_CNT -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 -#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 -#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L -#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L -#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L -#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L -//GDS_EDC_OA_PIPE_CNT -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe -#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L -#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L -#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L -//GDS_DSM_CNTL2 -#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf -#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a -#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L -#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L -//GDS_WD_GDS_CSB -#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 -#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd -#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL -#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L - - -// addressBlock: gc_rbdec -//DB_DEBUG -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 -#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 -#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 -#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 -#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 -#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f -#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L -#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L -#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L -#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L -#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L -#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L -#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L -#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L -#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L -#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L -#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L -#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L -#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L -#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L -#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L -#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L -#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L -#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L -#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L -#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L -#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L -#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L -#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L -//DB_DEBUG2 -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 -#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 -#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 -#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf -#define DB_DEBUG2__RESERVED__SHIFT 0x10 -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f -#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L -#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L -#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L -#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L -#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L -#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L -#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L -#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L -#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L -#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L -#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L -#define DB_DEBUG2__RESERVED_MASK 0x00010000L -#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L -#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L -#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L -#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L -#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L -#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L -//DB_DEBUG3 -#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 -#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 -#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 -#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f -#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L -#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L -#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L -#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L -#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L -#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L -#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L -#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L -#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L -#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L -#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L -#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L -#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L -#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L -#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L -#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L -#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L -#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L -#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L -#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L -#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L -#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L -#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L -#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L -#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L -#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L -#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L -#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L -#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L -#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L -#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L -//DB_DEBUG4 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 -#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 -#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 -#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 -#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 -#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa -#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb -#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc -#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd -#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe -#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf -#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 -#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 -#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 -#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 -#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L -#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L -#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L -#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L -#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L -#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L -#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L -#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L -#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L -#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L -#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L -#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L -#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L -#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L -#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L -#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L -#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L -#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L -#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L -#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L -//DB_CREDIT_LIMIT -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 -#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL -#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L -#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L -#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L -//DB_WATERMARKS -#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 -#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 -#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb -#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 -#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e -#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f -#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL -#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L -#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L -#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L -#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L -#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L -#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L -//DB_SUBTILE_CONTROL -#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 -#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 -#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 -#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 -#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 -#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa -#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc -#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe -#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 -#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 -#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L -#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL -#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L -#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L -#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L -#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L -#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L -#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L -#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L -#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L -//DB_FREE_CACHELINES -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 -#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 -#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 -#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL -#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L -#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L -#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L -#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L -//DB_FIFO_DEPTH1 -#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 -#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 -#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa -#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 -#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL -#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L -#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L -#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L -#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L -//DB_FIFO_DEPTH2 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 -#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL -#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L -#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L -#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L -//DB_EXCEPTION_CONTROL -#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 -#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 -#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 -#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L -#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L -#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L -//DB_RING_CONTROL -#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 -#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L -//DB_MEM_ARB_WATERMARKS -#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 -#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 -#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 -#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 -#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L -#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L -#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L -#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L -//DB_RMI_CACHE_POLICY -#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 -#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 -#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 -#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 -#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 -#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa -#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb -#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 -#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 -#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 -#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 -#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 -#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 -#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a -#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b -#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L -#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L -#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L -#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L -#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L -#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L -#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L -#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L -#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L -#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L -#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L -#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L -#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L -#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L -#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L -//DB_DFSM_CONFIG -#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 -#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 -#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 -#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 -#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 -#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L -#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L -#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L -#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L -#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L -//DB_DFSM_WATERMARK -#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 -#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 -#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL -#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L -//DB_DFSM_TILES_IN_FLIGHT -#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 -#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 -#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL -#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L -//DB_DFSM_PRIMS_IN_FLIGHT -#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 -#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 -#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL -#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L -//DB_DFSM_WATCHDOG -#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 -#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL -//DB_DFSM_FLUSH_ENABLE -#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 -#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 -#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c -#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL -#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L -#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L -//DB_DFSM_FLUSH_AUX_EVENT -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L -#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L -//CC_RB_REDUNDANCY -#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc -#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 -#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L -#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L -#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L -//CC_RB_BACKEND_DISABLE -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 -#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L -//GB_ADDR_CONFIG -#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 -#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a -#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e -#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f -#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L -#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L -#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L -#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L -//GB_BACKEND_MAP -#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 -#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL -//GB_GPU_ID -#define GB_GPU_ID__GPU_ID__SHIFT 0x0 -#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL -//CC_RB_DAISY_CHAIN -#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 -#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 -#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 -#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc -#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 -#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 -#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 -#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c -#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL -#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L -#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L -#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L -#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L -#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L -#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L -#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L -//GB_ADDR_CONFIG_READ -#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 -#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 -#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 -#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 -#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a -#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c -#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e -#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f -#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L -#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L -#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L -#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L -#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L -#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L -#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L -#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L -//GB_TILE_MODE0 -#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE1 -#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE2 -#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE3 -#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE4 -#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE5 -#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE6 -#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE7 -#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE8 -#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE9 -#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE10 -#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE11 -#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE12 -#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE13 -#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE14 -#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE15 -#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE16 -#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE17 -#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE18 -#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE19 -#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE20 -#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE21 -#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE22 -#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE23 -#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE24 -#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE25 -#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE26 -#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE27 -#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE28 -#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE29 -#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE30 -#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L -//GB_TILE_MODE31 -#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 -#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 -#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 -#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 -#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL -#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L -#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L -#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L -#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L -//GB_MACROTILE_MODE0 -#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE1 -#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE2 -#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE3 -#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE4 -#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE5 -#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE6 -#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE7 -#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE8 -#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE9 -#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE10 -#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE11 -#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE12 -#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE13 -#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE14 -#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L -//GB_MACROTILE_MODE15 -#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 -#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 -#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 -#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L -#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL -#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L -#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L -//CB_HW_CONTROL -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 -#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f -#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL -#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L -#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L -#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L -#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L -#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L -#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L -#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L -#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L -#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L -#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L -#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L -#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L -//CB_HW_CONTROL_1 -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 -#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a -#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL -#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L -#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L -#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L -#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L -//CB_HW_CONTROL_2 -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 -#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c -#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL -#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L -#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L -#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L -#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L -//CB_HW_CONTROL_3 -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd -#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe -#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf -#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 -#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 -#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a -#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b -#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c -#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L -#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L -#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L -#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L -#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L -#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L -#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L -#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L -#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L -#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L -#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L -#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L -#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L -#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L -#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L -#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L -#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L -#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L -#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L -//CB_HW_MEM_ARBITER_RD -#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 -#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 -#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa -#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 -#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 -#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 -#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a -#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d -#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L -#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL -#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L -#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L -#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L -#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L -#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L -//CB_HW_MEM_ARBITER_WR -#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 -#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 -#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa -#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 -#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 -#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 -#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a -#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d -#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L -#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL -#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L -#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L -#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L -#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L -#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L -//CB_DCC_CONFIG -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L -#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L -#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L -#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L -#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L -#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L -//GC_USER_RB_REDUNDANCY -#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc -#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 -#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L -#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L -#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L -//GC_USER_RB_BACKEND_DISABLE -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 -#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L - - -// addressBlock: gc_ea_gceadec2 -//GCEA_EDC_CNT -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc -#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe -#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 -#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 -#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 -#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 -#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 -#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a -#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L -#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L -#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L -#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L -#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L -#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L -#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L -#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L -#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L -//GCEA_EDC_CNT2 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa -#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc -#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L -#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L -#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L -#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L -#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L -#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L -//GCEA_DSM_CNTL -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L -#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L -//GCEA_DSM_CNTLA -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 -#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 -#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L -#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L -#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L -#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L -#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L -#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L -#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L -#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L -#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L -//GCEA_DSM_CNTLB -//GCEA_DSM_CNTL2 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 -#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L -#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//GCEA_DSM_CNTL2A -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L -//GCEA_DSM_CNTL2B -//GCEA_TCC_XBR_CREDITS -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 -#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 -#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 -#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 -#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL -#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L -#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L -#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L -#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L -#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L -#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L -//GCEA_TCC_XBR_MAXBURST -#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 -#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 -#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 -#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc -#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL -#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L -#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L -#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L -//GCEA_PROBE_CNTL -#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 -#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 -#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL -#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L -//GCEA_PROBE_MAP -#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 -#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 -#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 -#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 -#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 -#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 -#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 -#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 -#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 -#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 -#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa -#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb -#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc -#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd -#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe -#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf -#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 -#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L -#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L -#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L -#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L -#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L -#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L -#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L -#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L -#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L -#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L -#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L -#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L -#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L -#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L -#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L -#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L -#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L -//GCEA_ERR_STATUS -#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 -#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 -#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 -#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 -#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa -#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL -#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L -#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L -#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L -#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L -//GCEA_MISC2 -#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 -#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 -#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L -#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL -#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L -//GCEA_SDP_BACKDOOR_CMDCREDITS0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL -//GCEA_SDP_BACKDOOR_CMDCREDITS1 -#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL -//GCEA_SDP_BACKDOOR_DATACREDITS0 -#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL -//GCEA_SDP_BACKDOOR_DATACREDITS1 -#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL -//GCEA_SDP_BACKDOOR_MISCCREDITS -#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 -#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL -#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L -#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L -//GCEA_SDP_ENABLE -#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 -#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L - - -// addressBlock: gc_rmi_rmidec -//RMI_GENERAL_CNTL -#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 -#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 -#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 -#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 -#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 -#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a -#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b -#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c -#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d -#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e -#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L -#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L -#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L -#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L -#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L -#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L -#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L -//RMI_GENERAL_CNTL1 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 -#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 -#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 -#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa -#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb -#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc -#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL -#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L -#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L -#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L -#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L -#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L -#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L -//RMI_GENERAL_STATUS -#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 -#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 -#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 -#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 -#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 -#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 -#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 -#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 -#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 -#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc -#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd -#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 -#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 -#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 -#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 -#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 -#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d -#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e -#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f -#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L -#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L -#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L -#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L -#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L -#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L -#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L -#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L -#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L -#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L -#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L -#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L -#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L -#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L -#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L -#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L -#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L -#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L -#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L -#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L -//RMI_SUBBLOCK_STATUS0 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 -#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L -#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L -#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L -//RMI_SUBBLOCK_STATUS1 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa -#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL -#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L -#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L -//RMI_SUBBLOCK_STATUS2 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL -#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L -//RMI_SUBBLOCK_STATUS3 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL -#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L -//RMI_XBAR_CONFIG -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 -#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL -#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L -#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L -#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L -//RMI_PROBE_POP_LOGIC_CNTL -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 -#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L -#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L -#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L -#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L -//RMI_UTC_XNACK_N_MISC_CNTL -#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 -#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 -#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc -#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd -#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL -#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L -#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L -#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L -//RMI_DEMUX_CNTL -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 -#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 -#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L -#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L -#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L -//RMI_UTCL1_CNTL1 -#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 -#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 -#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 -#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 -#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 -#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 -#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 -#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b -#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L -#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L -#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L -#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L -#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L -#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//RMI_UTCL1_CNTL2 -#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 -#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa -#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb -#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd -#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 -#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 -#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL -#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L -#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L -#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L -#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L -#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L -#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L -#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L -#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//RMI_UTC_UNIT_CONFIG -//RMI_TCIW_FORMATTER0_CNTL -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c -#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e -#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L -#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L -#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L -#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L -#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L -#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L -//RMI_TCIW_FORMATTER1_CNTL -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c -#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e -#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L -#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L -#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L -#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L -#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L -#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L -//RMI_SCOREBOARD_CNTL -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L -#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L -#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L -#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L -#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L -#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L -//RMI_SCOREBOARD_STATUS0 -#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 -#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 -#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L -#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L -#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L -//RMI_SCOREBOARD_STATUS1 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd -#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L -#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L -#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L -#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L -//RMI_SCOREBOARD_STATUS2 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L -#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L -#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L -#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L -//RMI_XBAR_ARBITER_CONFIG -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L -#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L -//RMI_XBAR_ARBITER_CONFIG_1 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L -#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L -//RMI_CLOCK_CNTRL -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L -#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L -#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L -//RMI_UTCL1_STATUS -#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -//RMI_SPARE -#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 -#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 -#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 -#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 -#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 -#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 -#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 -#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 -#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 -#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 -#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L -#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L -#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L -#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L -#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L -#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L -#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L -#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L -#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L -#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L -//RMI_SPARE_1 -#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 -#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 -#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 -#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 -#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 -#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 -#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 -#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 -#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 -#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 -#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L -#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L -#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L -#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L -#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L -#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L -#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L -#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L -#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L -#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L -//RMI_SPARE_2 -#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 -#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 -#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 -#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 -#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 -#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 -#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 -#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 -#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 -#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc -#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 -#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 -#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L -#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L -#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L -#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L -#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L -#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L -#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L -#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L -#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L -#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L -#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L -#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L - - -// addressBlock: gc_dbgu_gfx_dbgudec -//port_a_addr -#define port_a_addr__Index__SHIFT 0x0 -#define port_a_addr__Reserved__SHIFT 0x8 -#define port_a_addr__ReadEnable__SHIFT 0x1f -#define port_a_addr__Index_MASK 0x000000FFL -#define port_a_addr__Reserved_MASK 0x7FFFFF00L -#define port_a_addr__ReadEnable_MASK 0x80000000L -//port_a_data_lo -#define port_a_data_lo__Data__SHIFT 0x0 -#define port_a_data_lo__Data_MASK 0xFFFFFFFFL -//port_a_data_hi -#define port_a_data_hi__Data__SHIFT 0x0 -#define port_a_data_hi__Data_MASK 0xFFFFFFFFL -//port_b_addr -#define port_b_addr__Index__SHIFT 0x0 -#define port_b_addr__Reserved__SHIFT 0x8 -#define port_b_addr__ReadEnable__SHIFT 0x1f -#define port_b_addr__Index_MASK 0x000000FFL -#define port_b_addr__Reserved_MASK 0x7FFFFF00L -#define port_b_addr__ReadEnable_MASK 0x80000000L -//port_b_data_lo -#define port_b_data_lo__Data__SHIFT 0x0 -#define port_b_data_lo__Data_MASK 0xFFFFFFFFL -//port_b_data_hi -#define port_b_data_hi__Data__SHIFT 0x0 -#define port_b_data_hi__Data_MASK 0xFFFFFFFFL -//port_c_addr -#define port_c_addr__Index__SHIFT 0x0 -#define port_c_addr__Reserved__SHIFT 0x8 -#define port_c_addr__ReadEnable__SHIFT 0x1f -#define port_c_addr__Index_MASK 0x000000FFL -#define port_c_addr__Reserved_MASK 0x7FFFFF00L -#define port_c_addr__ReadEnable_MASK 0x80000000L -//port_c_data_lo -#define port_c_data_lo__Data__SHIFT 0x0 -#define port_c_data_lo__Data_MASK 0xFFFFFFFFL -//port_c_data_hi -#define port_c_data_hi__Data__SHIFT 0x0 -#define port_c_data_hi__Data_MASK 0xFFFFFFFFL -//port_d_addr -#define port_d_addr__Index__SHIFT 0x0 -#define port_d_addr__Reserved__SHIFT 0x8 -#define port_d_addr__ReadEnable__SHIFT 0x1f -#define port_d_addr__Index_MASK 0x000000FFL -#define port_d_addr__Reserved_MASK 0x7FFFFF00L -#define port_d_addr__ReadEnable_MASK 0x80000000L -//port_d_data_lo -#define port_d_data_lo__Data__SHIFT 0x0 -#define port_d_data_lo__Data_MASK 0xFFFFFFFFL -//port_d_data_hi -#define port_d_data_hi__Data__SHIFT 0x0 -#define port_d_data_hi__Data_MASK 0xFFFFFFFFL - - -// addressBlock: gc_utcl2_atcl2dec -//ATC_L2_CNTL -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L -#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L -#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L -#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -//ATC_L2_CNTL2 -#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf -#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L -#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L -#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L -#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L -#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L -//ATC_L2_CACHE_DATA0 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 -#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L -#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L -#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL -#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L -//ATC_L2_CACHE_DATA1 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 -#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL -//ATC_L2_CACHE_DATA2 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 -#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL -//ATC_L2_CNTL3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 -#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L -#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L -//ATC_L2_STATUS -#define ATC_L2_STATUS__BUSY__SHIFT 0x0 -#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 -#define ATC_L2_STATUS__BUSY_MASK 0x00000001L -#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL -//ATC_L2_STATUS2 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 -#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL -#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L -//ATC_L2_MISC_CG -#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 -#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 -#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 -#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L -#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L -#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L -//ATC_L2_MEM_POWER_LS -#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//ATC_L2_CGTT_CLK_CTRL -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: gc_utcl2_vml2pfdec -//VM_L2_CNTL -#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a -#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L -#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L -#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL -#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L -#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L -#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L -#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L -#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L -#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L -#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L -#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L -#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L -#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L -#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L -//VM_L2_CNTL2 -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c -#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L -#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L -#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L -#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L -#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L -#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L -#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L -//VM_L2_CNTL3 -#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f -#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL -#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L -#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L -#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L -#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L -#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L -#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L -#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L -//VM_L2_STATUS -#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 -#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L -#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL -#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L -#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L -#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L -#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L -#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L -//VM_DUMMY_PAGE_FAULT_CNTL -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L -#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL -//VM_DUMMY_PAGE_FAULT_ADDR_LO32 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_DUMMY_PAGE_FAULT_ADDR_HI32 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_PROTECTION_FAULT_CNTL -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f -#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L -#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L -#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L -#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L -#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L -#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L -#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L -#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L -#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L -#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L -//VM_L2_PROTECTION_FAULT_CNTL2 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 -#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL -#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L -//VM_L2_PROTECTION_FAULT_MM_CNTL3 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_MM_CNTL4 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_STATUS -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 -#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 -#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 -#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 -#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 -#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 -#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L -#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL -#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L -#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L -#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L -#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L -#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L -#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L -#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L -#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L -//VM_L2_PROTECTION_FAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL -//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 -#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL -//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 -#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL -//VM_L2_CNTL4 -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c -#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL -#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L -#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L -#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L -#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L -#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L -//VM_L2_MM_GROUP_RT_CLASSES -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L -#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L -//VM_L2_BANK_SELECT_RESERVED_CID -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L -#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L -//VM_L2_BANK_SELECT_RESERVED_CID2 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L -#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L -#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L -//VM_L2_CACHE_PARITY_CNTL -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L -#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L -#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L -//VM_L2_CGTT_CLK_CTRL -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: gc_utcl2_vml2vcdec -//VM_CONTEXT0_CNTL -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT1_CNTL -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT2_CNTL -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT3_CNTL -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT4_CNTL -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT5_CNTL -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT6_CNTL -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT7_CNTL -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT8_CNTL -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT9_CNTL -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT10_CNTL -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT11_CNTL -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT12_CNTL -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT13_CNTL -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT14_CNTL -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXT15_CNTL -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 -#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L -#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L -#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L -#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L -#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L -#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L -#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L -#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L -#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L -#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L -#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L -//VM_CONTEXTS_DISABLE -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L -#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L -//VM_INVALIDATE_ENG0_SEM -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG1_SEM -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG2_SEM -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG3_SEM -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG4_SEM -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG5_SEM -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG6_SEM -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG7_SEM -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG8_SEM -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG9_SEM -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG10_SEM -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG11_SEM -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG12_SEM -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG13_SEM -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG14_SEM -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG15_SEM -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG16_SEM -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG17_SEM -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L -//VM_INVALIDATE_ENG0_REQ -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG1_REQ -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG2_REQ -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG3_REQ -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG4_REQ -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG5_REQ -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG6_REQ -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG7_REQ -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG8_REQ -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG9_REQ -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG10_REQ -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG11_REQ -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG12_REQ -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG13_REQ -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG14_REQ -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG15_REQ -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG16_REQ -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG17_REQ -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 -#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L -#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L -#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L -//VM_INVALIDATE_ENG0_ACK -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG1_ACK -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG2_ACK -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG3_ACK -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG4_ACK -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG5_ACK -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG6_ACK -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG7_ACK -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG8_ACK -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG9_ACK -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG10_ACK -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG11_ACK -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG12_ACK -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG13_ACK -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG14_ACK -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG15_ACK -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG16_ACK -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG17_ACK -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 -#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL -#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L -//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L -#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL -//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 -#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL -//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL -//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL -//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 -#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL - - -// addressBlock: gc_utcl2_vmsharedpfdec -//MC_VM_NB_MMIOBASE -#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 -#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL -//MC_VM_NB_MMIOLIMIT -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 -#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL -//MC_VM_NB_PCI_CTRL -#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 -#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L -//MC_VM_NB_PCI_ARB -#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 -#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L -//MC_VM_NB_TOP_OF_DRAM_SLOT1 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 -#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L -//MC_VM_NB_LOWER_TOP_OF_DRAM2 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L -#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L -//MC_VM_NB_UPPER_TOP_OF_DRAM2 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 -#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL -//MC_VM_FB_OFFSET -#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 -#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL -//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL -//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL -//MC_VM_STEERING -#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 -#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L -//MC_SHARED_VIRT_RESET_REQ -#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L -//MC_MEM_POWER_LS -#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//MC_VM_CACHEABLE_DRAM_ADDRESS_START -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 -#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL -//MC_VM_CACHEABLE_DRAM_ADDRESS_END -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 -#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL -//MC_VM_APT_CNTL -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 -#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L -#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L -//MC_VM_LOCAL_HBM_ADDRESS_START -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL -//MC_VM_LOCAL_HBM_ADDRESS_END -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL -//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 -#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L - - -// addressBlock: gc_utcl2_vmsharedvcdec -//MC_VM_FB_LOCATION_BASE -#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 -#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL -//MC_VM_FB_LOCATION_TOP -#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 -#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL -//MC_VM_AGP_TOP -#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 -#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL -//MC_VM_AGP_BOT -#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 -#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL -//MC_VM_AGP_BASE -#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 -#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL -//MC_VM_SYSTEM_APERTURE_LOW_ADDR -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL -//MC_VM_SYSTEM_APERTURE_HIGH_ADDR -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 -#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL -//MC_VM_MX_L1_TLB_CNTL -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 -#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L -#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L -#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L -#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L -#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L -#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L - - -// addressBlock: gc_ea_gceadec -//GCEA_DRAM_RD_CLI2GRP_MAP0 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_DRAM_RD_CLI2GRP_MAP1 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_DRAM_WR_CLI2GRP_MAP0 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_DRAM_WR_CLI2GRP_MAP1 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_DRAM_RD_GRP2VC_MAP -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//GCEA_DRAM_WR_GRP2VC_MAP -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L -#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L -//GCEA_DRAM_RD_LAZY -#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//GCEA_DRAM_WR_LAZY -#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 -#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 -#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 -#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 -#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L -#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L -#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L -#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L -//GCEA_DRAM_RD_CAM_CNTL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//GCEA_DRAM_WR_CAM_CNTL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L -#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L -#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L -//GCEA_DRAM_PAGE_BURST -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//GCEA_DRAM_RD_PRI_AGE -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_DRAM_WR_PRI_AGE -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_DRAM_RD_PRI_QUEUING -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_WR_PRI_QUEUING -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_RD_PRI_FIXED -#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_WR_PRI_FIXED -#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_DRAM_RD_PRI_URGENCY -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_DRAM_WR_PRI_URGENCY -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_DRAM_RD_PRI_QUANT_PRI1 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_RD_PRI_QUANT_PRI2 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_RD_PRI_QUANT_PRI3 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_WR_PRI_QUANT_PRI1 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_WR_PRI_QUANT_PRI2 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_DRAM_WR_PRI_QUANT_PRI3 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_ADDRNORM_BASE_ADDR0 -#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 -#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 -#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L -#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L -#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L -#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_LIMIT_ADDR0 -#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa -#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L -#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_BASE_ADDR1 -#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 -#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 -#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L -#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L -#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L -#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_LIMIT_ADDR1 -#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa -#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc -#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L -#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L -#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L -//GCEA_ADDRNORM_OFFSET_ADDR1 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L -#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L -//GCEA_ADDRNORM_HOLE_CNTL -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L -#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L -//GCEA_ADDRDEC_BANK_CFG -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL -#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L -#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L -//GCEA_ADDRDEC_MISC_CFG -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L -#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L -#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L -#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L -#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L -#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_PC -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L -//GCEA_ADDRDECDRAM_ADDR_HASH_PC2 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL -//GCEA_ADDRDECDRAM_ADDR_HASH_CS0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL -//GCEA_ADDRDECDRAM_ADDR_HASH_CS1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL -//GCEA_ADDRDECDRAM_HARVEST_ENABLE -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L -#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L -//GCEA_ADDRDEC0_BASE_ADDR_CS0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_CS1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_CS2 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_CS3 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_CS01 -#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_CS23 -#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC0_ADDR_CFG_CS01 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC0_ADDR_CFG_CS23 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC0_ADDR_SEL_CS01 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC0_ADDR_SEL_CS23 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC0_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC0_RM_SEL_CS01 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC0_RM_SEL_CS23 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC0_RM_SEL_SECCS01 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC0_RM_SEL_SECCS23 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_BASE_ADDR_CS0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_CS1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_CS2 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_CS3 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS2 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_BASE_ADDR_SECCS3 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L -#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_CS01 -#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_CS23 -#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_SECCS01 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_MASK_SECCS23 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 -#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL -//GCEA_ADDRDEC1_ADDR_CFG_CS01 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC1_ADDR_CFG_CS23 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L -//GCEA_ADDRDEC1_ADDR_SEL_CS01 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC1_ADDR_SEL_CS23 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L -#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_LO_CS01 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_LO_CS23 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_HI_CS01 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC1_COL_SEL_HI_CS23 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L -#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L -//GCEA_ADDRDEC1_RM_SEL_CS01 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_RM_SEL_CS23 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_RM_SEL_SECCS01 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_ADDRDEC1_RM_SEL_SECCS23 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L -#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L -//GCEA_IO_RD_CLI2GRP_MAP0 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_IO_RD_CLI2GRP_MAP1 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_IO_WR_CLI2GRP_MAP0 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa -#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc -#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe -#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 -#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a -#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c -#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e -#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL -#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L -#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L -//GCEA_IO_WR_CLI2GRP_MAP1 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa -#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc -#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe -#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 -#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a -#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c -#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e -#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL -#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L -#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L -//GCEA_IO_RD_COMBINE_FLUSH -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//GCEA_IO_WR_COMBINE_FLUSH -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L -#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L -//GCEA_IO_GROUP_BURST -#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 -#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 -#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 -#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 -#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL -#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L -#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L -#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L -//GCEA_IO_RD_PRI_AGE -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_IO_WR_PRI_AGE -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L -#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L -#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L -#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L -#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L -//GCEA_IO_RD_PRI_QUEUING -#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_WR_PRI_QUEUING -#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_RD_PRI_FIXED -#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_WR_PRI_FIXED -#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L -//GCEA_IO_RD_PRI_URGENCY -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_IO_WR_PRI_URGENCY -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L -#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L -#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L -//GCEA_IO_RD_PRI_URGENCY_MASK -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//GCEA_IO_WR_PRI_URGENCY_MASK -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L -#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L -//GCEA_IO_RD_PRI_QUANT_PRI1 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_RD_PRI_QUANT_PRI2 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_RD_PRI_QUANT_PRI3 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_WR_PRI_QUANT_PRI1 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_WR_PRI_QUANT_PRI2 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_IO_WR_PRI_QUANT_PRI3 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L -#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L -//GCEA_SDP_ARB_DRAM -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 -#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL -#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L -#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L -#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L -//GCEA_SDP_ARB_FINAL -#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 -#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 -#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa -#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf -#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 -#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 -#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 -#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a -#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL -#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L -#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L -#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L -#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L -#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L -#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L -//GCEA_SDP_DRAM_PRIORITY -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//GCEA_SDP_IO_PRIORITY -#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 -#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc -#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 -#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c -#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL -#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L -#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L -#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L -#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L -//GCEA_SDP_CREDITS -#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 -#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 -#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 -#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 -#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL -#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L -#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L -#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L -//GCEA_SDP_TAG_RESERVE0 -#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 -#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 -#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 -#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 -#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL -#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L -#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L -#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L -//GCEA_SDP_TAG_RESERVE1 -#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 -#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 -#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 -#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 -#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL -#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L -#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L -#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L -//GCEA_SDP_VCC_RESERVE0 -#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//GCEA_SDP_VCC_RESERVE1 -#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//GCEA_SDP_VCD_RESERVE0 -#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 -#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 -#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L -#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L -//GCEA_SDP_VCD_RESERVE1 -#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 -#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 -#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc -#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f -#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL -#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L -#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L -#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L -//GCEA_SDP_REQ_CNTL -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 -#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 -#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L -#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L -#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L -#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L -//GCEA_MISC -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 -#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 -#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 -#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa -#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb -#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc -#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd -#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe -#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf -#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 -#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 -#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b -#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c -#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L -#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L -#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L -#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L -#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L -#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L -#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L -#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L -#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L -#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L -#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L -#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L -#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L -#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L -#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L -//GCEA_LATENCY_SAMPLING -#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 -#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd -#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe -#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 -#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L -#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L -#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L -//GCEA_PERFCOUNTER_LO -#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//GCEA_PERFCOUNTER_HI -#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//GCEA_PERFCOUNTER0_CFG -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//GCEA_PERFCOUNTER1_CFG -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//GCEA_PERFCOUNTER_RSLT_CNTL -#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: gc_tcdec -//TCP_INVALIDATE -#define TCP_INVALIDATE__START__SHIFT 0x0 -#define TCP_INVALIDATE__START_MASK 0x00000001L -//TCP_STATUS -#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 -#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 -#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 -#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 -#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 -#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 -#define TCP_STATUS__READ_BUSY__SHIFT 0x6 -#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 -#define TCP_STATUS__VM_BUSY__SHIFT 0x8 -#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L -#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L -#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L -#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L -#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L -#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L -#define TCP_STATUS__READ_BUSY_MASK 0x00000040L -#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L -#define TCP_STATUS__VM_BUSY_MASK 0x00000100L -//TCP_CNTL -#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 -#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 -#define TCP_CNTL__L1_SIZE__SHIFT 0x2 -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 -#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c -#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d -#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e -#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L -#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L -#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL -#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L -#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L -#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L -#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L -#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L -#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L -#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L -//TCP_CHAN_STEER_LO -#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 -#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 -#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 -#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc -#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 -#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 -#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 -#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c -#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL -#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L -#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L -#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L -#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L -#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L -#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L -#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L -//TCP_CHAN_STEER_HI -#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 -#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 -#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 -#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc -#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 -#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 -#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 -#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c -#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL -#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L -#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L -#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L -#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L -#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L -#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L -#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L -//TCP_ADDR_CONFIG -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 -#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 -#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 -#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL -#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L -#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L -#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L -//TCP_CREDIT -#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 -#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 -#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d -#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL -#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L -#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L -//TCP_BUFFER_ADDR_HASH_CNTL -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L -#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L -#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L -//TCP_EDC_CNT -#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 -#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 -#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 -#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL -#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L -#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L -//TC_CFG_L1_LOAD_POLICY0 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e -#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L -//TC_CFG_L1_LOAD_POLICY1 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e -#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL -#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L -//TC_CFG_L1_STORE_POLICY -#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 -#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 -#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 -#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 -#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 -#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 -#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 -#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 -#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 -#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 -#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa -#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb -#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc -#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd -#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe -#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf -#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 -#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 -#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 -#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 -#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 -#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 -#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 -#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 -#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 -#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 -#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a -#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b -#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c -#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d -#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e -#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f -#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L -#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L -#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L -#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L -#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L -#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L -#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L -#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L -#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L -#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L -#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L -#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L -#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L -#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L -#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L -#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L -#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L -#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L -#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L -#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L -#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L -#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L -#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L -#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L -#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L -#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L -//TC_CFG_L2_LOAD_POLICY0 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e -#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L -//TC_CFG_L2_LOAD_POLICY1 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e -#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL -#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L -//TC_CFG_L2_STORE_POLICY0 -#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 -#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 -#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 -#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 -#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 -#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa -#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc -#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe -#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 -#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 -#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 -#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 -#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 -#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a -#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c -#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e -#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L -//TC_CFG_L2_STORE_POLICY1 -#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 -#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 -#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 -#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 -#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 -#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa -#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc -#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe -#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 -#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 -#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 -#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 -#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 -#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a -#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c -#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e -#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L -#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL -#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L -#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L -#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L -#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L -#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L -#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L -//TC_CFG_L2_ATOMIC_POLICY -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L -#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L -//TC_CFG_L1_VOLATILE -#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 -#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL -//TC_CFG_L2_VOLATILE -#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 -#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL -//TCI_STATUS -#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 -#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L -//TCI_CNTL_1 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 -#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 -#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 -#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL -#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L -#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L -//TCI_CNTL_2 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 -#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 -#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L -#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL -//TCC_CTRL -#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 -#define TCC_CTRL__RATE__SHIFT 0x2 -#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 -#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc -#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 -#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15 -#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 -#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c -#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L -#define TCC_CTRL__RATE_MASK 0x0000000CL -#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L -#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L -#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L -#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L -#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L -#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L -#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L -#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L -//TCC_CTRL2 -#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 -#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL -//TCC_EDC_CNT -#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 -#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 -#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 -#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 -#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 -#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa -#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc -#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe -#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 -#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 -#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14 -#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16 -#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18 -#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a -#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c -#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e -#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L -#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL -#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L -#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L -#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L -#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L -#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L -#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L -#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L -#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L -#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L -#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L -#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L -#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L -#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L -#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L -//TCC_EDC_CNT2 -#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0 -#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2 -#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4 -#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6 -#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8 -#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L -#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL -#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L -#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L -#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L -//TCC_REDUNDANCY -#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 -#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 -#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L -#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L -//TCC_EXE_DISABLE -#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 -#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L -//TCC_DSM_CNTL -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L -#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L -#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L -#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L -#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L -#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L -#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L -//TCC_DSM_CNTLA -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15 -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18 -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L -#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L -#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L -#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L -#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L -#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L -#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L -#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L -//TCC_DSM_CNTL2 -#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 -#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 -#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L -#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L -#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//TCC_DSM_CNTL2A -#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 -#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 -#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 -#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe -#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf -#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 -#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 -#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d -#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L -#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L -#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L -#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L -#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L -#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L -#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L -#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L -#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L -#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L -#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L -#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L -//TCC_DSM_CNTL2B -#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L -//TCC_WBINVL2 -#define TCC_WBINVL2__DONE__SHIFT 0x4 -#define TCC_WBINVL2__DONE_MASK 0x00000010L -//TCC_SOFT_RESET -#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 -#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L -//TCA_CTRL -#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 -#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 -#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 -#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 -#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 -#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL -#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L -#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L -#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L -#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L -//TCA_BURST_MASK -#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 -#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL -//TCA_BURST_CTRL -#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 -#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3 -#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 -#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 -#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 -#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 -#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8 -#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9 -#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa -#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb -#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc -#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd -#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe -#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L -#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L -#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L -#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L -#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L -#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L -#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L -#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L -#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L -#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L -#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L -#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L -#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L -//TCA_DSM_CNTL -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L -#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L -#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L -//TCA_DSM_CNTL2 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 -#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 -#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 -#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L -#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L -#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L -#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L -#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L -//TCA_EDC_CNT -#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0 -#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2 -#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L -#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL - - -// addressBlock: gc_shdec -//SPI_SHADER_PGM_RSRC3_PS -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL -#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L -#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L -#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L -//SPI_SHADER_PGM_LO_PS -#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_PS -#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_PS -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d -#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L -//SPI_SHADER_PGM_RSRC2_PS -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L -#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L -#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_PS_0 -#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_1 -#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_2 -#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_3 -#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_4 -#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_5 -#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_6 -#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_7 -#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_8 -#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_9 -#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_10 -#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_11 -#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_12 -#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_13 -#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_14 -#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_15 -#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_16 -#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_17 -#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_18 -#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_19 -#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_20 -#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_21 -#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_22 -#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_23 -#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_24 -#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_25 -#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_26 -#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_27 -#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_28 -#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_29 -#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_30 -#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_PS_31 -#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_RSRC3_VS -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL -#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L -#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L -#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L -//SPI_SHADER_LATE_ALLOC_VS -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 -#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL -//SPI_SHADER_PGM_LO_VS -#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_VS -#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_VS -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f -#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L -#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L -#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L -//SPI_SHADER_PGM_RSRC2_VS -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd -#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L -#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L -#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L -#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L -#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L -#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_VS_0 -#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_1 -#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_2 -#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_3 -#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_4 -#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_5 -#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_6 -#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_7 -#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_8 -#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_9 -#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_10 -#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_11 -#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_12 -#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_13 -#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_14 -#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_15 -#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_16 -#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_17 -#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_18 -#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_19 -#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_20 -#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_21 -#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_22 -#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_23 -#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_24 -#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_25 -#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_26 -#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_27 -#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_28 -#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_29 -#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_30 -#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_VS_31 -#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_RSRC2_GS_VS -#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 -#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 -#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L -#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_PGM_RSRC4_GS -#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL -#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L -//SPI_SHADER_USER_DATA_ADDR_LO_GS -#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ADDR_HI_GS -#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_LO_ES -#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_ES -#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC3_GS -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 -#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a -#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL -#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L -#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L -#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L -//SPI_SHADER_PGM_LO_GS -#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_GS -#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_GS -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 -#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d -#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f -#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L -#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L -#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L -//SPI_SHADER_PGM_RSRC2_GS -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 -#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 -#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L -#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L -#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L -#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L -#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_ES_0 -#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_1 -#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_2 -#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_3 -#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_4 -#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_5 -#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_6 -#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_7 -#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_8 -#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_9 -#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_10 -#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_11 -#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_12 -#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_13 -#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_14 -#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_15 -#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_16 -#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_17 -#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_18 -#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_19 -#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_20 -#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_21 -#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_22 -#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_23 -#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_24 -#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_25 -#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_26 -#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_27 -#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_28 -#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_29 -#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_30 -#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ES_31 -#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_RSRC4_HS -#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL -//SPI_SHADER_USER_DATA_ADDR_LO_HS -#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_ADDR_HI_HS -#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_LO_LS -#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_LS -#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC3_HS -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L -#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L -//SPI_SHADER_PGM_LO_HS -#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL -//SPI_SHADER_PGM_HI_HS -#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 -#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL -//SPI_SHADER_PGM_RSRC1_HS -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc -#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 -#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e -#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL -#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L -#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L -#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L -#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L -#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L -#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L -#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L -#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L -//SPI_SHADER_PGM_RSRC2_HS -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 -#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 -#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c -#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL -#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L -#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L -#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L -#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L -#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L -//SPI_SHADER_USER_DATA_LS_0 -#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_1 -#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_2 -#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_3 -#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_4 -#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_5 -#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_6 -#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_7 -#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_8 -#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_9 -#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_10 -#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_11 -#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_12 -#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_13 -#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_14 -#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_15 -#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_16 -#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_17 -#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_18 -#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_19 -#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_20 -#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_21 -#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_22 -#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_23 -#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_24 -#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_25 -#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_26 -#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_27 -#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_28 -#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_29 -#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_30 -#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_LS_31 -#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_0 -#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_1 -#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_2 -#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_3 -#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_4 -#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_5 -#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_6 -#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_7 -#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_8 -#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_9 -#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_10 -#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_11 -#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_12 -#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_13 -#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_14 -#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_15 -#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_16 -#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_17 -#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_18 -#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_19 -#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_20 -#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_21 -#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_22 -#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_23 -#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_24 -#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_25 -#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_26 -#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_27 -#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_28 -#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_29 -#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_30 -#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL -//SPI_SHADER_USER_DATA_COMMON_31 -#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 -#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL -//COMPUTE_DISPATCH_INITIATOR -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb -#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc -#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe -#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L -#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L -#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L -#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L -#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L -#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L -#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L -#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L -#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L -#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L -//COMPUTE_DIM_X -#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 -#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL -//COMPUTE_DIM_Y -#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 -#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL -//COMPUTE_DIM_Z -#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 -#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL -//COMPUTE_START_X -#define COMPUTE_START_X__START__SHIFT 0x0 -#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL -//COMPUTE_START_Y -#define COMPUTE_START_Y__START__SHIFT 0x0 -#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL -//COMPUTE_START_Z -#define COMPUTE_START_Z__START__SHIFT 0x0 -#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL -//COMPUTE_NUM_THREAD_X -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL -#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L -//COMPUTE_NUM_THREAD_Y -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL -#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L -//COMPUTE_NUM_THREAD_Z -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL -#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L -//COMPUTE_PIPELINESTAT_ENABLE -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 -#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L -//COMPUTE_PERFCOUNT_ENABLE -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 -#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L -//COMPUTE_PGM_LO -#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 -#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL -//COMPUTE_PGM_HI -#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 -#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL -//COMPUTE_DISPATCH_PKT_ADDR_LO -#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL -//COMPUTE_DISPATCH_PKT_ADDR_HI -#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL -//COMPUTE_DISPATCH_SCRATCH_BASE_LO -#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL -//COMPUTE_DISPATCH_SCRATCH_BASE_HI -#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 -#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL -//COMPUTE_PGM_RSRC1 -#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 -#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 -#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa -#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc -#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 -#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 -#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 -#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 -#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a -#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL -#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L -#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L -#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L -#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L -#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L -#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L -#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L -#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L -//COMPUTE_PGM_RSRC2 -#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 -#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 -#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 -#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 -#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd -#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf -#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 -#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f -#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L -#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL -#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L -#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L -#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L -#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L -#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L -#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L -#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L -#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L -#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L -//COMPUTE_VMID -#define COMPUTE_VMID__DATA__SHIFT 0x0 -#define COMPUTE_VMID__DATA_MASK 0x0000000FL -//COMPUTE_RESOURCE_LIMITS -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 -#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b -#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL -#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L -#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L -#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L -#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L -#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L -//COMPUTE_STATIC_THREAD_MGMT_SE0 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_STATIC_THREAD_MGMT_SE1 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_TMPRING_SIZE -#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 -#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc -#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL -#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L -//COMPUTE_STATIC_THREAD_MGMT_SE2 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_STATIC_THREAD_MGMT_SE3 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL -#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L -//COMPUTE_RESTART_X -#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 -#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL -//COMPUTE_RESTART_Y -#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 -#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL -//COMPUTE_RESTART_Z -#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 -#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL -//COMPUTE_THREAD_TRACE_ENABLE -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 -#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L -//COMPUTE_MISC_RESERVED -#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 -#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 -#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 -#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 -#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L -#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L -#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L -#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L -#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L -//COMPUTE_DISPATCH_ID -#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 -#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL -//COMPUTE_THREADGROUP_ID -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 -#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL -//COMPUTE_RELAUNCH -#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 -#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e -#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f -#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL -#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L -#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L -//COMPUTE_WAVE_RESTORE_ADDR_LO -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 -#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL -//COMPUTE_WAVE_RESTORE_ADDR_HI -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 -#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL -//COMPUTE_USER_DATA_0 -#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_1 -#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_2 -#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_3 -#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_4 -#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_5 -#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_6 -#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_7 -#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_8 -#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_9 -#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_10 -#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_11 -#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_12 -#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_13 -#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_14 -#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL -//COMPUTE_USER_DATA_15 -#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 -#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL -//COMPUTE_NOWHERE -#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 -#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_cppdec -//CP_DFY_CNTL -#define CP_DFY_CNTL__POLICY__SHIFT 0x0 -#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 -#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a -#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c -#define CP_DFY_CNTL__MODE__SHIFT 0x1d -#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f -#define CP_DFY_CNTL__POLICY_MASK 0x00000001L -#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL -#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L -#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L -#define CP_DFY_CNTL__MODE_MASK 0x60000000L -#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L -//CP_DFY_STAT -#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 -#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 -#define CP_DFY_STAT__BUSY__SHIFT 0x1f -#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL -#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L -#define CP_DFY_STAT__BUSY_MASK 0x80000000L -//CP_DFY_ADDR_HI -#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL -//CP_DFY_ADDR_LO -#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 -#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L -//CP_DFY_DATA_0 -#define CP_DFY_DATA_0__DATA__SHIFT 0x0 -#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_1 -#define CP_DFY_DATA_1__DATA__SHIFT 0x0 -#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_2 -#define CP_DFY_DATA_2__DATA__SHIFT 0x0 -#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_3 -#define CP_DFY_DATA_3__DATA__SHIFT 0x0 -#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_4 -#define CP_DFY_DATA_4__DATA__SHIFT 0x0 -#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_5 -#define CP_DFY_DATA_5__DATA__SHIFT 0x0 -#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_6 -#define CP_DFY_DATA_6__DATA__SHIFT 0x0 -#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_7 -#define CP_DFY_DATA_7__DATA__SHIFT 0x0 -#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_8 -#define CP_DFY_DATA_8__DATA__SHIFT 0x0 -#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_9 -#define CP_DFY_DATA_9__DATA__SHIFT 0x0 -#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_10 -#define CP_DFY_DATA_10__DATA__SHIFT 0x0 -#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_11 -#define CP_DFY_DATA_11__DATA__SHIFT 0x0 -#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_12 -#define CP_DFY_DATA_12__DATA__SHIFT 0x0 -#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_13 -#define CP_DFY_DATA_13__DATA__SHIFT 0x0 -#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_14 -#define CP_DFY_DATA_14__DATA__SHIFT 0x0 -#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL -//CP_DFY_DATA_15 -#define CP_DFY_DATA_15__DATA__SHIFT 0x0 -#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL -//CP_DFY_CMD -#define CP_DFY_CMD__OFFSET__SHIFT 0x0 -#define CP_DFY_CMD__SIZE__SHIFT 0x10 -#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL -#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L -//CP_EOPQ_WAIT_TIME -#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 -#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa -#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL -#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L -//CP_CPC_MGCG_SYNC_CNTL -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 -#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL -#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L -//CPC_INT_INFO -#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 -#define CPC_INT_INFO__TYPE__SHIFT 0x10 -#define CPC_INT_INFO__VMID__SHIFT 0x14 -#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c -#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL -#define CPC_INT_INFO__TYPE_MASK 0x00010000L -#define CPC_INT_INFO__VMID_MASK 0x00F00000L -#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L -//CP_VIRT_STATUS -#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 -#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL -//CPC_INT_ADDR -#define CPC_INT_ADDR__ADDR__SHIFT 0x0 -#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL -//CPC_INT_PASID -#define CPC_INT_PASID__PASID__SHIFT 0x0 -#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL -//CP_GFX_ERROR -#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 -#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 -#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 -#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 -#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 -#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 -#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 -#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa -#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb -#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc -#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd -#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe -#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf -#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 -#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 -#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 -#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 -#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 -#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 -#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 -#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 -#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 -#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 -#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a -#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b -#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c -#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d -#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e -#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f -#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL -#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L -#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L -#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L -#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L -#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L -#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L -#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L -#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L -#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L -#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L -#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L -#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L -#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L -#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L -#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L -#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L -#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L -#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L -#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L -#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L -#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L -#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L -#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L -#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L -#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L -#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L -#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L -#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L -//CPG_UTCL1_CNTL -#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e -#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -//CPC_UTCL1_CNTL -#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e -#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -//CPF_UTCL1_CNTL -#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 -#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e -#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f -#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L -#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L -#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L -//CP_AQL_SMM_STATUS -#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 -#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL -//CP_RB0_BASE -#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB_BASE -#define CP_RB_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB0_CNTL -#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 -#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L -#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB_CNTL -#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB_RPTR_WR -#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 -#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL -//CP_RB0_RPTR_ADDR -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB_RPTR_ADDR -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB0_RPTR_ADDR_HI -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB_RPTR_ADDR_HI -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB0_BUFSZ_MASK -#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 -#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL -//CP_RB_BUFSZ_MASK -#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 -#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL -//CP_RB_WPTR_POLL_ADDR_LO -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 -#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL -//CP_RB_WPTR_POLL_ADDR_HI -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 -#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL -//GC_PRIV_MODE -//CP_INT_CNTL -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_STATUS -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L -//CP_DEVICE_ID -#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 -#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL -//CP_ME0_PIPE_PRIORITY_CNTS -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_RING_PRIORITY_CNTS -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_ME0_PIPE0_PRIORITY -#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_RING0_PRIORITY -#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME0_PIPE1_PRIORITY -#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_RING1_PRIORITY -#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME0_PIPE2_PRIORITY -#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_RING2_PRIORITY -#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_FATAL_ERROR -#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 -#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 -#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 -#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 -#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 -#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L -#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L -#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L -#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L -#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L -//CP_RB_VMID -#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 -#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 -#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 -#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL -#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L -#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L -//CP_ME0_PIPE0_VMID -#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 -#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL -//CP_ME0_PIPE1_VMID -#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 -#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL -//CP_RB0_WPTR -#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB_WPTR -#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB0_WPTR_HI -#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 -#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB_WPTR_HI -#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 -#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB1_WPTR -#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB1_WPTR_HI -#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 -#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL -//CP_RB2_WPTR -#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 -#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL -//CP_RB_DOORBELL_CONTROL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_RANGE_LOWER -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 -#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL -//CP_RB_DOORBELL_RANGE_UPPER -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 -#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL -//CP_MEC_DOORBELL_RANGE_LOWER -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 -#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL -//CP_MEC_DOORBELL_RANGE_UPPER -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 -#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL -//CPG_UTCL1_ERROR -#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 -#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L -//CPC_UTCL1_ERROR -#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 -#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L -//CP_RB1_BASE -#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB1_CNTL -#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB1_RPTR_ADDR -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB1_RPTR_ADDR_HI -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB2_BASE -#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 -#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL -//CP_RB2_CNTL -#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 -#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 -#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 -#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 -#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b -#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f -#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL -#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L -#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L -#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L -#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L -#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L -#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L -//CP_RB2_RPTR_ADDR -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 -#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL -//CP_RB2_RPTR_ADDR_HI -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 -#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_RB0_ACTIVE -#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 -#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L -//CP_RB_ACTIVE -#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 -#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L -//CP_INT_CNTL_RING0 -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_CNTL_RING1 -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_CNTL_RING2 -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L -#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L -#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L -#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L -#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L -#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L -#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_INT_STATUS_RING0 -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L -//CP_INT_STATUS_RING1 -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L -//CP_INT_STATUS_RING2 -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe -#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f -#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L -#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L -#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L -#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L -#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L -#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L -#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L -#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L -#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L -#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L -#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L -#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L -#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L -#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L -#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L -#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 -#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L -//CP_PWR_CNTL -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L -#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L -#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L -//CP_MEM_SLP_CNTL -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 -#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 -#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 -#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L -#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L -#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL -#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L -#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L -#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L -//CP_ECC_FIRSTOCCURRENCE -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 -#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 -#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa -#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc -#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 -#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L -#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L -#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L -#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L -#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L -#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L -//CP_ECC_FIRSTOCCURRENCE_RING0 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL -//CP_ECC_FIRSTOCCURRENCE_RING1 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL -//CP_ECC_FIRSTOCCURRENCE_RING2 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 -#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL -//GB_EDC_MODE -#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf -#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 -#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 -#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 -#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d -#define GB_EDC_MODE__BYPASS__SHIFT 0x1f -#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L -#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L -#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L -#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L -#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L -#define GB_EDC_MODE__BYPASS_MASK 0x80000000L -//CP_PQ_WPTR_POLL_CNTL -#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 -#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e -#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f -#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL -#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L -#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L -#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L -//CP_PQ_WPTR_POLL_CNTL1 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 -#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL -//CP_ME1_PIPE0_INT_CNTL -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE1_INT_CNTL -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE2_INT_CNTL -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE3_INT_CNTL -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE0_INT_CNTL -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE1_INT_CNTL -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE2_INT_CNTL -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME2_PIPE3_INT_CNTL -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CP_ME1_PIPE0_INT_STATUS -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME1_PIPE1_INT_STATUS -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME1_PIPE2_INT_STATUS -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME1_PIPE3_INT_STATUS -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE0_INT_STATUS -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE1_INT_STATUS -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE2_INT_STATUS -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_ME2_PIPE3_INT_STATUS -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 -#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 -#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L -//CC_GC_EDC_CONFIG -#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -//CP_ME1_PIPE_PRIORITY_CNTS -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_ME1_PIPE0_PRIORITY -#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME1_PIPE1_PRIORITY -#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME1_PIPE2_PRIORITY -#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME1_PIPE3_PRIORITY -#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE_PRIORITY_CNTS -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L -#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L -//CP_ME2_PIPE0_PRIORITY -#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE1_PRIORITY -#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE2_PRIORITY -#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_ME2_PIPE3_PRIORITY -#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 -#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L -//CP_CE_PRGRM_CNTR_START -#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL -//CP_PFP_PRGRM_CNTR_START -#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL -//CP_ME_PRGRM_CNTR_START -#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL -//CP_MEC1_PRGRM_CNTR_START -#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL -//CP_MEC2_PRGRM_CNTR_START -#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 -#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL -//CP_CE_INTR_ROUTINE_START -#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL -//CP_PFP_INTR_ROUTINE_START -#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL -//CP_ME_INTR_ROUTINE_START -#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL -//CP_MEC1_INTR_ROUTINE_START -#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL -//CP_MEC2_INTR_ROUTINE_START -#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 -#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL -//CP_CONTEXT_CNTL -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L -#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L -#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L -//CP_MAX_CONTEXT -#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 -#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L -//CP_IQ_WAIT_TIME1 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 -#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 -#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL -#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L -#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L -#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L -//CP_IQ_WAIT_TIME2 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 -#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 -#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 -#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 -#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL -#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L -#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L -#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L -//CP_RB0_BASE_HI -#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 -#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL -//CP_RB1_BASE_HI -#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 -#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL -//CP_VMID_RESET -#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 -#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL -//CPC_INT_CNTL -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf -#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f -#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L -#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L -#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L -#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L -#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L -#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L -#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L -#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L -#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L -#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L -#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L -#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L -#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L -//CPC_INT_STATUS -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf -#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b -#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d -#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e -#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f -#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L -#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L -#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L -#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L -#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L -#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L -#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L -#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L -#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L -#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L -#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L -#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L -#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L -//CP_VMID_PREEMPT -#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 -#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 -#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL -#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L -//CPC_INT_CNTX_ID -#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 -#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL -//CP_PQ_STATUS -#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 -#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 -#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L -#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L -//CP_CPC_IC_BASE_LO -#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc -#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L -//CP_CPC_IC_BASE_HI -#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 -#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL -//CP_CPC_IC_BASE_CNTL -#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 -#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL -#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L -//CP_CPC_IC_OP_CNTL -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 -#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L -#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L -#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L -//CP_MEC1_F32_INT_DIS -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa -#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc -#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd -#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe -#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf -#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L -//CP_MEC2_F32_INT_DIS -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa -#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc -#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd -#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe -#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf -#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L -#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L -#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L -#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L -#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L -#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L -#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L -#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L -#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L -#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L -#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L -#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L -#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L -#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L -#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L -//CP_VMID_STATUS -#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 -#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 -#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL -#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L - - -// addressBlock: gc_cppdec2 -//CP_RB_DOORBELL_CONTROL_SCH_0 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_1 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_2 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_3 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_4 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_5 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_6 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CONTROL_SCH_7 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L -#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L -//CP_RB_DOORBELL_CLEAR -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L -#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L -#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L -#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L -//CP_GFX_MQD_CONTROL -#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 -#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL -#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L -//CP_GFX_MQD_BASE_ADDR -#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 -#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL -//CP_GFX_MQD_BASE_ADDR_HI -#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 -#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL -//CP_RB_STATUS -#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 -#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 -#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L -#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L -//CPG_UTCL1_STATUS -#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//CPC_UTCL1_STATUS -#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//CPF_UTCL1_STATUS -#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -//CP_SD_CNTL -#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 -#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 -#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 -#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 -#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 -#define CP_SD_CNTL__WD_EN__SHIFT 0x5 -#define CP_SD_CNTL__IA_EN__SHIFT 0x6 -#define CP_SD_CNTL__PA_EN__SHIFT 0x7 -#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 -#define CP_SD_CNTL__EA_EN__SHIFT 0x9 -#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L -#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L -#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L -#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L -#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L -#define CP_SD_CNTL__WD_EN_MASK 0x00000020L -#define CP_SD_CNTL__IA_EN_MASK 0x00000040L -#define CP_SD_CNTL__PA_EN_MASK 0x00000080L -#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L -#define CP_SD_CNTL__EA_EN_MASK 0x00000200L -//CP_SOFT_RESET_CNTL -#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 -#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 -#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 -#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 -#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 -#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 -#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 -#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L -#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L -#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L -#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L -#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L -#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L -#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L -//CP_CPC_GFX_CNTL -#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 -#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 -#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 -#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 -#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L -#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L -#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L -#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L - - -// addressBlock: gc_spipdec -//SPI_ARB_PRIORITY -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 -#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc -#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe -#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 -#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L -#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L -#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L -#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L -#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L -#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L -//SPI_ARB_CYCLES_0 -#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 -#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 -#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL -#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L -//SPI_ARB_CYCLES_1 -#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 -#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 -#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL -#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L -//SPI_WCL_PIPE_PERCENT_GFX -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 -#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL -#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L -#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L -#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L -#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L -//SPI_WCL_PIPE_PERCENT_HP3D -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 -#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL -#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L -#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L -//SPI_WCL_PIPE_PERCENT_CS0 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS1 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS2 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS3 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS4 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS5 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS6 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL -//SPI_WCL_PIPE_PERCENT_CS7 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 -#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL -//SPI_COMPUTE_QUEUE_RESET -#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 -#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L -//SPI_RESOURCE_RESERVE_CU_0 -#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_1 -#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_2 -#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_3 -#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_4 -#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_5 -#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_6 -#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_7 -#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_8 -#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_9 -#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_EN_CU_0 -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_1 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_2 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_3 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_4 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_5 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_6 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_7 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_8 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_9 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_CU_10 -#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_11 -#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_EN_CU_10 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_11 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_CU_12 -#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_13 -#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_14 -#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_CU_15 -#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 -#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 -#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf -#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL -#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L -#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L -#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L -#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L -//SPI_RESOURCE_RESERVE_EN_CU_12 -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_13 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_14 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_RESOURCE_RESERVE_EN_CU_15 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 -#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L -#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL -#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L -#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L -//SPI_COMPUTE_WF_CTX_SAVE -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f -#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L -#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L -#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L -#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L -//SPI_ARB_CNTL_0 -#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 -#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 -#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 -#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL -#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L -#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L - - -// addressBlock: gc_cpphqddec -//CP_HQD_GFX_CONTROL -#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 -#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 -#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf -#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL -#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L -#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L -//CP_HQD_GFX_STATUS -#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 -#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL -//CP_HPD_ROQ_OFFSETS -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 -#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L -#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L -#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L -//CP_HPD_STATUS0 -#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 -#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 -#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 -#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 -#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 -#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f -#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL -#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L -#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L -#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L -#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L -#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L -#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L -//CP_HPD_UTCL1_CNTL -#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 -#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL -//CP_HPD_UTCL1_ERROR -#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 -#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 -#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 -#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL -#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L -#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L -//CP_HPD_UTCL1_ERROR_ADDR -#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc -#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L -//CP_MQD_BASE_ADDR -#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 -#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL -//CP_MQD_BASE_ADDR_HI -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 -#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_ACTIVE -#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 -#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 -#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L -#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L -//CP_HQD_VMID -#define CP_HQD_VMID__VMID__SHIFT 0x0 -#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 -#define CP_HQD_VMID__VQID__SHIFT 0x10 -#define CP_HQD_VMID__VMID_MASK 0x0000000FL -#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L -#define CP_HQD_VMID__VQID_MASK 0x03FF0000L -//CP_HQD_PERSISTENT_STATE -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 -#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 -#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 -#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 -#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 -#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 -#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a -#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f -#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L -#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L -#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L -#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L -#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L -#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L -#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L -#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L -#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L -#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L -#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L -#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L -#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L -//CP_HQD_PIPE_PRIORITY -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 -#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L -//CP_HQD_QUEUE_PRIORITY -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 -#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL -//CP_HQD_QUANTUM -#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 -#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 -#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f -#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L -#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L -#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L -#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L -//CP_HQD_PQ_BASE -#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 -#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL -//CP_HQD_PQ_BASE_HI -#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 -#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL -//CP_HQD_PQ_RPTR -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 -#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL -//CP_HQD_PQ_RPTR_REPORT_ADDR -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 -#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL -//CP_HQD_PQ_RPTR_REPORT_ADDR_HI -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 -#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_PQ_WPTR_POLL_ADDR -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 -#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L -//CP_HQD_PQ_WPTR_POLL_ADDR_HI -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 -#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_PQ_DOORBELL_CONTROL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L -#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L -//CP_HQD_PQ_CONTROL -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 -#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 -#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 -#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe -#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf -#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 -#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d -#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e -#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f -#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL -#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L -#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L -#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L -#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L -#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L -#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L -#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L -#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L -#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L -#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L -#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L -#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L -#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L -#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L -//CP_HQD_IB_BASE_ADDR -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 -#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL -//CP_HQD_IB_BASE_ADDR_HI -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 -#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_IB_RPTR -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 -#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL -//CP_HQD_IB_CONTROL -#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 -#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f -#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL -#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L -#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L -//CP_HQD_IQ_TIMER -#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 -#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc -#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 -#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 -#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d -#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e -#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f -#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL -#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L -#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L -#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L -#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L -#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L -#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L -#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L -#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L -#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L -#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L -#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L -//CP_HQD_IQ_RPTR -#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 -#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL -//CP_HQD_DEQUEUE_REQUEST -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L -#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L -#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L -//CP_HQD_DMA_OFFLOAD -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 -#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L -//CP_HQD_OFFLOAD -#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 -#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L -#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L -#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L -#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L -//CP_HQD_SEMA_CMD -#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 -#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 -#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L -#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L -//CP_HQD_MSG_TYPE -#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 -#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 -#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L -#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L -//CP_HQD_ATOMIC0_PREOP_LO -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_HQD_ATOMIC0_PREOP_HI -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_HQD_ATOMIC1_PREOP_LO -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_HQD_ATOMIC1_PREOP_HI -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_HQD_HQ_SCHEDULER0 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 -#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL -//CP_HQD_HQ_STATUS0 -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 -#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 -#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa -#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e -#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f -#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L -#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL -#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L -#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L -#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L -#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L -#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L -#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L -#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L -//CP_HQD_HQ_CONTROL0 -#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 -#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL -//CP_HQD_HQ_SCHEDULER1 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 -#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL -//CP_MQD_CONTROL -#define CP_MQD_CONTROL__VMID__SHIFT 0x0 -#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 -#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc -#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd -#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL -#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L -#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L -#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L -#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L -//CP_HQD_HQ_STATUS1 -#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 -#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL -//CP_HQD_HQ_CONTROL1 -#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 -#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL -//CP_HQD_EOP_BASE_ADDR -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 -#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL -//CP_HQD_EOP_BASE_ADDR_HI -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 -#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL -//CP_HQD_EOP_CONTROL -#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe -#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 -#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f -#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL -#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L -#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L -#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L -#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L -#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L -#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L -#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L -#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L -#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L -//CP_HQD_EOP_RPTR -#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 -#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c -#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e -#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f -#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL -#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L -#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L -#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L -#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L -//CP_HQD_EOP_WPTR -#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 -#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf -#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 -#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL -#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L -#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L -//CP_HQD_EOP_EVENTS -#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 -#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL -#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L -//CP_HQD_CTX_SAVE_BASE_ADDR_LO -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc -#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L -//CP_HQD_CTX_SAVE_BASE_ADDR_HI -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_HQD_CTX_SAVE_CONTROL -#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 -#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 -#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L -#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L -//CP_HQD_CNTL_STACK_OFFSET -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 -#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL -//CP_HQD_CNTL_STACK_SIZE -#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc -#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L -//CP_HQD_WG_STATE_OFFSET -#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 -#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL -//CP_HQD_CTX_SAVE_SIZE -#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc -#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L -//CP_HQD_GDS_RESOURCE_STATE -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc -#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L -#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L -#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L -//CP_HQD_ERROR -#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 -#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 -#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 -#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 -#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 -#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa -#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb -#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc -#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd -#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe -#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf -#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 -#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 -#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 -#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 -#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL -#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L -#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L -#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L -#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L -#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L -#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L -#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L -#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L -#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L -#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L -#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L -#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L -#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L -#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L -//CP_HQD_EOP_WPTR_MEM -#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 -#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL -//CP_HQD_AQL_CONTROL -#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 -#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf -#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 -#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f -#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL -#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L -#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L -#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L -//CP_HQD_PQ_WPTR_LO -#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 -#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL -//CP_HQD_PQ_WPTR_HI -#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 -#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_didtdec -//DIDT_IND_INDEX -#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 -#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL -//DIDT_IND_DATA -#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 -#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_gccacdec -//GC_CAC_CTRL_1 -#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 -#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 -#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL -#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L -//GC_CAC_CTRL_2 -#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 -#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 -#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2 -#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L -#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L -#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL -//GC_CAC_CGTT_CLK_CTRL -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//GC_CAC_AGGR_LOWER -#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 -#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_AGGR_UPPER -#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 -#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL -//GC_CAC_PG_AGGR_LOWER -#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 -#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_PG_AGGR_UPPER -#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 -#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xFFFFFFFFL -//GC_CAC_SOFT_CTRL -#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 -#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1 -#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L -#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL -//GC_DIDT_CTRL0 -#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 -#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 -#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L -#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L -//GC_DIDT_CTRL1 -#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 -#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 -#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//GC_DIDT_CTRL2 -#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe -#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a -#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f -#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L -#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L -#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L -//GC_DIDT_WEIGHT -#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 -#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 -#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 -#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 -#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL -#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L -#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L -#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L -//GC_EDC_CTRL -#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 -#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa -#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L -#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L -//GC_EDC_THRESHOLD -#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//GC_EDC_STATUS -#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 -#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3 -#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L -#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L -//GC_EDC_OVERFLOW -#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11 -#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12 -#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L -#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L -//GC_EDC_ROLLING_POWER_DELTA -#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//GC_DIDT_DROOP_CTRL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf -#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13 -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L -#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L -#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L -//GC_EDC_DROOP_CTRL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf -#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14 -#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15 -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L -#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL -#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L -#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L -#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L -//GC_CAC_IND_INDEX -#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 -#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL -//GC_CAC_IND_DATA -#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 -#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL -//SE_CAC_CGTT_CLK_CTRL -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//SE_CAC_IND_INDEX -#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 -#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL -//SE_CAC_IND_DATA -#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 -#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL - - -// addressBlock: gc_tcpdec -//TCP_WATCH0_ADDR_H -#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH0_ADDR_L -#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH0_CNTL -#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L -//TCP_WATCH1_ADDR_H -#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH1_ADDR_L -#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH1_CNTL -#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L -//TCP_WATCH2_ADDR_H -#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH2_ADDR_L -#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH2_CNTL -#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L -//TCP_WATCH3_ADDR_H -#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 -#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL -//TCP_WATCH3_ADDR_L -#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 -#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L -//TCP_WATCH3_CNTL -#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 -#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 -#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c -#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d -#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f -#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL -#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L -#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L -#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L -#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L -//TCP_GATCL1_CNTL -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 -#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L -#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L -#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L -#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//TCP_ATC_EDC_GATCL1_CNT -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 -#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL -//TCP_GATCL1_DSM_CNTL -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L -#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L -#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L -//TCP_CNTL2 -#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 -#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL -//TCP_UTCL1_CNTL1 -#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 -#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 -#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 -#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 -#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 -#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 -#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 -#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 -#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 -#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 -#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a -#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c -#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e -#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L -#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L -#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L -#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L -#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L -#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L -#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L -#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L -#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L -#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L -#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L -#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L -#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L -//TCP_UTCL1_CNTL2 -#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 -#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 -#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa -#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc -#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe -#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf -#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a -#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL -#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L -#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L -#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L -#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L -#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L -#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L -//TCP_UTCL1_STATUS -#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -//TCP_PERFCOUNTER_FILTER -#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 -#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 -#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 -#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 -#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb -#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf -#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 -#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 -#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 -#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a -#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b -#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L -#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L -#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL -#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L -#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L -#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L -#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L -#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L -#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L -#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L -#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L -#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L -//TCP_PERFCOUNTER_FILTER_EN -#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 -#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 -#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 -#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 -#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 -#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 -#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 -#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 -#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 -#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 -#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa -#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb -#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L -#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L -#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L -#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L -#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L -#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L -#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L -#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L -#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L -#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L -#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L -#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L - - -// addressBlock: gc_gdspdec -//GDS_VMID0_BASE -#define GDS_VMID0_BASE__BASE__SHIFT 0x0 -#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID0_SIZE -#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID1_BASE -#define GDS_VMID1_BASE__BASE__SHIFT 0x0 -#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID1_SIZE -#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID2_BASE -#define GDS_VMID2_BASE__BASE__SHIFT 0x0 -#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID2_SIZE -#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID3_BASE -#define GDS_VMID3_BASE__BASE__SHIFT 0x0 -#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID3_SIZE -#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID4_BASE -#define GDS_VMID4_BASE__BASE__SHIFT 0x0 -#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID4_SIZE -#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID5_BASE -#define GDS_VMID5_BASE__BASE__SHIFT 0x0 -#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID5_SIZE -#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID6_BASE -#define GDS_VMID6_BASE__BASE__SHIFT 0x0 -#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID6_SIZE -#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID7_BASE -#define GDS_VMID7_BASE__BASE__SHIFT 0x0 -#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID7_SIZE -#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID8_BASE -#define GDS_VMID8_BASE__BASE__SHIFT 0x0 -#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID8_SIZE -#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID9_BASE -#define GDS_VMID9_BASE__BASE__SHIFT 0x0 -#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID9_SIZE -#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID10_BASE -#define GDS_VMID10_BASE__BASE__SHIFT 0x0 -#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID10_SIZE -#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID11_BASE -#define GDS_VMID11_BASE__BASE__SHIFT 0x0 -#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID11_SIZE -#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID12_BASE -#define GDS_VMID12_BASE__BASE__SHIFT 0x0 -#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID12_SIZE -#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID13_BASE -#define GDS_VMID13_BASE__BASE__SHIFT 0x0 -#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID13_SIZE -#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID14_BASE -#define GDS_VMID14_BASE__BASE__SHIFT 0x0 -#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID14_SIZE -#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_VMID15_BASE -#define GDS_VMID15_BASE__BASE__SHIFT 0x0 -#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL -//GDS_VMID15_SIZE -#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 -#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL -//GDS_GWS_VMID0 -#define GDS_GWS_VMID0__BASE__SHIFT 0x0 -#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID1 -#define GDS_GWS_VMID1__BASE__SHIFT 0x0 -#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID2 -#define GDS_GWS_VMID2__BASE__SHIFT 0x0 -#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID3 -#define GDS_GWS_VMID3__BASE__SHIFT 0x0 -#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID4 -#define GDS_GWS_VMID4__BASE__SHIFT 0x0 -#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID5 -#define GDS_GWS_VMID5__BASE__SHIFT 0x0 -#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID6 -#define GDS_GWS_VMID6__BASE__SHIFT 0x0 -#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID7 -#define GDS_GWS_VMID7__BASE__SHIFT 0x0 -#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID8 -#define GDS_GWS_VMID8__BASE__SHIFT 0x0 -#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID9 -#define GDS_GWS_VMID9__BASE__SHIFT 0x0 -#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID10 -#define GDS_GWS_VMID10__BASE__SHIFT 0x0 -#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID11 -#define GDS_GWS_VMID11__BASE__SHIFT 0x0 -#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID12 -#define GDS_GWS_VMID12__BASE__SHIFT 0x0 -#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID13 -#define GDS_GWS_VMID13__BASE__SHIFT 0x0 -#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID14 -#define GDS_GWS_VMID14__BASE__SHIFT 0x0 -#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L -//GDS_GWS_VMID15 -#define GDS_GWS_VMID15__BASE__SHIFT 0x0 -#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 -#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL -#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L -//GDS_OA_VMID0 -#define GDS_OA_VMID0__MASK__SHIFT 0x0 -#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID1 -#define GDS_OA_VMID1__MASK__SHIFT 0x0 -#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID2 -#define GDS_OA_VMID2__MASK__SHIFT 0x0 -#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID3 -#define GDS_OA_VMID3__MASK__SHIFT 0x0 -#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID4 -#define GDS_OA_VMID4__MASK__SHIFT 0x0 -#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID5 -#define GDS_OA_VMID5__MASK__SHIFT 0x0 -#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID6 -#define GDS_OA_VMID6__MASK__SHIFT 0x0 -#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID7 -#define GDS_OA_VMID7__MASK__SHIFT 0x0 -#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID8 -#define GDS_OA_VMID8__MASK__SHIFT 0x0 -#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID9 -#define GDS_OA_VMID9__MASK__SHIFT 0x0 -#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID10 -#define GDS_OA_VMID10__MASK__SHIFT 0x0 -#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID11 -#define GDS_OA_VMID11__MASK__SHIFT 0x0 -#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID12 -#define GDS_OA_VMID12__MASK__SHIFT 0x0 -#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID13 -#define GDS_OA_VMID13__MASK__SHIFT 0x0 -#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID14 -#define GDS_OA_VMID14__MASK__SHIFT 0x0 -#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L -//GDS_OA_VMID15 -#define GDS_OA_VMID15__MASK__SHIFT 0x0 -#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 -#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL -#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L -//GDS_GWS_RESET0 -#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 -#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 -#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 -#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 -#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 -#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 -#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 -#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 -#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 -#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 -#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa -#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb -#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc -#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd -#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe -#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf -#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 -#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 -#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 -#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 -#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 -#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 -#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 -#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 -#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 -#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 -#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a -#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b -#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c -#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d -#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e -#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f -#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L -#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L -#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L -#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L -#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L -#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L -#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L -#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L -#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L -#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L -#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L -#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L -#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L -#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L -#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L -#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L -#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L -#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L -#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L -#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L -#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L -#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L -#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L -#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L -#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L -#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L -#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L -#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L -#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L -#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L -#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L -#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L -//GDS_GWS_RESET1 -#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 -#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 -#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 -#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 -#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 -#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 -#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 -#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 -#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 -#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 -#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa -#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb -#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc -#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd -#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe -#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf -#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 -#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 -#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 -#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 -#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 -#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 -#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 -#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 -#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 -#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 -#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a -#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b -#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c -#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d -#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e -#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f -#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L -#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L -#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L -#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L -#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L -#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L -#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L -#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L -#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L -#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L -#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L -#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L -#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L -#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L -#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L -#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L -#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L -#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L -#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L -#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L -#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L -#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L -#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L -#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L -#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L -#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L -#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L -#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L -#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L -#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L -#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L -#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L -//GDS_GWS_RESOURCE_RESET -#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 -#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L -#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L -//GDS_COMPUTE_MAX_WAVE_ID -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 -#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL -//GDS_OA_RESET_MASK -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 -#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb -#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L -#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L -#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L -#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L -#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L -#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L -#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L -#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L -#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L -#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L -#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L -#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L -//GDS_OA_RESET -#define GDS_OA_RESET__RESET__SHIFT 0x0 -#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 -#define GDS_OA_RESET__RESET_MASK 0x00000001L -#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L -//GDS_ENHANCE -#define GDS_ENHANCE__MISC__SHIFT 0x0 -#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 -#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 -#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 -#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 -#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 -#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 -#define GDS_ENHANCE__UNUSED__SHIFT 0x16 -#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL -#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L -#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L -#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L -#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L -#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L -#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L -#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L -//GDS_OA_CGPG_RESTORE -#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 -#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 -#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc -#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 -#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 -#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL -#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L -#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L -#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L -#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L -//GDS_CS_CTXSW_STATUS -#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 -#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 -#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 -#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L -#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L -#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL -//GDS_CS_CTXSW_CNT0 -#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_CS_CTXSW_CNT1 -#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_CS_CTXSW_CNT2 -#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_CS_CTXSW_CNT3 -#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_GFX_CTXSW_STATUS -#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 -#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 -#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 -#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L -#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L -#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL -//GDS_VS_CTXSW_CNT0 -#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_VS_CTXSW_CNT1 -#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_VS_CTXSW_CNT2 -#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_VS_CTXSW_CNT3 -#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT0 -#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT1 -#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT2 -#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS0_CTXSW_CNT3 -#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT0 -#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT1 -#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT2 -#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS1_CTXSW_CNT3 -#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT0 -#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT1 -#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT2 -#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS2_CTXSW_CNT3 -#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT0 -#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT1 -#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT2 -#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS3_CTXSW_CNT3 -#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT0 -#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT1 -#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT2 -#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS4_CTXSW_CNT3 -#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT0 -#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT1 -#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT2 -#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS5_CTXSW_CNT3 -#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT0 -#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT1 -#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT2 -#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS6_CTXSW_CNT3 -#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT0 -#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT1 -#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT2 -#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_PS7_CTXSW_CNT3 -#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT0 -#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT1 -#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT2 -#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L -//GDS_GS_CTXSW_CNT3 -#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 -#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 -#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL -#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L - - -// addressBlock: gc_rasdec -//RAS_SIGNATURE_CONTROL -#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 -#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L -//RAS_SIGNATURE_MASK -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 -#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE0 -#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE1 -#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE2 -#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SX_SIGNATURE3 -#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 -#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_DB_SIGNATURE0 -#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_PA_SIGNATURE0 -#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_VGT_SIGNATURE0 -#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SQ_SIGNATURE0 -#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE0 -#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE1 -#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE2 -#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE3 -#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE4 -#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE5 -#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE6 -#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SC_SIGNATURE7 -#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 -#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_IA_SIGNATURE0 -#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_IA_SIGNATURE1 -#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SPI_SIGNATURE0 -#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_SPI_SIGNATURE1 -#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_TA_SIGNATURE0 -#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_TD_SIGNATURE0 -#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_CB_SIGNATURE0 -#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_BCI_SIGNATURE0 -#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 -#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_BCI_SIGNATURE1 -#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL -//RAS_TA_SIGNATURE1 -#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 -#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL - - -// addressBlock: gc_gfxdec0 -//DB_RENDER_CONTROL -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 -#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 -#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 -#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 -#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc -#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L -#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L -#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L -#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L -#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L -#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L -#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L -#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L -#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L -#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L -//DB_COUNT_CONTROL -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 -#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 -#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 -#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc -#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 -#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c -#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L -#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L -#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L -#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L -#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L -#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L -#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L -#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L -#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L -//DB_DEPTH_VIEW -#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 -#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd -#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 -#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a -#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL -#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L -#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L -#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L -//DB_RENDER_OVERRIDE -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa -#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f -#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL -#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L -#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L -#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L -#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L -#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L -#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L -#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L -#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L -#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L -#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L -#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L -#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L -#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L -#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L -#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L -#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L -#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L -#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L -//DB_RENDER_OVERRIDE2 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 -#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L -#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL -#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L -#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L -#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L -#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L -#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L -#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L -#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L -#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L -#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L -#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L -#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L -#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L -#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L -//DB_HTILE_DATA_BASE -#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 -#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_HTILE_DATA_BASE_HI -#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_DEPTH_SIZE -#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 -#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 -#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL -#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L -//DB_DEPTH_BOUNDS_MIN -#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 -#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL -//DB_DEPTH_BOUNDS_MAX -#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 -#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL -//DB_STENCIL_CLEAR -#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 -#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL -//DB_DEPTH_CLEAR -#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 -#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL -//PA_SC_SCREEN_SCISSOR_TL -#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 -#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_SCISSOR_BR -#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 -#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L -//DB_Z_INFO -#define DB_Z_INFO__FORMAT__SHIFT 0x0 -#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 -#define DB_Z_INFO__SW_MODE__SHIFT 0x4 -#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc -#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd -#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf -#define DB_Z_INFO__MAXMIP__SHIFT 0x10 -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 -#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b -#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c -#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d -#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e -#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f -#define DB_Z_INFO__FORMAT_MASK 0x00000003L -#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL -#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L -#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L -#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L -#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L -#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L -#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L -#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L -#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L -#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L -#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L -//DB_STENCIL_INFO -#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 -#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 -#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc -#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd -#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d -#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e -#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L -#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L -#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L -#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L -#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L -#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L -#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L -#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L -//DB_Z_READ_BASE -#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 -#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_Z_READ_BASE_HI -#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_STENCIL_READ_BASE -#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 -#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_STENCIL_READ_BASE_HI -#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_Z_WRITE_BASE -#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 -#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_Z_WRITE_BASE_HI -#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_STENCIL_WRITE_BASE -#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 -#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL -//DB_STENCIL_WRITE_BASE_HI -#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 -#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL -//DB_DFSM_CONTROL -#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 -#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 -#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 -#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L -#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L -#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L -//DB_RENDER_FILTER -#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0 -#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL -//DB_Z_INFO2 -#define DB_Z_INFO2__EPITCH__SHIFT 0x0 -#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL -//DB_STENCIL_INFO2 -#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 -#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL -//TA_BC_BASE_ADDR -#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 -#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL -//TA_BC_BASE_ADDR_HI -#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 -#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL -//COHER_DEST_BASE_HI_0 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_HI_1 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_HI_2 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_HI_3 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 -#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL -//COHER_DEST_BASE_2 -#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL -//COHER_DEST_BASE_3 -#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL -//PA_SC_WINDOW_OFFSET -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 -#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL -#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L -//PA_SC_WINDOW_SCISSOR_TL -#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_WINDOW_SCISSOR_BR -#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 -#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_RULE -#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 -#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL -//PA_SC_CLIPRECT_0_TL -#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_0_BR -#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_1_TL -#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_1_BR -#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_2_TL -#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_2_BR -#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_3_TL -#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L -//PA_SC_CLIPRECT_3_BR -#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 -#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 -#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_EDGERULE -#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 -#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 -#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 -#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc -#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 -#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 -#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c -#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL -#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L -#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L -#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L -#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L -#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L -#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L -//PA_SU_HARDWARE_SCREEN_OFFSET -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL -#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L -//CB_TARGET_MASK -#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 -#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 -#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 -#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc -#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 -#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 -#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 -#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c -#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL -#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L -#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L -#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L -#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L -#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L -#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L -#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L -//CB_SHADER_MASK -#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 -#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 -#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 -#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc -#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 -#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 -#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 -#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c -#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL -#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L -#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L -#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L -#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L -#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L -#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L -#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L -//PA_SC_GENERIC_SCISSOR_TL -#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_GENERIC_SCISSOR_BR -#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 -#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L -//COHER_DEST_BASE_0 -#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL -//COHER_DEST_BASE_1 -#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 -#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL -//PA_SC_VPORT_SCISSOR_0_TL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_0_BR -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_1_TL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_1_BR -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_2_TL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_2_BR -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_3_TL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_3_BR -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_4_TL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_4_BR -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_5_TL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_5_BR -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_6_TL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_6_BR -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_7_TL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_7_BR -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_8_TL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_8_BR -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_9_TL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_9_BR -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_10_TL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_10_BR -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_11_TL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_11_BR -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_12_TL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_12_BR -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_13_TL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_13_BR -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_14_TL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_14_BR -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_SCISSOR_15_TL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f -#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L -#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L -//PA_SC_VPORT_SCISSOR_15_BR -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 -#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL -#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L -//PA_SC_VPORT_ZMIN_0 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_0 -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_1 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_1 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_2 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_2 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_3 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_3 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_4 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_4 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_5 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_5 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_6 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_6 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_7 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_7 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_8 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_8 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_9 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_9 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_10 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_10 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_11 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_11 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_12 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_12 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_13 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_13 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_14 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_14 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMIN_15 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 -#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL -//PA_SC_VPORT_ZMAX_15 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 -#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL -//PA_SC_RASTER_CONFIG -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 -#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 -#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 -#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 -#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 -#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa -#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc -#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe -#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 -#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 -#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 -#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 -#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a -#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL -#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L -#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L -#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L -#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L -#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L -#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L -#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L -#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L -#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L -#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L -#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L -#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L -#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L -//PA_SC_RASTER_CONFIG_1 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL -#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L -//PA_SC_SCREEN_EXTENT_CONTROL -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L -#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL -//PA_SC_TILE_STEERING_OVERRIDE -#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 -#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L -#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L -//CP_PERFMON_CNTX_CNTL -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f -#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L -//CP_PIPEID -#define CP_PIPEID__PIPE_ID__SHIFT 0x0 -#define CP_PIPEID__PIPE_ID_MASK 0x00000003L -//CP_RINGID -#define CP_RINGID__RINGID__SHIFT 0x0 -#define CP_RINGID__RINGID_MASK 0x00000003L -//CP_VMID -#define CP_VMID__VMID__SHIFT 0x0 -#define CP_VMID__VMID_MASK 0x0000000FL -//PA_SC_RIGHT_VERT_GRID -#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 -#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 -#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 -#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 -#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL -#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L -#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L -#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L -//PA_SC_LEFT_VERT_GRID -#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 -#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 -#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 -#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 -#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL -#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L -#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L -#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L -//PA_SC_HORIZ_GRID -#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 -#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 -#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 -#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 -#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL -#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L -#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L -#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_LR -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_TB -#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L -//VGT_MULTI_PRIM_IB_RESET_INDX -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 -#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL -//CB_BLEND_RED -#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 -#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL -//CB_BLEND_GREEN -#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 -#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL -//CB_BLEND_BLUE -#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 -#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL -//CB_BLEND_ALPHA -#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 -#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL -//CB_DCC_CONTROL -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L -#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL -//DB_STENCIL_CONTROL -#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 -#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 -#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 -#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc -#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 -#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL -#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L -#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L -#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L -#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L -#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L -//DB_STENCILREFMASK -#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 -#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 -#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 -#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 -#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL -#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L -#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L -#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L -//DB_STENCILREFMASK_BF -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 -#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 -#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL -#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L -#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L -#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L -//PA_CL_VPORT_XSCALE -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_1 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_1 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_1 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_1 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_1 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_1 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_2 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_2 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_2 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_2 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_2 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_2 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_3 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_3 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_3 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_3 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_3 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_3 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_4 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_4 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_4 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_4 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_4 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_4 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_5 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_5 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_5 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_5 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_5 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_5 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_6 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_6 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_6 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_6 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_6 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_6 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_7 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_7 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_7 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_7 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_7 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_7 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_8 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_8 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_8 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_8 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_8 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_8 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_9 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_9 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_9 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_9 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_9 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_9 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_10 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_10 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_10 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_10 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_10 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_10 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_11 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_11 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_11 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_11 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_11 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_11 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_12 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_12 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_12 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_12 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_12 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_12 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_13 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_13 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_13 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_13 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_13 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_13 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_14 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_14 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_14 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_14 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_14 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_14 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XSCALE_15 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 -#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_XOFFSET_15 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YSCALE_15 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 -#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_YOFFSET_15 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZSCALE_15 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 -#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL -//PA_CL_VPORT_ZOFFSET_15 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 -#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_X -#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_Y -#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_Z -#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_0_W -#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_X -#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_Y -#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_Z -#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_1_W -#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_X -#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_Y -#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_Z -#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_2_W -#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_X -#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_Y -#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_Z -#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_3_W -#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_X -#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_Y -#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_Z -#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_4_W -#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_X -#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_Y -#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_Z -#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_UCP_5_W -#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL -//SPI_PS_INPUT_CNTL_0 -#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_1 -#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_2 -#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_3 -#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_4 -#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_5 -#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_6 -#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_7 -#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_8 -#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_9 -#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_10 -#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_11 -#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_12 -#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_13 -#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_14 -#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_15 -#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_16 -#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_17 -#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_18 -#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_19 -#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 -#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L -#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L -#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_20 -#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_21 -#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_22 -#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_23 -#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_24 -#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_25 -#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_26 -#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_27 -#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_28 -#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_29 -#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_30 -#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L -//SPI_PS_INPUT_CNTL_31 -#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa -#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 -#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L -#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L -#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L -#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L -#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L -#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L -#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L -#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L -//SPI_VS_OUT_CONFIG -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 -#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL -#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L -//SPI_PS_INPUT_ENA -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf -#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L -//SPI_PS_INPUT_ADDR -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf -#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L -#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L -#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L -#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L -#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L -#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L -#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L -#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L -#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L -#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L -#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L -#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L -#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L -#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L -#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L -//SPI_INTERP_CONTROL_0 -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe -#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L -#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L -//SPI_PS_IN_CONTROL -#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 -#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 -#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 -#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe -#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL -#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L -#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L -#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L -#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L -//SPI_BARYC_CNTL -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 -#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 -#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L -#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L -#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L -#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L -#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L -#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L -#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L -//SPI_TMPRING_SIZE -#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 -#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc -#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL -#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L -//SPI_SHADER_POS_FORMAT -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc -#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL -#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L -#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L -#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L -//SPI_SHADER_Z_FORMAT -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 -#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL -//SPI_SHADER_COL_FORMAT -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c -#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL -#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L -#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L -#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L -#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L -#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L -#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L -#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L -//SX_PS_DOWNCONVERT -#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 -#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 -#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 -#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc -#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 -#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 -#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 -#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c -#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL -#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L -#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L -#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L -#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L -#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L -#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L -#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L -//SX_BLEND_OPT_EPSILON -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c -#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL -#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L -#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L -#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L -#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L -#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L -#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L -#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L -//SX_BLEND_OPT_CONTROL -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f -#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L -#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L -#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L -#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L -#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L -#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L -#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L -#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L -#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L -#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L -#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L -#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L -#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L -#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L -#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L -#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L -#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L -//SX_MRT0_BLEND_OPT -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT1_BLEND_OPT -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT2_BLEND_OPT -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT3_BLEND_OPT -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT4_BLEND_OPT -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT5_BLEND_OPT -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT6_BLEND_OPT -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//SX_MRT7_BLEND_OPT -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 -#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L -#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L -#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L -#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L -#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L -#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L -//CB_BLEND0_CONTROL -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND1_CONTROL -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND2_CONTROL -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND3_CONTROL -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND4_CONTROL -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND5_CONTROL -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND6_CONTROL -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_BLEND7_CONTROL -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d -#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e -#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f -#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL -#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L -#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L -#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L -#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L -#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L -#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L -#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L -#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L -//CB_MRT0_EPITCH -#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT1_EPITCH -#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT2_EPITCH -#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT3_EPITCH -#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT4_EPITCH -#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT5_EPITCH -#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT6_EPITCH -#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL -//CB_MRT7_EPITCH -#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 -#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL -//CS_COPY_STATE -#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 -#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -//GFX_COPY_STATE -#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 -#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L -//PA_CL_POINT_X_RAD -#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_POINT_Y_RAD -#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_POINT_SIZE -#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_POINT_CULL_RAD -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL -//VGT_DMA_BASE_HI -#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 -#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL -//VGT_DMA_BASE -#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 -#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL -//VGT_DRAW_INITIATOR -#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 -#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 -#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 -#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 -#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 -#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 -#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d -#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L -#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL -#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L -#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L -#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L -#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L -#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L -#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L -//VGT_IMMED_DATA -#define VGT_IMMED_DATA__DATA__SHIFT 0x0 -#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL -//VGT_EVENT_ADDRESS_REG -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 -#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL -//DB_DEPTH_CONTROL -#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 -#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 -#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 -#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 -#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f -#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L -#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L -#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L -#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L -#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L -#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L -#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L -#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L -#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L -#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L -//DB_EQAA -#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 -#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 -#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 -#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 -#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 -#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b -#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L -#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L -#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L -#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L -#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L -#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L -#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L -#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L -#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L -#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L -#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L -#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L -//CB_COLOR_CONTROL -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 -#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 -#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 -#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L -#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L -#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L -#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L -//DB_SHADER_CONTROL -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 -#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 -#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 -#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf -#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 -#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 -#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 -#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L -#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L -#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L -#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L -#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L -#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L -#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L -#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L -#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L -#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L -#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L -#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L -#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L -#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L -#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L -#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L -//PA_CL_CLIP_CNTL -#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 -#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 -#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 -#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 -#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 -#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd -#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe -#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 -#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b -#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L -#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L -#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L -#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L -#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L -#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L -#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L -#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L -#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L -#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L -#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L -#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L -#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L -#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L -#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L -#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L -#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L -#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L -#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L -//PA_SU_SC_MODE_CNTL -#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 -#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 -#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 -#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 -#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 -#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 -#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L -#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L -#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L -#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L -#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L -#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L -#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L -#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L -#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L -#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L -#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L -#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L -#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L -//PA_CL_VTE_CNTL -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 -#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 -#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 -#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb -#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L -#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L -#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L -#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L -#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L -#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L -#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L -#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L -#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L -#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L -//PA_CL_VS_OUT_CNTL -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a -#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L -#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L -#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L -#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L -#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L -//PA_CL_NANINF_CNTL -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 -#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L -#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L -#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L -#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L -#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L -#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L -#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L -#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L -#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L -#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L -#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L -#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L -#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L -#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L -#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L -#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L -//PA_SU_LINE_STIPPLE_CNTL -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 -#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L -#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L -#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L -#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L -//PA_SU_LINE_STIPPLE_SCALE -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 -#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL -//PA_SU_PRIM_FILTER_CNTL -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L -#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L -#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L -#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L -#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L -#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L -#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L -#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L -//PA_SU_SMALL_PRIM_FILTER_CNTL -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L -//PA_CL_OBJPRIM_ID_CNTL -#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 -#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 -#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 -#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L -#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L -#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L -//PA_CL_NGG_CNTL -#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 -#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 -#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L -#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L -//PA_SU_OVER_RASTERIZATION_CNTL -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 -#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L -#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L -#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L -//PA_SU_POINT_SIZE -#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 -#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 -#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL -#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L -//PA_SU_POINT_MINMAX -#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 -#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 -#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL -#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L -//PA_SU_LINE_CNTL -#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 -#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL -//PA_SC_LINE_STIPPLE -#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d -#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL -#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L -#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L -#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L -//VGT_OUTPUT_PATH_CNTL -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 -#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L -//VGT_HOS_CNTL -#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 -#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L -//VGT_HOS_MAX_TESS_LEVEL -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 -#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL -//VGT_HOS_MIN_TESS_LEVEL -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 -#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL -//VGT_HOS_REUSE_DEPTH -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 -#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL -//VGT_GROUP_PRIM_TYPE -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 -#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL -#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L -#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L -#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L -//VGT_GROUP_FIRST_DECR -#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 -#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL -//VGT_GROUP_DECR -#define VGT_GROUP_DECR__DECR__SHIFT 0x0 -#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL -//VGT_GROUP_VECT_0_CNTL -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 -#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 -#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 -#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L -#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L -//VGT_GROUP_VECT_1_CNTL -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 -#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 -#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 -#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L -#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L -#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L -#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L -#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L -#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L -//VGT_GROUP_VECT_0_FMT_CNTL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c -#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL -#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L -#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L -#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L -#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L -//VGT_GROUP_VECT_1_FMT_CNTL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c -#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL -#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L -#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L -#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L -#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L -//VGT_GS_MODE -#define VGT_GS_MODE__MODE__SHIFT 0x0 -#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 -#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 -#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 -#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb -#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc -#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd -#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe -#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf -#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 -#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 -#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 -#define VGT_GS_MODE__MODE_MASK 0x00000007L -#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L -#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L -#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L -#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L -#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L -#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L -#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L -#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L -#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L -#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L -#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L -#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L -#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L -#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L -//VGT_GS_ONCHIP_CNTL -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb -#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 -#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL -#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L -#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L -//PA_SC_MODE_CNTL_0 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 -#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 -#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 -#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 -#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L -#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L -#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L -#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L -#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L -#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L -//PA_SC_MODE_CNTL_1 -#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c -#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L -#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L -#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L -#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L -#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L -#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L -#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L -#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L -#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L -#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L -#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L -#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L -#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L -#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L -#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L -#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L -#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L -//VGT_ENHANCE -#define VGT_ENHANCE__MISC__SHIFT 0x0 -#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL -//VGT_GS_PER_ES -#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 -#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL -//VGT_ES_PER_GS -#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 -#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL -//VGT_GS_PER_VS -#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 -#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL -//VGT_GSVS_RING_OFFSET_1 -#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 -#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL -//VGT_GSVS_RING_OFFSET_2 -#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 -#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL -//VGT_GSVS_RING_OFFSET_3 -#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 -#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL -//VGT_GS_OUT_PRIM_TYPE -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L -#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L -#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L -//IA_ENHANCE -#define IA_ENHANCE__MISC__SHIFT 0x0 -#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL -//VGT_DMA_SIZE -#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 -#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL -//VGT_DMA_MAX_SIZE -#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 -#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL -//VGT_DMA_INDEX_TYPE -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 -#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 -#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 -#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 -#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 -#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa -#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL -#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L -#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L -#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L -#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L -#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L -//WD_ENHANCE -#define WD_ENHANCE__MISC__SHIFT 0x0 -#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL -//VGT_PRIMITIVEID_EN -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 -#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 -#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L -#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L -#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L -//VGT_DMA_NUM_INSTANCES -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 -#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL -//VGT_PRIMITIVEID_RESET -#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 -#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL -//VGT_EVENT_INITIATOR -#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 -#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b -#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL -#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L -#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L -//VGT_GS_MAX_PRIMS_PER_SUBGROUP -#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 -#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL -//VGT_DRAW_PAYLOAD_CNTL -#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 -#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 -#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 -#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 -#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L -#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L -#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L -#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L -//VGT_INDEX_PAYLOAD_CNTL -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0 -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L -//VGT_INSTANCE_STEP_RATE_0 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 -#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL -//VGT_INSTANCE_STEP_RATE_1 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 -#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL -//VGT_ESGS_RING_ITEMSIZE -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 -#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL -//VGT_GSVS_RING_ITEMSIZE -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 -#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL -//VGT_REUSE_OFF -#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 -#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L -//VGT_VTX_CNT_EN -#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 -#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L -//DB_HTILE_SURFACE -#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 -#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 -#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 -#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 -#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 -#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L -#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L -#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L -#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L -#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L -#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L -#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L -#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L -//DB_SRESULTS_COMPARE_STATE0 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 -#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L -#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L -#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L -//DB_SRESULTS_COMPARE_STATE1 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 -#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L -#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L -#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L -//DB_PRELOAD_CONTROL -#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 -#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 -#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 -#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 -#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL -#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L -#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L -#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L -//VGT_STRMOUT_BUFFER_SIZE_0 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_0 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_0 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_SIZE_1 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_1 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_1 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_SIZE_2 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_2 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_2 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_SIZE_3 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_VTX_STRIDE_3 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL -//VGT_STRMOUT_BUFFER_OFFSET_3 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_DRAW_OPAQUE_OFFSET -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 -#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL -//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 -#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL -//VGT_GS_MAX_VERT_OUT -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 -#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL -//VGT_TESS_DISTRIBUTION -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 -#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d -#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL -#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L -#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L -#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L -//VGT_SHADER_STAGES_EN -#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 -#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 -#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 -#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 -#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc -#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd -#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe -#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf -#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 -#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L -#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L -#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L -#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L -#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L -#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L -#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L -#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L -#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L -#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L -#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L -#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L -//VGT_LS_HS_CONFIG -#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe -#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL -#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L -#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L -//VGT_GS_VERT_ITEMSIZE -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL -//VGT_GS_VERT_ITEMSIZE_1 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL -//VGT_GS_VERT_ITEMSIZE_2 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL -//VGT_GS_VERT_ITEMSIZE_3 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 -#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL -//VGT_TF_PARAM -#define VGT_TF_PARAM__TYPE__SHIFT 0x0 -#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 -#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 -#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 -#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe -#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf -#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 -#define VGT_TF_PARAM__TYPE_MASK 0x00000003L -#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL -#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L -#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L -#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L -#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L -#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L -#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L -//DB_ALPHA_TO_MASK -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe -#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L -#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L -#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L -//VGT_DISPATCH_DRAW_INDEX -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 -#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_DB_FMT_CNTL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL -#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L -//PA_SU_POLY_OFFSET_CLAMP -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_FRONT_SCALE -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_FRONT_OFFSET -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_BACK_SCALE -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL -//PA_SU_POLY_OFFSET_BACK_OFFSET -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 -#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL -//VGT_GS_INSTANCE_CNT -#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 -#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 -#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L -#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL -//VGT_STRMOUT_CONFIG -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 -#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 -#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f -#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L -#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L -#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L -#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L -#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L -#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L -#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L -//VGT_STRMOUT_BUFFER_CONFIG -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L -#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L -//VGT_DMA_EVENT_INITIATOR -#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 -#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa -#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b -#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL -#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L -#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L -//PA_SC_CENTROID_PRIORITY_0 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L -#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L -//PA_SC_CENTROID_PRIORITY_1 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L -#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L -//PA_SC_LINE_CNTL -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 -#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc -#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L -#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L -#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L -#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L -//PA_SC_AA_CONFIG -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 -#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a -#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L -#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L -#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L -#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L -#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L -#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L -//PA_SU_VTX_CNTL -#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 -#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 -#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 -#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L -#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L -#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L -//PA_CL_GB_VERT_CLIP_ADJ -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_GB_VERT_DISC_ADJ -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_GB_HORZ_CLIP_ADJ -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_CL_GB_HORZ_DISC_ADJ -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 -#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L -//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L -#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L -//PA_SC_AA_MASK_X0Y0_X1Y0 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL -#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L -//PA_SC_AA_MASK_X0Y1_X1Y1 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL -#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L -//PA_SC_SHADER_CONTROL -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 -#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 -#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 -#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L -#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L -#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L -//PA_SC_BINNER_CNTL_0 -#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 -#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa -#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd -#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 -#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 -#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b -#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L -#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L -#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L -#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L -#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L -#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L -#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L -//PA_SC_BINNER_CNTL_1 -#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 -#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 -#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL -#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L -//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L -#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L -//PA_SC_NGG_MODE_CNTL -#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 -#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL -//VGT_VERTEX_REUSE_BLOCK_CNTL -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 -#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL -//VGT_OUT_DEALLOC_CNTL -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 -#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL -//CB_COLOR0_BASE -#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_BASE_EXT -#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR0_ATTRIB2 -#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR0_VIEW -#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR0_INFO -#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR0_ATTRIB -#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR0_DCC_CONTROL -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR0_CMASK -#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_CMASK_BASE_EXT -#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR0_FMASK -#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_FMASK_BASE_EXT -#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR0_CLEAR_WORD0 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR0_CLEAR_WORD1 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR0_DCC_BASE -#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR0_DCC_BASE_EXT -#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_BASE -#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_BASE_EXT -#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_ATTRIB2 -#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR1_VIEW -#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR1_INFO -#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR1_ATTRIB -#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR1_DCC_CONTROL -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR1_CMASK -#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_CMASK_BASE_EXT -#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_FMASK -#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_FMASK_BASE_EXT -#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR1_CLEAR_WORD0 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR1_CLEAR_WORD1 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR1_DCC_BASE -#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR1_DCC_BASE_EXT -#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_BASE -#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_BASE_EXT -#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_ATTRIB2 -#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR2_VIEW -#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR2_INFO -#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR2_ATTRIB -#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR2_DCC_CONTROL -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR2_CMASK -#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_CMASK_BASE_EXT -#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_FMASK -#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_FMASK_BASE_EXT -#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR2_CLEAR_WORD0 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR2_CLEAR_WORD1 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR2_DCC_BASE -#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR2_DCC_BASE_EXT -#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_BASE -#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_BASE_EXT -#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_ATTRIB2 -#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR3_VIEW -#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR3_INFO -#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR3_ATTRIB -#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR3_DCC_CONTROL -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR3_CMASK -#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_CMASK_BASE_EXT -#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_FMASK -#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_FMASK_BASE_EXT -#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR3_CLEAR_WORD0 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR3_CLEAR_WORD1 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR3_DCC_BASE -#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR3_DCC_BASE_EXT -#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_BASE -#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_BASE_EXT -#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_ATTRIB2 -#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR4_VIEW -#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR4_INFO -#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR4_ATTRIB -#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR4_DCC_CONTROL -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR4_CMASK -#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_CMASK_BASE_EXT -#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_FMASK -#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_FMASK_BASE_EXT -#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR4_CLEAR_WORD0 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR4_CLEAR_WORD1 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR4_DCC_BASE -#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR4_DCC_BASE_EXT -#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_BASE -#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_BASE_EXT -#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_ATTRIB2 -#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR5_VIEW -#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR5_INFO -#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR5_ATTRIB -#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR5_DCC_CONTROL -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR5_CMASK -#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_CMASK_BASE_EXT -#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_FMASK -#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_FMASK_BASE_EXT -#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR5_CLEAR_WORD0 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR5_CLEAR_WORD1 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR5_DCC_BASE -#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR5_DCC_BASE_EXT -#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_BASE -#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_BASE_EXT -#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_ATTRIB2 -#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR6_VIEW -#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR6_INFO -#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR6_ATTRIB -#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR6_DCC_CONTROL -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR6_CMASK -#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_CMASK_BASE_EXT -#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_FMASK -#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_FMASK_BASE_EXT -#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR6_CLEAR_WORD0 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR6_CLEAR_WORD1 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR6_DCC_BASE -#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR6_DCC_BASE_EXT -#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_BASE -#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_BASE_EXT -#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_ATTRIB2 -#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 -#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe -#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c -#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL -#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L -#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L -//CB_COLOR7_VIEW -#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 -#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd -#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 -#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL -#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L -#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L -//CB_COLOR7_INFO -#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 -#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 -#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 -#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb -#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd -#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe -#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf -#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 -#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 -#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b -#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d -#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L -#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL -#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L -#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L -#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L -#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L -#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L -#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L -#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L -#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L -#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L -#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L -#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L -#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L -#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L -#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L -//CB_COLOR7_ATTRIB -#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 -#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb -#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 -#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 -#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 -#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c -#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e -#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f -#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL -#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L -#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L -#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L -#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L -#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L -#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L -#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L -#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L -#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L -//CB_COLOR7_DCC_CONTROL -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe -#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L -#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L -#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL -#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L -#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L -#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L -#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L -#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L -#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L -//CB_COLOR7_CMASK -#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_CMASK_BASE_EXT -#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_FMASK -#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_FMASK_BASE_EXT -#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL -//CB_COLOR7_CLEAR_WORD0 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 -#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL -//CB_COLOR7_CLEAR_WORD1 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 -#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL -//CB_COLOR7_DCC_BASE -#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL -//CB_COLOR7_DCC_BASE_EXT -#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 -#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL - - -// addressBlock: gc_gfxudec -//CP_EOP_DONE_ADDR_LO -#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 -#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL -//CP_EOP_DONE_ADDR_HI -#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_EOP_DONE_DATA_LO -#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 -#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL -//CP_EOP_DONE_DATA_HI -#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 -#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL -//CP_EOP_LAST_FENCE_LO -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 -#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL -//CP_EOP_LAST_FENCE_HI -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 -#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL -//CP_STREAM_OUT_ADDR_LO -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 -#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL -//CP_STREAM_OUT_ADDR_HI -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 -#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL -//CP_NUM_PRIM_WRITTEN_COUNT0_LO -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT0_HI -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT0_LO -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT0_HI -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT1_LO -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT1_HI -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT1_LO -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT1_HI -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT2_LO -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT2_HI -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT2_LO -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT2_HI -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT3_LO -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_WRITTEN_COUNT3_HI -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 -#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT3_LO -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL -//CP_NUM_PRIM_NEEDED_COUNT3_HI -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 -#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL -//CP_PIPE_STATS_ADDR_LO -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 -#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL -//CP_PIPE_STATS_ADDR_HI -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 -#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL -//CP_VGT_IAVERT_COUNT_LO -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 -#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_IAVERT_COUNT_HI -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 -#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_IAPRIM_COUNT_LO -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 -#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_IAPRIM_COUNT_HI -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 -#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_GSPRIM_COUNT_LO -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 -#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_GSPRIM_COUNT_HI -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 -#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_VSINVOC_COUNT_LO -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_VSINVOC_COUNT_HI -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_GSINVOC_COUNT_LO -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_GSINVOC_COUNT_HI -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_HSINVOC_COUNT_LO -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_HSINVOC_COUNT_HI -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_VGT_DSINVOC_COUNT_LO -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_DSINVOC_COUNT_HI -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_PA_CINVOC_COUNT_LO -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 -#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_PA_CINVOC_COUNT_HI -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 -#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_PA_CPRIM_COUNT_LO -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 -#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL -//CP_PA_CPRIM_COUNT_HI -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 -#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT0_LO -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT0_HI -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT1_LO -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL -//CP_SC_PSINVOC_COUNT1_HI -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 -#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL -//CP_VGT_CSINVOC_COUNT_LO -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 -#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL -//CP_VGT_CSINVOC_COUNT_HI -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 -#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL -//CP_PIPE_STATS_CONTROL -#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 -#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L -//CP_STREAM_OUT_CONTROL -#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 -#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L -//CP_STRMOUT_CNTL -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 -#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L -//SCRATCH_REG0 -#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 -#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL -//SCRATCH_REG1 -#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 -#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL -//SCRATCH_REG2 -#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 -#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL -//SCRATCH_REG3 -#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 -#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL -//SCRATCH_REG4 -#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 -#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL -//SCRATCH_REG5 -#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 -#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL -//SCRATCH_REG6 -#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 -#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL -//SCRATCH_REG7 -#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 -#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL -//CP_APPEND_DATA_HI -#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 -#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_CS_FENCE_HI -#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_PS_FENCE_HI -#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL -//SCRATCH_UMSK -#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 -#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 -#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL -#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L -//SCRATCH_ADDR -#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 -#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL -//CP_PFP_ATOMIC_PREOP_LO -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 -#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL -//CP_PFP_ATOMIC_PREOP_HI -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 -#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC0_PREOP_LO -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC0_PREOP_HI -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC1_PREOP_LO -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_PFP_GDS_ATOMIC1_PREOP_HI -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_APPEND_ADDR_LO -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 -#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL -//CP_APPEND_ADDR_HI -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 -#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 -#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 -#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d -#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL -#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L -#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L -#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L -//CP_APPEND_DATA_LO -#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 -#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_CS_FENCE_LO -#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL -//CP_APPEND_LAST_PS_FENCE_LO -#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 -#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL -//CP_ATOMIC_PREOP_LO -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 -#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ME_ATOMIC_PREOP_LO -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 -#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ATOMIC_PREOP_HI -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 -#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_ATOMIC_PREOP_HI -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 -#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC0_PREOP_LO -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC0_PREOP_LO -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC0_PREOP_HI -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC0_PREOP_HI -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC1_PREOP_LO -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC1_PREOP_LO -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL -//CP_GDS_ATOMIC1_PREOP_HI -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_GDS_ATOMIC1_PREOP_HI -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 -#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL -//CP_ME_MC_WADDR_LO -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 -#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL -//CP_ME_MC_WADDR_HI -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 -#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 -#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL -#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L -//CP_ME_MC_WDATA_LO -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 -#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL -//CP_ME_MC_WDATA_HI -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 -#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL -//CP_ME_MC_RADDR_LO -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 -#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL -//CP_ME_MC_RADDR_HI -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 -#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 -#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL -#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L -//CP_SEM_WAIT_TIMER -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 -#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL -//CP_SIG_SEM_ADDR_LO -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L -//CP_SIG_SEM_ADDR_HI -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d -#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL -#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L -//CP_WAIT_REG_MEM_TIMEOUT -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 -#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL -//CP_WAIT_SEM_ADDR_LO -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L -#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L -//CP_WAIT_SEM_ADDR_HI -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d -#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL -#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L -#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L -#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L -//CP_DMA_PFP_CONTROL -#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd -#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 -#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d -#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L -//CP_DMA_ME_CONTROL -#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd -#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 -#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d -#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L -#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L -#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L -#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L -#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L -//CP_COHER_BASE_HI -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 -#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL -//CP_COHER_START_DELAY -#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 -#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL -//CP_COHER_CNTL -#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 -#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 -#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf -#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 -#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 -#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 -#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 -#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e -#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L -#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L -#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L -#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L -#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L -#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L -#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L -#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L -#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L -#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L -#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L -#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L -#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L -//CP_COHER_SIZE -#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 -#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL -//CP_COHER_BASE -#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 -#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL -//CP_COHER_STATUS -#define CP_COHER_STATUS__MEID__SHIFT 0x18 -#define CP_COHER_STATUS__STATUS__SHIFT 0x1f -#define CP_COHER_STATUS__MEID_MASK 0x03000000L -#define CP_COHER_STATUS__STATUS_MASK 0x80000000L -//CP_DMA_ME_SRC_ADDR -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 -#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_ME_SRC_ADDR_HI -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 -#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_ME_DST_ADDR -#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 -#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_ME_DST_ADDR_HI -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 -#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_ME_COMMAND -#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 -#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a -#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b -#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c -#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d -#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e -#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f -#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL -#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L -//CP_DMA_PFP_SRC_ADDR -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 -#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_PFP_SRC_ADDR_HI -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 -#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_PFP_DST_ADDR -#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 -#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL -//CP_DMA_PFP_DST_ADDR_HI -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 -#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL -//CP_DMA_PFP_COMMAND -#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 -#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a -#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b -#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c -#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d -#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e -#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f -#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL -#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L -#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L -#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L -#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L -#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L -#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L -//CP_DMA_CNTL -#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 -#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 -#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 -#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c -#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d -#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e -#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L -#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L -#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L -#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L -#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L -#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L -//CP_DMA_READ_TAGS -#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c -#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL -#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L -//CP_COHER_SIZE_HI -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 -#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL -//CP_PFP_IB_CONTROL -#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 -#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL -//CP_PFP_LOAD_CONTROL -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 -#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L -#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L -#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L -#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L -//CP_SCRATCH_INDEX -#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 -#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL -//CP_SCRATCH_DATA -#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 -#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL -//CP_RB_OFFSET -#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 -#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL -//CP_IB1_OFFSET -#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 -#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL -//CP_IB2_OFFSET -#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 -#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL -//CP_IB1_PREAMBLE_BEGIN -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 -#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL -//CP_IB1_PREAMBLE_END -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 -#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL -//CP_IB2_PREAMBLE_BEGIN -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 -#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL -//CP_IB2_PREAMBLE_END -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 -#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL -//CP_CE_IB1_OFFSET -#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 -#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL -//CP_CE_IB2_OFFSET -#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 -#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL -//CP_CE_COUNTER -#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 -#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL -//CP_CE_RB_OFFSET -#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 -#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL -//CP_CE_INIT_CMD_BUFSZ -#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 -#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL -//CP_CE_IB1_CMD_BUFSZ -#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 -#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL -//CP_CE_IB2_CMD_BUFSZ -#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 -#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL -//CP_IB1_CMD_BUFSZ -#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 -#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL -//CP_IB2_CMD_BUFSZ -#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 -#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL -//CP_ST_CMD_BUFSZ -#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 -#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL -//CP_CE_INIT_BASE_LO -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 -#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L -//CP_CE_INIT_BASE_HI -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 -#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL -//CP_CE_INIT_BUFSZ -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 -#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL -//CP_CE_IB1_BASE_LO -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 -#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL -//CP_CE_IB1_BASE_HI -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 -#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL -//CP_CE_IB1_BUFSZ -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 -#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL -//CP_CE_IB2_BASE_LO -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 -#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL -//CP_CE_IB2_BASE_HI -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 -#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL -//CP_CE_IB2_BUFSZ -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 -#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL -//CP_IB1_BASE_LO -#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 -#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL -//CP_IB1_BASE_HI -#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 -#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL -//CP_IB1_BUFSZ -#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 -#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL -//CP_IB2_BASE_LO -#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 -#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL -//CP_IB2_BASE_HI -#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 -#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL -//CP_IB2_BUFSZ -#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 -#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL -//CP_ST_BASE_LO -#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 -#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL -//CP_ST_BASE_HI -#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 -#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL -//CP_ST_BUFSZ -#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 -#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL -//CP_EOP_DONE_EVENT_CNTL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc -#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 -#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c -#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL -#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L -#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L -#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L -//CP_EOP_DONE_DATA_CNTL -#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 -#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d -#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L -#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L -#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L -//CP_EOP_DONE_CNTX_ID -#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 -#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL -//CP_PFP_COMPLETION_STATUS -#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 -#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L -//CP_CE_COMPLETION_STATUS -#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 -#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L -//CP_PRED_NOT_VISIBLE -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 -#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L -//CP_PFP_METADATA_BASE_ADDR -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_PFP_METADATA_BASE_ADDR_HI -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_CE_METADATA_BASE_ADDR -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_CE_METADATA_BASE_ADDR_HI -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_DRAW_INDX_INDR_ADDR -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_DRAW_INDX_INDR_ADDR_HI -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_DISPATCH_INDR_ADDR -#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_DISPATCH_INDR_ADDR_HI -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_INDEX_BASE_ADDR -#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_INDEX_BASE_ADDR_HI -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_INDEX_TYPE -#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 -#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -//CP_GDS_BKUP_ADDR -#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 -#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL -//CP_GDS_BKUP_ADDR_HI -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 -#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL -//CP_SAMPLE_STATUS -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 -#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L -#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L -#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L -#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L -#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L -#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L -#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L -#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L -//CP_ME_COHER_CNTL -#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 -#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 -#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 -#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 -#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 -#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 -#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa -#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb -#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc -#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd -#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe -#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 -#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 -#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L -#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L -#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L -#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L -#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L -#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L -#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L -#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L -#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L -#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L -#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L -#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L -#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L -//CP_ME_COHER_SIZE -#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 -#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL -//CP_ME_COHER_SIZE_HI -#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 -#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL -//CP_ME_COHER_BASE -#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 -#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL -//CP_ME_COHER_BASE_HI -#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 -#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL -//CP_ME_COHER_STATUS -#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 -#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f -#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL -#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L -//RLC_GPM_PERF_COUNT_0 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 -#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 -#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 -#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 -#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 -#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 -#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 -#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL -#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L -#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L -#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L -#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L -#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L -#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L -#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L -//RLC_GPM_PERF_COUNT_1 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 -#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 -#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 -#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 -#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 -#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 -#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 -#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL -#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L -#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L -#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L -#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L -#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L -#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L -#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L -//GRBM_GFX_INDEX -#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 -#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 -#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f -#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL -#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L -#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L -#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L -//VGT_GSVS_RING_SIZE -#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 -#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL -//VGT_PRIMITIVE_TYPE -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 -#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL -//VGT_INDEX_TYPE -#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 -#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 -#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L -#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L -//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL -//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 -#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL -//VGT_MAX_VTX_INDX -#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 -#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL -//VGT_MIN_VTX_INDX -#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 -#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL -//VGT_INDX_OFFSET -#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 -#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL -//VGT_MULTI_PRIM_IB_RESET_EN -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 -#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 -#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L -#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L -//VGT_NUM_INDICES -#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 -#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL -//VGT_NUM_INSTANCES -#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 -#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL -//VGT_TF_RING_SIZE -#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 -#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL -//VGT_HS_OFFCHIP_PARAM -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL -#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L -//VGT_TF_MEMORY_BASE -#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 -#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL -//VGT_TF_MEMORY_BASE_HI -#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 -#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL -//WD_POS_BUF_BASE -#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 -#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL -//WD_POS_BUF_BASE_HI -#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 -#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL -//WD_CNTL_SB_BUF_BASE -#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 -#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL -//WD_CNTL_SB_BUF_BASE_HI -#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 -#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL -//WD_INDEX_BUF_BASE -#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 -#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL -//WD_INDEX_BUF_BASE_HI -#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 -#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL -//IA_MULTI_VGT_PARAM -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 -#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 -#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL -#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L -#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L -#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L -#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L -#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L -#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L -//VGT_OBJECT_ID -#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0 -#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL -//VGT_INSTANCE_BASE_ID -#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 -#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL -//PA_SU_LINE_STIPPLE_VALUE -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 -#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL -//PA_SC_LINE_STIPPLE_STATE -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL -#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L -//PA_SC_SCREEN_EXTENT_MIN_0 -#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_EXTENT_MAX_0 -#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_EXTENT_MIN_1 -#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L -//PA_SC_SCREEN_EXTENT_MAX_1 -#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 -#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 -#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL -#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L -//PA_SC_P3D_TRAP_SCREEN_HV_EN -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L -//PA_SC_P3D_TRAP_SCREEN_H -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL -//PA_SC_P3D_TRAP_SCREEN_V -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL -//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL -//PA_SC_P3D_TRAP_SCREEN_COUNT -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 -#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL -//PA_SC_HP3D_TRAP_SCREEN_HV_EN -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L -//PA_SC_HP3D_TRAP_SCREEN_H -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL -//PA_SC_HP3D_TRAP_SCREEN_V -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL -//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL -//PA_SC_HP3D_TRAP_SCREEN_COUNT -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 -#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL -//PA_SC_TRAP_SCREEN_HV_EN -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 -#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L -#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L -//PA_SC_TRAP_SCREEN_H -#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL -//PA_SC_TRAP_SCREEN_V -#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL -//PA_SC_TRAP_SCREEN_OCCURRENCE -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL -//PA_SC_TRAP_SCREEN_COUNT -#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 -#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL -//SQ_THREAD_TRACE_BASE -#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 -#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_SIZE -#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 -#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL -//SQ_THREAD_TRACE_MASK -#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 -#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 -#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf -#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL -#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L -#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L -#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L -#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L -#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L -#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L -//SQ_THREAD_TRACE_TOKEN_MASK -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 -#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L -#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L -//SQ_THREAD_TRACE_PERF_MASK -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 -#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL -#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L -//SQ_THREAD_TRACE_CTRL -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f -#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L -//SQ_THREAD_TRACE_MODE -#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 -#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 -#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 -#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 -#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc -#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf -#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 -#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 -#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b -#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e -#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f -#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L -#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L -#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L -#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L -#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L -#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L -#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L -#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L -#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L -#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L -#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L -#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L -#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L -#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L -#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L -//SQ_THREAD_TRACE_BASE2 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 -#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL -//SQ_THREAD_TRACE_TOKEN_MASK2 -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 -#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_WPTR -#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e -#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL -#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L -//SQ_THREAD_TRACE_STATUS -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 -#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c -#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d -#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e -#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f -#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL -#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L -#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L -#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L -#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L -#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L -//SQ_THREAD_TRACE_HIWATER -#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 -#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L -//SQ_THREAD_TRACE_CNTR -#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 -#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_0 -#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_1 -#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_2 -#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL -//SQ_THREAD_TRACE_USERDATA_3 -#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 -#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL -//SQC_CACHES -#define SQC_CACHES__TARGET_INST__SHIFT 0x0 -#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 -#define SQC_CACHES__INVALIDATE__SHIFT 0x2 -#define SQC_CACHES__WRITEBACK__SHIFT 0x3 -#define SQC_CACHES__VOL__SHIFT 0x4 -#define SQC_CACHES__COMPLETE__SHIFT 0x10 -#define SQC_CACHES__TARGET_INST_MASK 0x00000001L -#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L -#define SQC_CACHES__INVALIDATE_MASK 0x00000004L -#define SQC_CACHES__WRITEBACK_MASK 0x00000008L -#define SQC_CACHES__VOL_MASK 0x00000010L -#define SQC_CACHES__COMPLETE_MASK 0x00010000L -//SQC_WRITEBACK -#define SQC_WRITEBACK__DWB__SHIFT 0x0 -#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 -#define SQC_WRITEBACK__DWB_MASK 0x00000001L -#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L -//TA_CS_BC_BASE_ADDR -#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 -#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL -//TA_CS_BC_BASE_ADDR_HI -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 -#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL -//TA_GRAD_ADJ_UCONFIG -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L -//DB_OCCLUSION_COUNT0_LOW -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT0_HI -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_OCCLUSION_COUNT1_LOW -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT1_HI -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_OCCLUSION_COUNT2_LOW -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT2_HI -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_OCCLUSION_COUNT3_LOW -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_OCCLUSION_COUNT3_HI -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 -#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL -//DB_ZPASS_COUNT_LOW -#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 -#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL -//DB_ZPASS_COUNT_HI -#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 -#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL -//GDS_RD_ADDR -#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 -#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL -//GDS_RD_DATA -#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 -#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL -//GDS_RD_BURST_ADDR -#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 -#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL -//GDS_RD_BURST_COUNT -#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 -#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL -//GDS_RD_BURST_DATA -#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 -#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL -//GDS_WR_ADDR -#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 -#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL -//GDS_WR_DATA -#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 -#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL -//GDS_WR_BURST_ADDR -#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 -#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL -//GDS_WR_BURST_DATA -#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 -#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL -//GDS_WRITE_COMPLETE -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 -#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL -//GDS_ATOM_CNTL -#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 -#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 -#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 -#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa -#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL -#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L -#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L -#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L -//GDS_ATOM_COMPLETE -#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 -#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 -#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L -#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL -//GDS_ATOM_BASE -#define GDS_ATOM_BASE__BASE__SHIFT 0x0 -#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 -#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL -#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L -//GDS_ATOM_SIZE -#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 -#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 -#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL -#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L -//GDS_ATOM_OFFSET0 -#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 -#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 -#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL -#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L -//GDS_ATOM_OFFSET1 -#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 -#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 -#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL -#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L -//GDS_ATOM_DST -#define GDS_ATOM_DST__DST__SHIFT 0x0 -#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL -//GDS_ATOM_OP -#define GDS_ATOM_OP__OP__SHIFT 0x0 -#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 -#define GDS_ATOM_OP__OP_MASK 0x000000FFL -#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L -//GDS_ATOM_SRC0 -#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_SRC0_U -#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_SRC1 -#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_SRC1_U -#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 -#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ0 -#define GDS_ATOM_READ0__DATA__SHIFT 0x0 -#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ0_U -#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 -#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ1 -#define GDS_ATOM_READ1__DATA__SHIFT 0x0 -#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL -//GDS_ATOM_READ1_U -#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 -#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL -//GDS_GWS_RESOURCE_CNTL -#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 -#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 -#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL -#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L -//GDS_GWS_RESOURCE -#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 -#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 -#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd -#define GDS_GWS_RESOURCE__DED__SHIFT 0xe -#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf -#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 -#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c -#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d -#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e -#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f -#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L -#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL -#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L -#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L -#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L -#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L -#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L -#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L -#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L -#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L -//GDS_GWS_RESOURCE_CNT -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 -#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 -#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL -#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L -//GDS_OA_CNTL -#define GDS_OA_CNTL__INDEX__SHIFT 0x0 -#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 -#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL -#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L -//GDS_OA_COUNTER -#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 -#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL -//GDS_OA_ADDRESS -#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 -#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 -#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 -#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 -#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e -#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f -#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL -#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L -#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L -#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L -#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L -#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L -//GDS_OA_INCDEC -#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 -#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f -#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL -#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L -//GDS_OA_RING_SIZE -#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 -#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL -//SPI_CONFIG_CNTL -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b -#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c -#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d -#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e -#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL -#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L -#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L -#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L -#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L -#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L -#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L -#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L -//SPI_CONFIG_CNTL_1 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 -#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa -#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe -#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 -#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL -#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L -#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L -#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L -#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L -#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L -#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L -#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L -//SPI_CONFIG_CNTL_2 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL -#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L - - -// addressBlock: gc_perfddec -//CPG_PERFCOUNTER1_LO -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPG_PERFCOUNTER1_HI -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPG_PERFCOUNTER0_LO -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPG_PERFCOUNTER0_HI -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER1_LO -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER1_HI -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER0_LO -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPC_PERFCOUNTER0_HI -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER1_LO -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER1_HI -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER0_LO -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CPF_PERFCOUNTER0_HI -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CPF_LATENCY_STATS_DATA -#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 -#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL -//CPG_LATENCY_STATS_DATA -#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 -#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL -//CPC_LATENCY_STATS_DATA -#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 -#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER0_LO -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER0_HI -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER1_LO -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_PERFCOUNTER1_HI -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE0_PERFCOUNTER_LO -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE0_PERFCOUNTER_HI -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE1_PERFCOUNTER_LO -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE1_PERFCOUNTER_HI -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE2_PERFCOUNTER_LO -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE2_PERFCOUNTER_HI -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GRBM_SE3_PERFCOUNTER_LO -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GRBM_SE3_PERFCOUNTER_HI -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER0_LO -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER0_HI -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER1_LO -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER1_HI -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER2_LO -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER2_HI -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER3_LO -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//WD_PERFCOUNTER3_HI -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER0_LO -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER0_HI -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER1_LO -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER1_HI -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER2_LO -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER2_HI -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER3_LO -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//IA_PERFCOUNTER3_HI -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER0_LO -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER0_HI -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER1_LO -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER1_HI -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER2_LO -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER2_HI -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER3_LO -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//VGT_PERFCOUNTER3_HI -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER0_LO -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER0_HI -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SU_PERFCOUNTER1_LO -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER1_HI -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SU_PERFCOUNTER2_LO -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER2_HI -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SU_PERFCOUNTER3_LO -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SU_PERFCOUNTER3_HI -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL -//PA_SC_PERFCOUNTER0_LO -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER0_HI -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER1_LO -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER1_HI -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER2_LO -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER2_HI -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER3_LO -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER3_HI -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER4_LO -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER4_HI -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER5_LO -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER5_HI -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER6_LO -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER6_HI -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER7_LO -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//PA_SC_PERFCOUNTER7_HI -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER0_HI -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER0_LO -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER1_HI -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER1_LO -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER2_HI -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER2_LO -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER3_HI -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER3_LO -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER4_HI -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER4_LO -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER5_HI -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SPI_PERFCOUNTER5_LO -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER0_LO -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER0_HI -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER1_LO -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER1_HI -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER2_LO -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER2_HI -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER3_LO -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER3_HI -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER4_LO -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER4_HI -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER5_LO -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER5_HI -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER6_LO -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER6_HI -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER7_LO -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER7_HI -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER8_LO -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER8_HI -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER9_LO -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER9_HI -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER10_LO -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER10_HI -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER11_LO -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER11_HI -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER12_LO -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER12_HI -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER13_LO -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER13_HI -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER14_LO -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER14_HI -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER15_LO -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SQ_PERFCOUNTER15_HI -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER0_LO -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER0_HI -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER1_LO -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER1_HI -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER2_LO -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER2_HI -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER3_LO -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//SX_PERFCOUNTER3_HI -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER0_LO -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER0_HI -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER1_LO -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER1_HI -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER2_LO -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER2_HI -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER3_LO -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//GDS_PERFCOUNTER3_HI -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER0_LO -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER0_HI -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER1_LO -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TA_PERFCOUNTER1_HI -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER0_LO -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER0_HI -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER1_LO -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TD_PERFCOUNTER1_HI -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER0_LO -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER0_HI -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER1_LO -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER1_HI -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER2_LO -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER2_HI -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER3_LO -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCP_PERFCOUNTER3_HI -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER0_LO -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER0_HI -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER1_LO -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER1_HI -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER2_LO -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER2_HI -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER3_LO -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCC_PERFCOUNTER3_HI -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER0_LO -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER0_HI -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER1_LO -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER1_HI -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER2_LO -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER2_HI -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER3_LO -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//TCA_PERFCOUNTER3_HI -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER0_LO -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER0_HI -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER1_LO -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER1_HI -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER2_LO -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER2_HI -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER3_LO -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//CB_PERFCOUNTER3_HI -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER0_LO -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER0_HI -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER1_LO -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER1_HI -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER2_LO -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER2_HI -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER3_LO -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//DB_PERFCOUNTER3_HI -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER0_LO -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER0_HI -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER1_LO -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RLC_PERFCOUNTER1_HI -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER0_LO -#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER0_HI -#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER1_LO -#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER1_HI -#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER2_LO -#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER2_HI -#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER3_LO -#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 -#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL -//RMI_PERFCOUNTER3_HI -#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 -#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL - - -// addressBlock: gc_utcl2_atcl2pfcntrdec -//ATC_L2_PERFCOUNTER_LO -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//ATC_L2_PERFCOUNTER_HI -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: gc_utcl2_vml2prdec -//MC_VM_L2_PERFCOUNTER_LO -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//MC_VM_L2_PERFCOUNTER_HI -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - - -// addressBlock: gc_perfsdec -//CPG_PERFCOUNTER1_SELECT -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPG_PERFCOUNTER0_SELECT1 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL -#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L -#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L -//CPG_PERFCOUNTER0_SELECT -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPC_PERFCOUNTER1_SELECT -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPC_PERFCOUNTER0_SELECT1 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL -#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L -#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L -//CPF_PERFCOUNTER1_SELECT -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPF_PERFCOUNTER0_SELECT1 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL -#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L -#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L -//CPF_PERFCOUNTER0_SELECT -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CP_PERFMON_CNTL -#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa -#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL -#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L -#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L -#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -//CPC_PERFCOUNTER0_SELECT -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa -#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL -#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L -#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L -#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L -//CPF_TC_PERF_COUNTER_WINDOW_SELECT -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L -#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L -//CPG_TC_PERF_COUNTER_WINDOW_SELECT -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L -#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L -//CPF_LATENCY_STATS_SELECT -#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 -#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e -#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f -#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL -#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L -//CPG_LATENCY_STATS_SELECT -#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 -#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e -#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f -#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL -#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L -//CPC_LATENCY_STATS_SELECT -#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 -#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e -#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f -#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L -#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L -#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L -//CP_DRAW_OBJECT -#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 -#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL -//CP_DRAW_OBJECT_COUNTER -#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 -#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL -//CP_DRAW_WINDOW_MASK_HI -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 -#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL -//CP_DRAW_WINDOW_HI -#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 -#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL -//CP_DRAW_WINDOW_LO -#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 -#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 -#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL -#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L -//CP_DRAW_WINDOW_CNTL -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 -#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L -#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L -#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L -//GRBM_PERFCOUNTER0_SELECT -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c -#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d -#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e -#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f -#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L -#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L -#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L -#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L -//GRBM_PERFCOUNTER1_SELECT -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c -#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d -#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e -#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f -#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L -#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L -#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L -#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L -#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L -#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L -#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L -#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L -#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L -#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L -//GRBM_SE0_PERFCOUNTER_SELECT -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//GRBM_SE1_PERFCOUNTER_SELECT -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//GRBM_SE2_PERFCOUNTER_SELECT -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//GRBM_SE3_PERFCOUNTER_SELECT -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 -#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 -#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L -#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L -#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L -#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L -#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L -#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L -#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L -#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L -#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L -//WD_PERFCOUNTER0_SELECT -#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//WD_PERFCOUNTER1_SELECT -#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//WD_PERFCOUNTER2_SELECT -#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//WD_PERFCOUNTER3_SELECT -#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL -#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER0_SELECT -#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER1_SELECT -#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER2_SELECT -#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL -#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER3_SELECT -#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL -#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//IA_PERFCOUNTER0_SELECT1 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//VGT_PERFCOUNTER0_SELECT -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER1_SELECT -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER2_SELECT -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL -#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER3_SELECT -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL -#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//VGT_PERFCOUNTER0_SELECT1 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//VGT_PERFCOUNTER1_SELECT1 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//VGT_PERFCOUNTER_SEID_MASK -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 -#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL -//PA_SU_PERFCOUNTER0_SELECT -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SU_PERFCOUNTER0_SELECT1 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -//PA_SU_PERFCOUNTER1_SELECT -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SU_PERFCOUNTER1_SELECT1 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -//PA_SU_PERFCOUNTER2_SELECT -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SU_PERFCOUNTER3_SELECT -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SC_PERFCOUNTER0_SELECT -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//PA_SC_PERFCOUNTER0_SELECT1 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -//PA_SC_PERFCOUNTER1_SELECT -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER2_SELECT -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER3_SELECT -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER4_SELECT -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER5_SELECT -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER6_SELECT -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL -//PA_SC_PERFCOUNTER7_SELECT -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 -#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL -//SPI_PERFCOUNTER0_SELECT -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER1_SELECT -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER2_SELECT -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER3_SELECT -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L -#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//SPI_PERFCOUNTER0_SELECT1 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER1_SELECT1 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER2_SELECT1 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER3_SELECT1 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L -//SPI_PERFCOUNTER4_SELECT -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL -//SPI_PERFCOUNTER5_SELECT -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 -#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL -//SPI_PERFCOUNTER_BINS -#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 -#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 -#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 -#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc -#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 -#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 -#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 -#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c -#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL -#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L -#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L -#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L -#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L -#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L -#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L -#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L -//SQ_PERFCOUNTER0_SELECT -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER1_SELECT -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER2_SELECT -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER3_SELECT -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER4_SELECT -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER5_SELECT -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER6_SELECT -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER7_SELECT -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER8_SELECT -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER9_SELECT -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER10_SELECT -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER11_SELECT -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER12_SELECT -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER13_SELECT -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER14_SELECT -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER15_SELECT -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c -#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL -#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L -#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L -#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L -#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L -#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L -//SQ_PERFCOUNTER_CTRL -#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 -#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 -#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 -#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 -#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 -#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 -#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd -#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L -#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L -#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L -#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L -#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L -#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L -#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L -#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L -#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L -//SQ_PERFCOUNTER_MASK -#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 -#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 -#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL -#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L -//SQ_PERFCOUNTER_CTRL2 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 -#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L -//SX_PERFCOUNTER0_SELECT -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER1_SELECT -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER2_SELECT -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER3_SELECT -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -//SX_PERFCOUNTER0_SELECT1 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL -#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L -//SX_PERFCOUNTER1_SELECT1 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL -#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L -//GDS_PERFCOUNTER0_SELECT -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER1_SELECT -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER2_SELECT -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER3_SELECT -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL -#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L -#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -//GDS_PERFCOUNTER0_SELECT1 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL -#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L -//TA_PERFCOUNTER0_SELECT -#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL -#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TA_PERFCOUNTER0_SELECT1 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL -#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TA_PERFCOUNTER1_SELECT -#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TD_PERFCOUNTER0_SELECT -#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL -#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TD_PERFCOUNTER0_SELECT1 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL -#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TD_PERFCOUNTER1_SELECT -#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL -#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L -#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER0_SELECT -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER0_SELECT1 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TCP_PERFCOUNTER1_SELECT -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER1_SELECT1 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//TCP_PERFCOUNTER2_SELECT -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//TCP_PERFCOUNTER3_SELECT -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER0_SELECT -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER0_SELECT1 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCC_PERFCOUNTER1_SELECT -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER1_SELECT1 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCC_PERFCOUNTER2_SELECT -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//TCC_PERFCOUNTER3_SELECT -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER0_SELECT -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER0_SELECT1 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCA_PERFCOUNTER1_SELECT -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER1_SELECT1 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L -#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L -//TCA_PERFCOUNTER2_SELECT -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//TCA_PERFCOUNTER3_SELECT -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER_FILTER -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 -#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L -#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L -#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L -#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L -#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L -#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L -#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L -//CB_PERFCOUNTER0_SELECT -#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L -#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER0_SELECT1 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL -#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//CB_PERFCOUNTER1_SELECT -#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER2_SELECT -#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//CB_PERFCOUNTER3_SELECT -#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL -#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER0_SELECT -#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER0_SELECT1 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//DB_PERFCOUNTER1_SELECT -#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER1_SELECT1 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL -#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L -//DB_PERFCOUNTER2_SELECT -#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//DB_PERFCOUNTER3_SELECT -#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 -#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL -#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L -#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L -#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//RLC_SPM_PERFMON_CNTL -#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x2 -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc -#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 -#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFCL -#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L -#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L -#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L -//RLC_SPM_PERFMON_RING_BASE_LO -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 -#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL -//RLC_SPM_PERFMON_RING_BASE_HI -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 -#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL -#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L -//RLC_SPM_PERFMON_RING_SIZE -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 -#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL -//RLC_SPM_PERFMON_SEGMENT_SIZE -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f -#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L -#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L -//RLC_SPM_SE_MUXSEL_ADDR -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 -#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL -//RLC_SPM_SE_MUXSEL_DATA -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 -#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL -//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_CB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_DB_PERFMON_SAMPLE_DELAY -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_PA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_IA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TA_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_TD_PERFMON_SAMPLE_DELAY -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_SX_PERFMON_SAMPLE_DELAY -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_SPM_GLOBAL_MUXSEL_ADDR -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 -#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL -//RLC_SPM_GLOBAL_MUXSEL_DATA -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 -#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL -//RLC_SPM_RING_RDPTR -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 -#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL -//RLC_SPM_SEGMENT_THRESHOLD -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 -#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL -//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL -#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L -//RLC_PERFMON_CLK_CNTL -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 -#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L -//RLC_PERFMON_CNTL -#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa -#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L -#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L -//RLC_PERFCOUNTER0_SELECT -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL -//RLC_PERFCOUNTER1_SELECT -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 -#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL -//RLC_GPU_IOV_PERF_CNT_CNTL -#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 -#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L -#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L -//RLC_GPU_IOV_PERF_CNT_WR_ADDR -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L -#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L -//RLC_GPU_IOV_PERF_CNT_WR_DATA -#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL -//RLC_GPU_IOV_PERF_CNT_RD_ADDR -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L -#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L -//RLC_GPU_IOV_PERF_CNT_RD_DATA -#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL -//RMI_PERFCOUNTER0_SELECT -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa -#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L -#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L -#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERFCOUNTER0_SELECT1 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL -#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L -//RMI_PERFCOUNTER1_SELECT -#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERFCOUNTER2_SELECT -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa -#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L -#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L -#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERFCOUNTER2_SELECT1 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL -#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L -#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L -//RMI_PERFCOUNTER3_SELECT -#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 -#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c -#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL -#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L -//RMI_PERF_COUNTER_CNTL -#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 -#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 -#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 -#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 -#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a -#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L -#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL -#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L -#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L -#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L -#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L -#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L - - -// addressBlock: gc_utcl2_atcl2pfcntldec -//ATC_L2_PERFCOUNTER0_CFG -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//ATC_L2_PERFCOUNTER1_CFG -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//ATC_L2_PERFCOUNTER_RSLT_CNTL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: gc_utcl2_vml2pldec -//MC_VM_L2_PERFCOUNTER0_CFG -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER1_CFG -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER2_CFG -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER3_CFG -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER4_CFG -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER5_CFG -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER6_CFG -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER7_CFG -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L -#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L -//MC_VM_L2_PERFCOUNTER_RSLT_CNTL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L - - -// addressBlock: gc_rlcpdec -//RLC_CNTL -#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 -#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 -#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 -#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 -#define RLC_CNTL__RESERVED__SHIFT 0x4 -#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L -#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L -#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L -#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L -#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L -//RLC_STAT -#define RLC_STAT__RLC_BUSY__SHIFT 0x0 -#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 -#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 -#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3 -#define RLC_STAT__MC_BUSY__SHIFT 0x4 -#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 -#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 -#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 -#define RLC_STAT__RESERVED__SHIFT 0x8 -#define RLC_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L -#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L -#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L -#define RLC_STAT__MC_BUSY_MASK 0x00000010L -#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L -#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L -#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L -#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L -//RLC_SAFE_MODE -#define RLC_SAFE_MODE__CMD__SHIFT 0x0 -#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 -#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 -#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 -#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc -#define RLC_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL -#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L -#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L -#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L -//RLC_MEM_SLP_CNTL -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 -#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 -#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L -#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L -#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL -#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L -#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L -#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L -//SMU_RLC_RESPONSE -#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 -#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL -//RLC_RLCV_SAFE_MODE -#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 -#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 -#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 -#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 -#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc -#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL -#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L -#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L -#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L -//RLC_SMU_SAFE_MODE -#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 -#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 -#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 -#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 -#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc -#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L -#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL -#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L -#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L -#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L -//RLC_RLCV_COMMAND -#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 -#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 -#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL -#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L -//RLC_REFCLOCK_TIMESTAMP_LSB -#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 -#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL -//RLC_REFCLOCK_TIMESTAMP_MSB -#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 -#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_INT_0 -#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_INT_1 -#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_INT_2 -#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_CTRL -#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 -#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 -#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 -#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 -#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 -#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L -#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L -#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L -#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L -#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L -//RLC_LB_CNTR_MAX -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 -#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL -//RLC_GPM_TIMER_STAT -#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 -#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 -#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 -#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 -#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4 -#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L -#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L -#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L -#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L -#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L -//RLC_GPM_TIMER_INT_3 -#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 -#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL -//RLC_SERDES_WR_NONCU_MASTER_MASK_1 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L -//RLC_SERDES_NONCU_MASTER_BUSY_1 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L -#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L -//RLC_INT_STAT -#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 -#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 -#define RLC_INT_STAT__RESERVED__SHIFT 0x9 -#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL -#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L -#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L -//RLC_LB_CNTL -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 -#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 -#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 -#define RLC_LB_CNTL__RESERVED__SHIFT 0xc -#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L -#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L -#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L -#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L -#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L -#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L -//RLC_MGCG_CTRL -#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 -#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 -#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 -#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 -#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 -#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 -#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L -#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L -#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L -#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L -#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L -#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L -#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L -#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L -//RLC_LB_CNTR_INIT -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 -#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL -//RLC_LOAD_BALANCE_CNTR -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 -#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL -//RLC_JUMP_TABLE_RESTORE -#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 -#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL -//RLC_PG_DELAY_2 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 -#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL -#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L -#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L -//RLC_GPU_CLOCK_COUNT_LSB -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 -#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL -//RLC_GPU_CLOCK_COUNT_MSB -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 -#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL -//RLC_CAPTURE_GPU_CLOCK_COUNT -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 -#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L -#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL -//RLC_UCODE_CNTL -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 -#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL -//RLC_GPM_THREAD_RESET -#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 -#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 -#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 -#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 -#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 -#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L -#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L -#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L -#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L -#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L -//RLC_GPM_CP_DMA_COMPLETE_T0 -#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 -#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 -#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L -#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPM_CP_DMA_COMPLETE_T1 -#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 -#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 -#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L -#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL -//RLC_FIREWALL_VIOLATION -#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 -#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL -//RLC_GPM_STAT -#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 -#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 -#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 -#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 -#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe -#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 -#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 -#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 -#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 -#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 -#define RLC_GPM_STAT__RESERVED__SHIFT 0x17 -#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 -#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L -#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L -#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L -#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L -#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L -#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L -#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L -#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L -#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L -#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L -#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L -#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L -#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L -#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L -#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L -#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L -#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L -#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L -#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L -#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L -#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L -#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L -#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L -//RLC_GPU_CLOCK_32_RES_SEL -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 -#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL -#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L -//RLC_GPU_CLOCK_32 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 -#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL -//RLC_PG_CNTL -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 -#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 -#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe -#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 -#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 -#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L -#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L -#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L -#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L -#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L -#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L -#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L -#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L -#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L -#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L -#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L -#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L -//RLC_GPM_THREAD_PRIORITY -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 -#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL -#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L -#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L -#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L -//RLC_GPM_THREAD_ENABLE -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 -#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 -#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L -#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L -#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L -#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L -#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L -//RLC_CGTT_MGCG_OVERRIDE -#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0 -#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 -#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 -#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8 -#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L -#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L -#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L -#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L -#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L -//RLC_CGCG_CGLS_CTRL -#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 -#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f -#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL -#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L -#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L -//RLC_CGCG_RAMP_CTRL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL -#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L -#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L -#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L -//RLC_DYN_PG_STATUS -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 -#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL -//RLC_DYN_PG_REQUEST -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 -#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL -//RLC_PG_DELAY -#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 -#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 -#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 -#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL -#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L -#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L -#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L -//RLC_CU_STATUS -#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 -#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL -//RLC_LB_INIT_CU_MASK -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 -#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL -//RLC_LB_ALWAYS_ACTIVE_CU_MASK -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 -#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL -//RLC_LB_PARAMS -#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 -#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 -#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L -#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL -#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L -#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L -//RLC_THREAD1_DELAY -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 -#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 -#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL -#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L -#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L -#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L -//RLC_PG_ALWAYS_ON_CU_MASK -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 -#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL -//RLC_MAX_PG_CU -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 -#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 -#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL -#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L -//RLC_AUTO_PG_CTRL -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 -#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L -#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L -#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L -#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L -#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L -//RLC_SMU_GRBM_REG_SAVE_CTRL -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 -#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L -#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL -//RLC_SERDES_RD_MASTER_INDEX -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 -#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 -#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL -#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L -#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L -#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L -#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L -#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L -#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L -//RLC_SERDES_RD_DATA_0 -#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 -#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_RD_DATA_1 -#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 -#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_RD_DATA_2 -#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 -#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_WR_CU_MASTER_MASK -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 -#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL -//RLC_SERDES_WR_NONCU_MASTER_MASK -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L -#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L -//RLC_SERDES_WR_CTRL -#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 -#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 -#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 -#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa -#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc -#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd -#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf -#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b -#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c -#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL -#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L -#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L -#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L -#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L -#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L -#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L -#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L -#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L -#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L -#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L -#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L -#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L -//RLC_SERDES_WR_DATA -#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 -#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_SERDES_CU_MASTER_BUSY -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 -#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL -//RLC_SERDES_NONCU_MASTER_BUSY -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 -#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 -#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a -#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L -#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L -#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L -#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L -#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L -//RLC_GPM_GENERAL_0 -#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_1 -#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_2 -#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_3 -#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_4 -#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_5 -#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_6 -#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_7 -#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_SCRATCH_ADDR -#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 -#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 -#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL -#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L -//RLC_GPM_SCRATCH_DATA -#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 -#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_STATIC_PG_STATUS -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 -#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL -//RLC_SPM_MC_CNTL -#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 -#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 -#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 -#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 -#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa -#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL -#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L -#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L -#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L -#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L -#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L -//RLC_SPM_INT_CNTL -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 -#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 -#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L -#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RLC_SPM_INT_STATUS -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 -#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 -#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L -#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL -//RLC_SMU_MESSAGE -#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 -#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL -//RLC_GPM_LOG_SIZE -#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 -#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL -//RLC_PG_DELAY_3 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 -#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 -#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL -#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L -//RLC_GPR_REG1 -#define RLC_GPR_REG1__DATA__SHIFT 0x0 -#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL -//RLC_GPR_REG2 -#define RLC_GPR_REG2__DATA__SHIFT 0x0 -#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_LOG_CONT -#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 -#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL -//RLC_GPM_INT_DISABLE_TH0 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 -#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL -//RLC_GPM_INT_DISABLE_TH1 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 -#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL -//RLC_GPM_INT_FORCE_TH0 -#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 -#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL -//RLC_GPM_INT_FORCE_TH1 -#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 -#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL -//RLC_SRM_CNTL -#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 -#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 -#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 -#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L -#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L -#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_ARAM_ADDR -#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 -#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc -#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL -#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L -//RLC_SRM_ARAM_DATA -#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 -#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_DRAM_ADDR -#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 -#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc -#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL -#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L -//RLC_SRM_DRAM_DATA -#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 -#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_GPM_COMMAND -#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 -#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 -#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 -#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f -#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L -#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL -#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L -#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L -#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L -#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L -//RLC_SRM_GPM_COMMAND_STATUS -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L -#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L -#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_RLCV_COMMAND -#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 -#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 -#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 -#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 -#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f -#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L -#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL -#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L -#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L -#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L -#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L -//RLC_SRM_RLCV_COMMAND_STATUS -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L -#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L -#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_INDEX_CNTL_ADDR_0 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_1 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_2 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_3 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_4 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_5 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_6 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_ADDR_7 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 -#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL -#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L -//RLC_SRM_INDEX_CNTL_DATA_0 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_1 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_2 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_3 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_4 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_5 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_6 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_INDEX_CNTL_DATA_7 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 -#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL -//RLC_SRM_STAT -#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 -#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 -#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 -#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L -#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L -#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL -//RLC_SRM_GPM_ABORT -#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 -#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 -#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L -#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL -//RLC_CSIB_ADDR_LO -#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 -#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL -//RLC_CSIB_ADDR_HI -#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 -#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL -//RLC_CSIB_LENGTH -#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 -#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL -//RLC_SMU_COMMAND -#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 -#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL -//RLC_CP_SCHEDULERS -#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 -#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 -#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 -#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 -#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL -#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L -#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L -#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L -//RLC_SMU_ARGUMENT_1 -#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 -#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL -//RLC_SMU_ARGUMENT_2 -#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 -#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_8 -#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_9 -#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_10 -#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_11 -#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_GENERAL_12 -#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 -#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_CNTL_0 -#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 -#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 -#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a -#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e -#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L -//RLC_GPM_UTCL1_CNTL_1 -#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 -#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 -#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a -#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e -#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L -//RLC_GPM_UTCL1_CNTL_2 -#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 -#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 -#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a -#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e -#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L -#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L -#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L -#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L -#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L -//RLC_SPM_UTCL1_CNTL -#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e -#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L -//RLC_UTCL1_STATUS_2 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 -#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L -#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L -#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L -#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L -#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L -#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L -#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L -//RLC_LB_THR_CONFIG_2 -#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL -//RLC_LB_THR_CONFIG_3 -#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL -//RLC_LB_THR_CONFIG_4 -#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL -//RLC_SPM_UTCL1_ERROR_1 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_SPM_UTCL1_ERROR_2 -#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH0_ERROR_1 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_LB_THR_CONFIG_1 -#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 -#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH0_ERROR_2 -#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH1_ERROR_1 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_GPM_UTCL1_TH1_ERROR_2 -#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_GPM_UTCL1_TH2_ERROR_1 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL -#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L -//RLC_GPM_UTCL1_TH2_ERROR_2 -#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 -#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL -//RLC_CGCG_CGLS_CTRL_3D -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c -#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d -#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L -#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L -#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L -#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L -#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L -//RLC_CGCG_RAMP_CTRL_3D -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL -#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L -#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L -#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L -//RLC_SEMAPHORE_0 -#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 -#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 -#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL -#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L -//RLC_SEMAPHORE_1 -#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 -#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 -#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL -#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L -//RLC_CP_EOF_INT -#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 -#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 -#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L -#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL -//RLC_CP_EOF_INT_CNT -#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 -#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL -//RLC_SPARE_INT -#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 -#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 -#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L -#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL -//RLC_PREWALKER_UTCL1_CNTL -#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 -#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 -#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a -#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d -#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e -#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL -#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L -#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L -#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L -#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L -#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L -#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L -//RLC_PREWALKER_UTCL1_TRIG -#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 -#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 -#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 -#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 -#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 -#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 -#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f -#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L -#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL -#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L -#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L -#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L -#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L -#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L -#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L -//RLC_PREWALKER_UTCL1_ADDR_LSB -#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL -//RLC_PREWALKER_UTCL1_ADDR_MSB -#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL -//RLC_PREWALKER_UTCL1_SIZE_LSB -#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL -//RLC_PREWALKER_UTCL1_SIZE_MSB -#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 -#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L -//RLC_DSM_TRIG -//RLC_UTCL1_STATUS -#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 -#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 -#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 -#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 -#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 -#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe -#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 -#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 -#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 -#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e -#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L -#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L -#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L -#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L -#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L -#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L -#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L -#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L -#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L -#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L -//RLC_R2I_CNTL_0 -#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL -//RLC_R2I_CNTL_1 -#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL -//RLC_R2I_CNTL_2 -#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL -//RLC_R2I_CNTL_3 -#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 -#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL -//RLC_UTCL2_CNTL -#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 -#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 -#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L -#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RLC_LBPW_CU_STAT -#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 -#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 -#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL -#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L -//RLC_DS_CNTL -#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 -#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 -#define RLC_DS_CNTL__RESRVED__SHIFT 0x2 -#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 -#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 -#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 -#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L -#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L -#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL -#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L -#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L -#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L -//RLC_RLCV_SPARE_INT -#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 -#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 -#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L -#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL - - -// addressBlock: gc_pwrdec -//CGTS_SM_CTRL_REG -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 -#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc -#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 -#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 -#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 -#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 -#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL -#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L -#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L -#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L -#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L -#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L -#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L -#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L -#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L -//CGTS_RD_CTRL_REG -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 -#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 -#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL -#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L -//CGTS_RD_REG -#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 -#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL -//CGTS_TCC_DISABLE -#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 -#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L -//CGTS_USER_TCC_DISABLE -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 -#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L -//CGTS_CU0_SP0_CTRL_REG -#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_LDS_SQ_CTRL_REG -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_TA_SQC_CTRL_REG -#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_SP1_CTRL_REG -#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_TD_TCP_CTRL_REG -#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_SP0_CTRL_REG -#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_LDS_SQ_CTRL_REG -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_TA_SQC_CTRL_REG -#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU1_SP1_CTRL_REG -#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU1_TD_TCP_CTRL_REG -#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_SP0_CTRL_REG -#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_LDS_SQ_CTRL_REG -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_TA_SQC_CTRL_REG -#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU2_SP1_CTRL_REG -#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU2_TD_TCP_CTRL_REG -#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_SP0_CTRL_REG -#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_LDS_SQ_CTRL_REG -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_TA_SQC_CTRL_REG -#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_SP1_CTRL_REG -#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU3_TD_TCP_CTRL_REG -#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_SP0_CTRL_REG -#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_LDS_SQ_CTRL_REG -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_TA_SQC_CTRL_REG -#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU4_SP1_CTRL_REG -#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU4_TD_TCP_CTRL_REG -#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_SP0_CTRL_REG -#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_LDS_SQ_CTRL_REG -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_TA_SQC_CTRL_REG -#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU5_SP1_CTRL_REG -#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU5_TD_TCP_CTRL_REG -#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_SP0_CTRL_REG -#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_LDS_SQ_CTRL_REG -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_TA_SQC_CTRL_REG -#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_SP1_CTRL_REG -#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU6_TD_TCP_CTRL_REG -#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_SP0_CTRL_REG -#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_LDS_SQ_CTRL_REG -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_TA_SQC_CTRL_REG -#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU7_SP1_CTRL_REG -#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU7_TD_TCP_CTRL_REG -#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_SP0_CTRL_REG -#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_LDS_SQ_CTRL_REG -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_TA_SQC_CTRL_REG -#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU8_SP1_CTRL_REG -#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU8_TD_TCP_CTRL_REG -#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_SP0_CTRL_REG -#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_LDS_SQ_CTRL_REG -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_TA_SQC_CTRL_REG -#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_SP1_CTRL_REG -#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU9_TD_TCP_CTRL_REG -#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_SP0_CTRL_REG -#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_LDS_SQ_CTRL_REG -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_TA_SQC_CTRL_REG -#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU10_SP1_CTRL_REG -#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU10_TD_TCP_CTRL_REG -#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_SP0_CTRL_REG -#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_LDS_SQ_CTRL_REG -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_TA_SQC_CTRL_REG -#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU11_SP1_CTRL_REG -#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU11_TD_TCP_CTRL_REG -#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_SP0_CTRL_REG -#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_LDS_SQ_CTRL_REG -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_TA_SQC_CTRL_REG -#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_SP1_CTRL_REG -#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU12_TD_TCP_CTRL_REG -#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_SP0_CTRL_REG -#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_LDS_SQ_CTRL_REG -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_TA_SQC_CTRL_REG -#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU13_SP1_CTRL_REG -#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU13_TD_TCP_CTRL_REG -#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_SP0_CTRL_REG -#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_LDS_SQ_CTRL_REG -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_TA_SQC_CTRL_REG -#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -//CGTS_CU14_SP1_CTRL_REG -#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU14_TD_TCP_CTRL_REG -#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_SP0_CTRL_REG -#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL -#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_LDS_SQ_CTRL_REG -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_TA_SQC_CTRL_REG -#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_SP1_CTRL_REG -#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL -#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU15_TD_TCP_CTRL_REG -#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L -#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L -//CGTS_CU0_TCPI_CTRL_REG -#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU1_TCPI_CTRL_REG -#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU2_TCPI_CTRL_REG -#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU3_TCPI_CTRL_REG -#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU4_TCPI_CTRL_REG -#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU5_TCPI_CTRL_REG -#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU6_TCPI_CTRL_REG -#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU7_TCPI_CTRL_REG -#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU8_TCPI_CTRL_REG -#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU9_TCPI_CTRL_REG -#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU10_TCPI_CTRL_REG -#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU11_TCPI_CTRL_REG -#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU12_TCPI_CTRL_REG -#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU13_TCPI_CTRL_REG -#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU14_TCPI_CTRL_REG -#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTS_CU15_TCPI_CTRL_REG -#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb -#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L -#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L -#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L -//CGTT_SPI_CLK_CTRL -#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L -#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L -#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L -#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L -#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L -#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L -#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_PC_CLK_CTRL -#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 -#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 -#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L -#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L -#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L -#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L -#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_BCI_CLK_CTRL -#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L -#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L -#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L -#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L -#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L -#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L -#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L -#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_VGT_CLK_CTRL -#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a -#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L -#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L -#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L -#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L -#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L -#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_IA_CLK_CTRL -#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_WD_CLK_CTRL -#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a -#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L -#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L -#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L -#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L -#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L -#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L -#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_PA_CLK_CTRL -#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f -#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L -#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L -//CGTT_SC_CLK_CTRL0 -#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 -#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 -#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e -#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f -#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL -#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L -#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L -#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L -#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L -#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L -//CGTT_SC_CLK_CTRL1 -#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 -#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 -#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d -#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e -#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL -#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L -#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L -#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L -#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L -#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L -#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L -#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L -#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L -//CGTT_SQ_CLK_CTRL -#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L -#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//CGTT_SQG_CLK_CTRL -#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f -#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L -#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L -#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L -#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L -//SQ_ALU_CLK_CTRL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL -#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L -//SQ_TEX_CLK_CTRL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL -#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L -//SQ_LDS_CLK_CTRL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL -#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L -//SQ_POWER_THROTTLE -#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 -#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 -#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e -#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL -#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L -#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L -//SQ_POWER_THROTTLE2 -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f -#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L -//CGTT_SX_CLK_CTRL0 -#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL1 -#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL2 -#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL3 -#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_SX_CLK_CTRL4 -#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL -#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L -//TD_CGTT_CTRL -#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 -#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL -#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//TA_CGTT_CTRL -#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 -#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL -#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_TCPI_CLK_CTRL -#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_TCI_CLK_CTRL -#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_GDS_CLK_CTRL -#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//DB_CGTT_CLK_CTRL_0 -#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 -#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f -#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL -#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L -#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L -//CB_CGTT_SCLK_CTRL -#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//TCC_CGTT_SCLK_CTRL -#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//TCA_CGTT_SCLK_CTRL -#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_CP_CLK_CTRL -#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//CGTT_CPF_CLK_CTRL -#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//CGTT_CPC_CLK_CTRL -#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//RLC_PWR_CTRL -#define RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT 0x0 -#define RLC_PWR_CTRL__RESERVED__SHIFT 0x1 -#define RLC_PWR_CTRL__DLDO_STATUS__SHIFT 0x8 -#define RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK 0x00000001L -#define RLC_PWR_CTRL__RESERVED_MASK 0x000000FEL -#define RLC_PWR_CTRL__DLDO_STATUS_MASK 0x00000100L -//CGTT_RLC_CLK_CTRL -#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f -#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L -#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L -//RLC_GFX_RM_CNTL -#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 -#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 -#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L -#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RMI_CGTT_SCLK_CTRL -#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 -#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//CGTT_TCPF_CLK_CTRL -#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L -#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L - - -// addressBlock: gc_ea_pwrdec -//GCEA_CGTT_CLK_CTRL -#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f -#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L -#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L - - -// addressBlock: gc_utcl2_vmsharedhvdec -//MC_VM_FB_SIZE_OFFSET_VF0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF1 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF2 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF3 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF4 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF5 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF6 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF7 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF8 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF9 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF11 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF12 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF13 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF14 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L -//MC_VM_FB_SIZE_OFFSET_VF15 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL -#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L -//VM_IOMMU_MMIO_CNTRL_1 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 -#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L -//MC_VM_MARC_BASE_LO_0 -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_1 -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_2 -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_LO_3 -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc -#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_BASE_HI_0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_1 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_2 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_BASE_HI_3 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 -#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_LO_0 -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_1 -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_2 -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_LO_3 -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc -#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L -#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L -#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_RELOC_HI_0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_1 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_2 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_RELOC_HI_3 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 -#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_LO_0 -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_1 -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_2 -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_LO_3 -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc -#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L -//MC_VM_MARC_LEN_HI_0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_1 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_2 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL -//MC_VM_MARC_LEN_HI_3 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 -#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL -//VM_IOMMU_CONTROL_REGISTER -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 -#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L -//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd -#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L -//VM_PCIE_ATS_CNTL -#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 -#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L -#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_0 -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_1 -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_2 -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_3 -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_4 -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_5 -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_6 -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_7 -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_8 -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_9 -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_10 -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_11 -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_12 -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_13 -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_14 -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L -//VM_PCIE_ATS_CNTL_VF_15 -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f -#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L -//UTCL2_CGTT_CLK_CTRL -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 -#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L -#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L -#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L - - -// addressBlock: gc_hypdec -//CP_HYP_PFP_UCODE_ADDR -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL -//CP_PFP_UCODE_ADDR -#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL -//CP_HYP_PFP_UCODE_DATA -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_PFP_UCODE_DATA -#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_ME_UCODE_ADDR -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL -//CP_ME_RAM_RADDR -#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 -#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL -//CP_ME_RAM_WADDR -#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 -#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL -//CP_HYP_ME_UCODE_DATA -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_ME_RAM_DATA -#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 -#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL -//CP_CE_UCODE_ADDR -#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL -//CP_HYP_CE_UCODE_ADDR -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL -//CP_CE_UCODE_DATA -#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_CE_UCODE_DATA -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_MEC1_UCODE_ADDR -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_MEC_ME1_UCODE_ADDR -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_HYP_MEC1_UCODE_DATA -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_MEC_ME1_UCODE_DATA -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_HYP_MEC2_UCODE_ADDR -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_MEC_ME2_UCODE_ADDR -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL -//CP_HYP_MEC2_UCODE_DATA -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//CP_MEC_ME2_UCODE_DATA -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//RLC_GPM_UCODE_ADDR -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe -#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL -#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L -//RLC_GPM_UCODE_DATA -#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//GRBM_GFX_INDEX_SR_SELECT -#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 -#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L -//GRBM_GFX_INDEX_SR_DATA -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 -#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 -#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 -#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e -#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL -#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L -#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L -#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L -#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L -#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L -//GRBM_GFX_CNTL_SR_SELECT -#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 -#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L -//GRBM_GFX_CNTL_SR_DATA -#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 -#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 -#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 -#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 -#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L -#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL -#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L -#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L -//GRBM_CAM_INDEX -#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 -#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L -//GRBM_HYP_CAM_INDEX -#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 -#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L -//GRBM_CAM_DATA -#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 -#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 -#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL -#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L -//GRBM_HYP_CAM_DATA -#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 -#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL -#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L -//RLC_GPU_IOV_VF_ENABLE -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 -#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 -#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL -#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L -//RLC_GFX_RM_CNTL_ADJ -#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT 0x0 -#define RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT 0x1 -#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK 0x00000001L -#define RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_CFG_REG6 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 -#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 -#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa -#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL -#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L -#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L -#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L -//RLC_GPU_IOV_CFG_REG8 -#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL -//RLC_RLCV_TIMER_INT_0 -#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 -#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL -//RLC_RLCV_TIMER_CTRL -#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 -#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1 -#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L -#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL -//RLC_RLCV_TIMER_STAT -#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 -#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1 -#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L -#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_VF_DOORBELL_STATUS -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L -//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L -//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L -//RLC_GPU_IOV_VF_MASK -#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 -#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L -//RLC_HYP_SEMAPHORE_2 -#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 -#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 -#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL -#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L -//RLC_HYP_SEMAPHORE_3 -#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 -#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 -#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL -#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L -//RLC_CLK_CNTL -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1 -#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2 -#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L -#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L -#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL -//RLC_GPU_IOV_SCH_BLOCK -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 -#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L -#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L -#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L -//RLC_GPU_IOV_CFG_REG1 -#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 -#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 -#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 -#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 -#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 -#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L -#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L -#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L -#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L -#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L -#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L -//RLC_GPU_IOV_CFG_REG2 -#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 -#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL -#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L -//RLC_GPU_IOV_VM_BUSY_STATUS -#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCH_0 -#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_ACTIVE_FCN_ID -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f -#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL -#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L -//RLC_GPU_IOV_SCH_3 -#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCH_1 -#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCH_2 -#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_UCODE_ADDR -#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 -#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc -#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL -#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L -//RLC_GPU_IOV_UCODE_DATA -#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 -#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SCRATCH_ADDR -#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 -#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 -#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL -#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L -//RLC_GPU_IOV_SCRATCH_DATA -#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 -#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_F32_CNTL -#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 -#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L -#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_F32_RESET -#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 -#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L -#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL -//RLC_GPU_IOV_SDMA0_STATUS -#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 -#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd -#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL -#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L -#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L -#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L -//RLC_GPU_IOV_SDMA1_STATUS -#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 -#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 -#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd -#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL -#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L -#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L -#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L -//RLC_GPU_IOV_SMU_RESPONSE -#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 -#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_VIRT_RESET_REQ -#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 -#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 -#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f -#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL -#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L -#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L -//RLC_GPU_IOV_RLC_RESPONSE -#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 -#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_INT_DISABLE -#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 -#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_INT_FORCE -#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 -#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SDMA0_BUSY_STATUS -#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL -//RLC_GPU_IOV_SDMA1_BUSY_STATUS -#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 -#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL - - -// addressBlock: gccacind -//GC_CAC_CNTL -#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 -#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 -#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 -#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 -#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f -#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L -#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL -#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L -#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L -#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L -//GC_CAC_OVR_SEL -#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 -#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL -//GC_CAC_OVR_VAL -#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 -#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_BCI_0 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CB_0 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CB_1 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CP_0 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CP_1 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_DB_0 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_DB_1 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_GDS_0 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_GDS_1 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_IA_0 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_LDS_0 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_LDS_1 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_PA_0 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_PC_0 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SC_0 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SPI_0 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SPI_1 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SPI_2 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_0 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_1 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_2 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_3 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SQ_4 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SX_0 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_SXRB_0 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TA_0 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCC_0 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCC_1 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCC_2 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCP_0 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCP_1 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TCP_2 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TD_0 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TD_1 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_TD_2 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_VGT_0 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_VGT_1 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_WD_0 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10 -#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_0 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_1 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_2 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_3 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_4 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_CU_5 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10 -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L -//GC_CAC_ACC_BCI0 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB0 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB1 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB2 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CB3 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CP0 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CP1 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CP2 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB0 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB1 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB2 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_DB3 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS0 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS1 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS2 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_GDS3 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_IA0 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS0 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS1 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS2 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_LDS3 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_PA0 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_PA1 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_PC0 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SC0 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI0 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI1 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI2 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI3 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI4 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SPI5 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_PG_0 -#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_PG_0__unused__SHIFT 0x10 -#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_PG_0__unused_MASK 0xFFFF0000L -//GC_CAC_ACC_PG0 -#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_PG -#define GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT 0x10 -#define GC_CAC_OVRD_PG__OVRRD_SELECT_MASK 0x0000FFFFL -#define GC_CAC_OVRD_PG__OVRRD_VALUE_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ATCL2_0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L -//GC_CAC_ACC_EA0 -#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA1 -#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA2 -#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA3 -#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ATCL20 -#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_EA -#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 -#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL -#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L -//GC_CAC_OVRD_UTCL2_ATCL2 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_WEIGHT_EA_0 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_EA_1 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_RMI_0 -#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10 -#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L -//GC_CAC_ACC_RMI0 -#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_RMI -#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_WEIGHT_UTCL2_ATCL2_1 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L -//GC_CAC_ACC_UTCL2_ATCL21 -#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ATCL22 -#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ATCL23 -#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA4 -#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_EA5 -#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_EA_2 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L -//GC_CAC_ACC_SQ0_LOWER -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ0_UPPER -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ1_LOWER -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ1_UPPER -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ2_LOWER -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ2_UPPER -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ3_LOWER -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ3_UPPER -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ4_LOWER -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ4_UPPER -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ5_LOWER -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ5_UPPER -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ6_LOWER -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ6_UPPER -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ7_LOWER -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ7_UPPER -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SQ8_LOWER -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SQ8_UPPER -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8 -#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL -#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L -//GC_CAC_ACC_SX0 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SXRB0 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_SXRB1 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TA0 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC0 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC1 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC2 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC3 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCC4 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP0 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP1 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP2 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP3 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TCP4 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD0 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD1 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD2 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD3 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD4 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_TD5 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_VGT0 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_VGT1 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_VGT2 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_WD0 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU0 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU1 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU2 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU3 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU4 -#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU5 -#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU6 -#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU7 -#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU8 -#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU9 -#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_CU10 -#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_BCI -#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 -#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L -#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL -//GC_CAC_OVRD_CB -#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_CP -#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 -#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L -#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L -//GC_CAC_OVRD_DB -#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_GDS -#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_IA -#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_LDS -#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 -#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL -#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L -//GC_CAC_OVRD_PA -#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 -#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L -#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL -//GC_CAC_OVRD_PC -#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SC -#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SPI -#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 -#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL -#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L -//GC_CAC_OVRD_CU -#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SQ -#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 -#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL -#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L -//GC_CAC_OVRD_SX -#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_SXRB -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_TA -#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_OVRD_TCC -#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_OVRD_TCP -#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_OVRD_TD -#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 -#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL -#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L -//GC_CAC_OVRD_VGT -#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 -#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L -#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L -//GC_CAC_OVRD_WD -#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 -#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L -#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L -//GC_CAC_ACC_BCI1 -#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_WEIGHT_UTCL2_ATCL2_2 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_1 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_2 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_3 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_ROUTER_4 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_VML2_0 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_VML2_1 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_VML2_2 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L -//GC_CAC_ACC_UTCL2_ATCL24 -#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER0 -#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER1 -#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER2 -#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER3 -#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER4 -#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER5 -#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER6 -#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER7 -#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER8 -#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_ROUTER9 -#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML20 -#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML21 -#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML22 -#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML23 -#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_VML24 -#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_UTCL2_ROUTER -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL -#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L -//GC_CAC_OVRD_UTCL2_VML2 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L -//GC_CAC_WEIGHT_UTCL2_WALKER_0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_WALKER_1 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L -//GC_CAC_WEIGHT_UTCL2_WALKER_2 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10 -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL -#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L -//GC_CAC_ACC_UTCL2_WALKER0 -#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER1 -#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER2 -#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER3 -#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_ACC_UTCL2_WALKER4 -#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 -#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL -//GC_CAC_OVRD_UTCL2_WALKER -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL -#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L - - -// addressBlock: secacind -//SE_CAC_CNTL -#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 -#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 -#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 -#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 -#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f -#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L -#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL -#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L -#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L -#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L -//SE_CAC_OVR_SEL -#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 -#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL -//SE_CAC_OVR_VAL -#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 -#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL - - -// addressBlock: sqind -//SQ_WAVE_MODE -#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 -#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 -#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 -#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 -#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa -#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc -#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 -#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 -#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 -#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a -#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b -#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c -#define SQ_WAVE_MODE__CSP__SHIFT 0x1d -#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL -#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L -#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L -#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L -#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L -#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L -#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L -#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L -#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L -#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L -#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L -#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L -#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L -//SQ_WAVE_STATUS -#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 -#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 -#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 -#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 -#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 -#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 -#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 -#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 -#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa -#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb -#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc -#define SQ_WAVE_STATUS__HALT__SHIFT 0xd -#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe -#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf -#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 -#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 -#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 -#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 -#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 -#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 -#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b -#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L -#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L -#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L -#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L -#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L -#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L -#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L -#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L -#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L -#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L -#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L -#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L -#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L -#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L -#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L -#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L -#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L -#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L -#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L -#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L -#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L -//SQ_WAVE_TRAPSTS -#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 -#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa -#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb -#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 -#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c -#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d -#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL -#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L -#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L -#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L -#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L -#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L -#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L -//SQ_WAVE_HW_ID -#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 -#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 -#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 -#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 -#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc -#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd -#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 -#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 -#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 -#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b -#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e -#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL -#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L -#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L -#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L -#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L -#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L -#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L -#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L -#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L -#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L -#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L -//SQ_WAVE_GPR_ALLOC -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 -#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL -#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L -#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L -#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L -//SQ_WAVE_LDS_ALLOC -#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc -#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL -#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L -//SQ_WAVE_IB_STS -#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 -#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 -#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 -#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc -#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf -#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 -#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 -#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL -#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L -#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L -#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L -#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L -#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L -#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L -//SQ_WAVE_PC_LO -#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 -#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL -//SQ_WAVE_PC_HI -#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 -#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL -//SQ_WAVE_INST_DW0 -#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 -#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL -//SQ_WAVE_INST_DW1 -#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 -#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL -//SQ_WAVE_IB_DBG0 -#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 -#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 -#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 -#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa -#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 -#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 -#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a -#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b -#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f -#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L -#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L -#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L -#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L -#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L -#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L -#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L -#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L -#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L -#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L -#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L -#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L -//SQ_WAVE_IB_DBG1 -#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 -#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 -#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 -#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb -#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 -#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 -#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L -#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L -#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L -#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L -#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L -#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L -#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L -//SQ_WAVE_FLUSH_IB -#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 -#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP0 -#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP1 -#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP2 -#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP3 -#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP4 -#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP5 -#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP6 -#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP7 -#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP8 -#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP9 -#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP10 -#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP11 -#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP12 -#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP13 -#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP14 -#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_TTMP15 -#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 -#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL -//SQ_WAVE_M0 -#define SQ_WAVE_M0__M0__SHIFT 0x0 -#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL -//SQ_WAVE_EXEC_LO -#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 -#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL -//SQ_WAVE_EXEC_HI -#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 -#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL -//SQ_INTERRUPT_WORD_AUTO_CTXID -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L -#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L -//SQ_INTERRUPT_WORD_AUTO_HI -#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa -#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L -#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L -//SQ_INTERRUPT_WORD_AUTO_LO -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 -#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 -#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 -#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L -#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L -#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L -#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L -#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L -#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L -#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L -//SQ_INTERRUPT_WORD_CMN_CTXID -#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L -#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L -//SQ_INTERRUPT_WORD_CMN_HI -#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa -#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L -#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L -//SQ_INTERRUPT_WORD_WAVE_CTXID -#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc -#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd -#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L -#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L -//SQ_INTERRUPT_WORD_WAVE_HI -#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 -#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 -#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa -#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL -#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L -#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L -#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L -//SQ_INTERRUPT_WORD_WAVE_LO -#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 -#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 -#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 -#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a -#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e -#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL -#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L -#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L - - - - - - - - -// addressBlock: didtind -//DIDT_SQ_CTRL0 -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_SQ_CTRL1 -#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_SQ_CTRL2 -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_SQ_STALL_CTRL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_SQ_TUNING_CTRL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_SQ_STALL_AUTO_RELEASE_CTRL -#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_SQ_CTRL3 -#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_SQ_STALL_PATTERN_1_2 -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_STALL_PATTERN_3_4 -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_STALL_PATTERN_5_6 -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_STALL_PATTERN_7 -#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_SQ_WEIGHT0_3 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_SQ_WEIGHT4_7 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_SQ_WEIGHT8_11 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_SQ_EDC_CTRL -#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_SQ_EDC_THRESHOLD -#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_SQ_EDC_STALL_PATTERN_1_2 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_EDC_STALL_PATTERN_3_4 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_EDC_STALL_PATTERN_5_6 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_SQ_EDC_STALL_PATTERN_7 -#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_SQ_EDC_STATUS -#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_SQ_EDC_STALL_DELAY_1 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12 -#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L -#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L -#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L -//DIDT_SQ_EDC_STALL_DELAY_2 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12 -#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L -#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L -#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L -//DIDT_SQ_EDC_STALL_DELAY_3 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0xc -#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L -#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x0003F000L -#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L -//DIDT_SQ_EDC_OVERFLOW -#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_SQ_EDC_ROLLING_POWER_DELTA -#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_DB_CTRL0 -#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_DB_CTRL1 -#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_DB_CTRL2 -#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_DB_STALL_CTRL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_DB_TUNING_CTRL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_DB_STALL_AUTO_RELEASE_CTRL -#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_DB_CTRL3 -#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_DB_STALL_PATTERN_1_2 -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DB_STALL_PATTERN_3_4 -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DB_STALL_PATTERN_5_6 -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DB_STALL_PATTERN_7 -#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DB_WEIGHT0_3 -#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_DB_WEIGHT4_7 -#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_DB_WEIGHT8_11 -#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_DB_EDC_CTRL -#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_DB_EDC_THRESHOLD -#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_DB_EDC_STALL_PATTERN_1_2 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DB_EDC_STALL_PATTERN_3_4 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DB_EDC_STALL_PATTERN_5_6 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DB_EDC_STALL_PATTERN_7 -#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DB_EDC_STATUS -#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_DB_EDC_STALL_DELAY_1 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x3 -#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6 -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x00000007L -#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000038L -#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L -//DIDT_DB_EDC_OVERFLOW -#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_DB_EDC_ROLLING_POWER_DELTA -#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_TD_CTRL0 -#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_TD_CTRL1 -#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_TD_CTRL2 -#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_TD_STALL_CTRL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_TD_TUNING_CTRL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_TD_STALL_AUTO_RELEASE_CTRL -#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_TD_CTRL3 -#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_TD_STALL_PATTERN_1_2 -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TD_STALL_PATTERN_3_4 -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TD_STALL_PATTERN_5_6 -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TD_STALL_PATTERN_7 -#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TD_WEIGHT0_3 -#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_TD_WEIGHT4_7 -#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_TD_WEIGHT8_11 -#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_TD_EDC_CTRL -#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_TD_EDC_THRESHOLD -#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_TD_EDC_STALL_PATTERN_1_2 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TD_EDC_STALL_PATTERN_3_4 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TD_EDC_STALL_PATTERN_5_6 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TD_EDC_STALL_PATTERN_7 -#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TD_EDC_STATUS -#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_TD_EDC_STALL_DELAY_1 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12 -#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L -#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L -#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L -//DIDT_TD_EDC_STALL_DELAY_2 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12 -#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L -#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L -#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L -//DIDT_TD_EDC_STALL_DELAY_3 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0xc -#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L -#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x0003F000L -#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L -//DIDT_TD_EDC_OVERFLOW -#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_TD_EDC_ROLLING_POWER_DELTA -#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_TCP_CTRL0 -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_TCP_CTRL1 -#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_TCP_CTRL2 -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_TCP_STALL_CTRL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_TCP_TUNING_CTRL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_TCP_STALL_AUTO_RELEASE_CTRL -#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_TCP_CTRL3 -#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_TCP_STALL_PATTERN_1_2 -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_STALL_PATTERN_3_4 -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_STALL_PATTERN_5_6 -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_STALL_PATTERN_7 -#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TCP_WEIGHT0_3 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_TCP_WEIGHT4_7 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_TCP_WEIGHT8_11 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_TCP_EDC_CTRL -#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_TCP_EDC_THRESHOLD -#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_TCP_EDC_STALL_PATTERN_1_2 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_EDC_STALL_PATTERN_3_4 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_EDC_STALL_PATTERN_5_6 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_TCP_EDC_STALL_PATTERN_7 -#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_TCP_EDC_STATUS -#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -//DIDT_TCP_EDC_STALL_DELAY_1 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12 -#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L -#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L -#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L -//DIDT_TCP_EDC_STALL_DELAY_2 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12 -#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L -#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L -#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L -//DIDT_TCP_EDC_STALL_DELAY_3 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0xc -#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L -#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x0003F000L -#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L -//DIDT_TCP_EDC_OVERFLOW -#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_TCP_EDC_ROLLING_POWER_DELTA -#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_DBR_CTRL0 -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 -#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1 -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 -#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 -#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 -#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 -#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 -#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a -#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b -#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L -#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L -#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L -#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L -#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L -#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L -#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L -#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L -#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L -#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L -#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L -//DIDT_DBR_CTRL1 -#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 -#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 -#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL -#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L -//DIDT_DBR_CTRL2 -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 -#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 -#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b -#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f -#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL -#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L -#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L -#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L -#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L -#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L -//DIDT_DBR_STALL_CTRL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 -#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18 -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL -#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L -#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L -#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L -//DIDT_DBR_TUNING_CTRL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL -#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L -//DIDT_DBR_STALL_AUTO_RELEASE_CTRL -#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 -#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL -//DIDT_DBR_CTRL3 -#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 -#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 -#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2 -#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 -#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe -#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 -#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 -#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 -#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b -#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c -#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L -#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L -#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL -#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L -#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L -#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L -#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L -#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L -#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L -#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L -//DIDT_DBR_STALL_PATTERN_1_2 -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_STALL_PATTERN_3_4 -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_STALL_PATTERN_5_6 -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_STALL_PATTERN_7 -#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DBR_WEIGHT0_3 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 -#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 -#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 -#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 -#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL -#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L -#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L -#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L -//DIDT_DBR_WEIGHT4_7 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 -#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 -#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 -#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 -#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL -#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L -#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L -#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L -//DIDT_DBR_WEIGHT8_11 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 -#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 -#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 -#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 -#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL -#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L -#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L -#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L -//DIDT_DBR_EDC_CTRL -#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0 -#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 -#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 -#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 -#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 -#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 -#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 -#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 -#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 -#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 -#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 -#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17 -#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L -#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L -#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L -#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L -#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L -#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L -#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L -#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L -#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L -#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L -//DIDT_DBR_EDC_THRESHOLD -#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 -#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL -//DIDT_DBR_EDC_STALL_PATTERN_1_2 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L -#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_EDC_STALL_PATTERN_3_4 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L -#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_EDC_STALL_PATTERN_5_6 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L -#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L -//DIDT_DBR_EDC_STALL_PATTERN_7 -#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf -#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL -#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L -//DIDT_DBR_EDC_STATUS -#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 -#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 -#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4 -#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L -#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL -#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L -//DIDT_DBR_EDC_STALL_DELAY_1 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0 -#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x1 -#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000001L -#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFFEL -//DIDT_DBR_EDC_OVERFLOW -#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 -#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 -#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L -#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL -//DIDT_DBR_EDC_ROLLING_POWER_DELTA -#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 -#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL -//DIDT_SQ_STALL_EVENT_COUNTER -#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_DB_STALL_EVENT_COUNTER -#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_TD_STALL_EVENT_COUNTER -#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_TCP_STALL_EVENT_COUNTER -#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL -//DIDT_DBR_STALL_EVENT_COUNTER -#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 -#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL - - - - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h deleted file mode 100644 index 392ef7721f53..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/MMHUB/mmhub_9_1_default.h +++ /dev/null @@ -1,1028 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mmhub_9_1_DEFAULT_HEADER -#define _mmhub_9_1_DEFAULT_HEADER - - -// addressBlock: mmhub_dagbdec -#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI19_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI20_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI21_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI22_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI23_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI24_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI25_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI26_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI27_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI28_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI29_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI30_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RDCLI31_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 -#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 -#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888 -#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111 -#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI19_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI20_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI21_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI22_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI23_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI24_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI25_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI26_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI27_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI28_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI29_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI30_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WRCLI31_DEFAULT 0xfe5fe0f9 -#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 -#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f -#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 -#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 -#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 -#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 -#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_DEFAULT 0x88888888 -#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000 -#define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_DEFAULT 0x11111111 -#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_DEFAULT 0x00000000 -#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 -#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408 -#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 -#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870 -#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 -#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 -#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 -#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa -#define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 -#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff -#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 -#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff -#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff -#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmDAGB0_RESERVE0_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE1_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE2_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE3_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE4_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE5_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE6_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE7_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE8_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE9_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE10_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE11_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE12_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE13_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE14_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE15_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE16_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE17_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE18_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE19_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE20_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE21_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE22_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE23_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE24_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE25_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE26_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE27_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE28_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE29_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE30_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE31_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE32_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE33_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE34_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE35_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE36_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE37_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE38_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE39_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE40_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE41_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE42_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE43_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE44_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE45_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE46_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE47_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE48_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE49_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE50_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE51_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE52_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE53_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE54_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE55_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE56_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE57_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE58_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE59_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE60_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE61_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE62_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE63_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE64_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE65_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE66_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE67_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE68_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE69_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE70_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE71_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE72_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE73_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE74_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE75_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE76_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE77_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE78_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE79_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE80_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE81_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE82_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE83_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE84_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE85_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE86_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE87_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE88_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE89_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE90_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE91_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE92_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE93_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE94_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE95_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE96_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE97_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE98_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE99_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE100_DEFAULT 0x00000000 -#define mmDAGB0_RESERVE101_DEFAULT 0x00000000 - - -// addressBlock: mmhub_ea_mmeadec -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 -#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf -#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmMMEA0_MISC_DEFAULT 0x00180130 -#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 -#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 -#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000 -#define mmMMEA0_MISC2_DEFAULT 0x00000000 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 -#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 -#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 -#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 -#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef -#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 -#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 -#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 -#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 -#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 -#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 -#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 -#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 -#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 -#define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff -#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f -#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f -#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff -#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040 -#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff -#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 -#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf -#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 -#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 -#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f -#define mmMMEA1_MISC_DEFAULT 0x00180130 -#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 -#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 -#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 -#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 -#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 -#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000 -#define mmMMEA1_MISC2_DEFAULT 0x00000000 - - -// addressBlock: mmhub_pctldec -#define mmPCTL_MISC_DEFAULT 0x00000889 -#define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 -#define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 -#define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 -#define mmPCTL_PG_DAGB_DEFAULT 0x00000000 -#define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL0_MISC_DEFAULT 0x00001000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff -#define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL1_MISC_DEFAULT 0x00000800 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 -#define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff -#define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 -#define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 -#define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 -#define mmPCTL2_MISC_DEFAULT 0x00000800 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a -#define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff -#define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff - - -// addressBlock: mmhub_l1tlb_vml1dec -#define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 - - -// addressBlock: mmhub_l1tlb_vml1pldec -#define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: mmhub_l1tlb_vml1prdec -#define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_l1tlb_vmtlspfdec -#define mmVM_L2_SAW_CNTL_DEFAULT 0x0c0b8602 -#define mmVM_L2_SAW_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CNTL3_DEFAULT 0x80100004 -#define mmVM_L2_SAW_CNTL4_DEFAULT 0x00000001 -#define mmVM_L2_SAW_CONTEXT0_CNTL_DEFAULT 0x00fffed8 -#define mmVM_L2_SAW_CONTEXT0_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_SAW_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_L2_SAW_PIPES_BUSY_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_atcl2dec -#define mmATC_L2_CNTL_DEFAULT 0x000001c9 -#define mmATC_L2_CNTL2_DEFAULT 0x00000100 -#define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 -#define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 -#define mmATC_L2_CNTL3_DEFAULT 0x000001f8 -#define mmATC_L2_STATUS_DEFAULT 0x00000000 -#define mmATC_L2_STATUS2_DEFAULT 0x00000000 -#define mmATC_L2_MISC_CG_DEFAULT 0x00000200 -#define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vml2pfdec -#define mmVM_L2_CNTL_DEFAULT 0x00080602 -#define mmVM_L2_CNTL2_DEFAULT 0x00000000 -#define mmVM_L2_CNTL3_DEFAULT 0x80100007 -#define mmVM_L2_STATUS_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc -#define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff -#define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 -#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 -#define mmVM_L2_CNTL4_DEFAULT 0x000000c1 -#define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 -#define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 -#define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 -#define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vml2vcdec -#define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 -#define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 -#define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 -#define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 -#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vml2pldec -#define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - - -// addressBlock: mmhub_utcl2_vml2prdec -#define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vmsharedhvdec -#define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 -#define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 -#define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 -#define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 -#define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 -#define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 - - -// addressBlock: mmhub_utcl2_vmsharedpfdec -#define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 -#define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 -#define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 -#define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 -#define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 -#define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 -#define mmMC_VM_STEERING_DEFAULT 0x00000001 -#define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 -#define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 -#define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff -#define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_vmsharedvcdec -#define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 -#define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 -#define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 - - -// addressBlock: mmhub_utcl2_atcl2pfcntrdec -#define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 - - -// addressBlock: mmhub_utcl2_atcl2pfcntldec -#define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h deleted file mode 100644 index 1445bba8f41f..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_sh_mask.h +++ /dev/null @@ -1,1658 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_1_SH_MASK_HEADER -#define _sdma0_4_1_SH_MASK_HEADER - - -// addressBlock: sdma0_sdma0dec -//SDMA0_UCODE_ADDR -#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL -//SDMA0_UCODE_DATA -#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_VM_CNTL -#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 -#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL -//SDMA0_VM_CTX_LO -#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 -#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_VM_CTX_HI -#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 -#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_ACTIVE_FCN_ID -#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//SDMA0_VM_CTX_CNTL -#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 -#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 -#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L -//SDMA0_VIRT_RESET_REQ -#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L -//SDMA0_CONTEXT_REG_TYPE0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L -//SDMA0_CONTEXT_REG_TYPE1 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L -//SDMA0_CONTEXT_REG_TYPE2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L -//SDMA0_CONTEXT_REG_TYPE3 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_PUB_REG_TYPE0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE3 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL -//SDMA0_MMHUB_CNTL -#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 -#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL -//SDMA0_CONTEXT_GROUP_BOUNDARY -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_POWER_CNTL -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc -#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L -#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L -//SDMA0_CLK_CTRL -#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//SDMA0_CNTL -#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 -#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 -#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 -#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c -#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e -#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L -//SDMA0_CHICKEN_BITS -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L -//SDMA0_GB_ADDR_CONFIG -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_GB_ADDR_CONFIG_READ -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_RB_RPTR_FETCH_HI -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL -//SDMA0_RB_RPTR_FETCH -#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL -//SDMA0_IB_OFFSET_FETCH -#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL -//SDMA0_PROGRAM -#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 -#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL -//SDMA0_STATUS_REG -#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 -#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 -#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 -#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 -#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 -#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 -#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 -#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 -#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 -#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 -#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb -#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc -#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd -#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe -#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 -#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 -#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 -#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 -#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a -#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b -#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c -#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e -#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f -#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L -//SDMA0_STATUS1_REG -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 -#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 -#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 -#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 -#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 -#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa -#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd -#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe -#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf -#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 -#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L -//SDMA0_RD_BURST_CNTL -#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 -#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L -//SDMA0_HBM_PAGE_CONFIG -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L -//SDMA0_UCODE_CHECKSUM -#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 -#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL -//SDMA0_F32_CNTL -#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 -#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 -#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L -//SDMA0_FREEZE -#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 -#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 -#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 -#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 -#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L -//SDMA0_PHASE0_QUANTUM -#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L -//SDMA0_PHASE1_QUANTUM -#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L -//SDMA_POWER_GATING -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 -#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L -#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L -//SDMA_PGFSM_CONFIG -#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 -#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 -#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 -#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa -#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb -#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc -#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b -#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c -#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL -#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L -#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L -#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L -#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L -#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L -#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L -#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L -//SDMA_PGFSM_WRITE -#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL -//SDMA_PGFSM_READ -#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL -//SDMA0_EDC_CONFIG -#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 -#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L -//SDMA0_BA_THRESHOLD -#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 -#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 -#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL -#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L -//SDMA0_ID -#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 -#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL -//SDMA0_VERSION -#define SDMA0_VERSION__MINVER__SHIFT 0x0 -#define SDMA0_VERSION__MAJVER__SHIFT 0x8 -#define SDMA0_VERSION__REV__SHIFT 0x10 -#define SDMA0_VERSION__MINVER_MASK 0x0000007FL -#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L -#define SDMA0_VERSION__REV_MASK 0x003F0000L -//SDMA0_EDC_COUNTER -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L -//SDMA0_EDC_COUNTER_CLEAR -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L -//SDMA0_STATUS2_REG -#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 -#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 -#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 -#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL -#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L -//SDMA0_ATOMIC_CNTL -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L -//SDMA0_ATOMIC_PREOP_LO -#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL -//SDMA0_ATOMIC_PREOP_HI -#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_CNTL -#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 -#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 -#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb -#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d -#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL -#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L -//SDMA0_UTCL1_WATERMK -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L -//SDMA0_UTCL1_RD_STATUS -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L -//SDMA0_UTCL1_WR_STATUS -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L -//SDMA0_UTCL1_INV0 -#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 -#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 -#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 -#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 -#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb -#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc -#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c -#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L -#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L -//SDMA0_UTCL1_INV1 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_INV2 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK1 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_WR_XNACK0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_WR_XNACK1 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_TIMEOUT -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L -//SDMA0_UTCL1_PAGE -#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 -#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 -#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 -#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL -#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L -//SDMA0_POWER_CNTL_IDLE -#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 -#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 -#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 -#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL -#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L -#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L -//SDMA0_RELAX_ORDERING_LUT -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 -#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 -#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 -#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd -#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L -//SDMA0_CHICKEN_BITS_2 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL -//SDMA0_STATUS3_REG -#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 -#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 -#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL -#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L -//SDMA0_PHYSICAL_ADDR_LO -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 -#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L -//SDMA0_PHYSICAL_ADDR_HI -#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL -//SDMA0_ERROR_LOG -#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 -#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 -#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL -#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L -//SDMA0_PUB_DUMMY_REG0 -#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG1 -#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG2 -#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG3 -#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL -//SDMA0_F32_COUNTER -#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 -#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL -//SDMA0_UNBREAKABLE -#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 -#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L -//SDMA0_PERFMON_CNTL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 -#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb -#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L -//SDMA0_PERFCOUNTER0_RESULT -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER1_RESULT -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L -//SDMA0_CRD_CNTL -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L -//SDMA0_MMHUB_TRUSTLVL -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L -//SDMA0_GPU_IOV_VIOLATION_LOG -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//SDMA0_ULV_CNTL -#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 -#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d -#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e -#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f -#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL -#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L -#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L -#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L -//SDMA0_EA_DBIT_ADDR_DATA -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_EA_DBIT_ADDR_INDEX -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L -//SDMA0_GFX_RB_CNTL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_GFX_RB_BASE -#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_BASE_HI -#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_GFX_RB_RPTR -#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_HI -#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR -#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_HI -#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_CNTL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_GFX_RB_RPTR_ADDR_HI -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_ADDR_LO -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_IB_CNTL -#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_GFX_IB_RPTR -#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_OFFSET -#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_BASE_LO -#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_GFX_IB_BASE_HI -#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SIZE -#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_GFX_SKIP_CNTL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_GFX_CONTEXT_STATUS -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_GFX_DOORBELL -#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_GFX_CONTEXT_CNTL -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -//SDMA0_GFX_STATUS -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_GFX_DOORBELL_LOG -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_GFX_WATERMARK -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_GFX_DOORBELL_OFFSET -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_GFX_CSA_ADDR_LO -#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_CSA_ADDR_HI -#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SUB_REMAIN -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_GFX_PREEMPT -#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_GFX_DUMMY_REG -#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_RB_AQL_CNTL -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_GFX_MINOR_PTR_UPDATE -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_GFX_MIDCMD_DATA0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA1 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA2 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA3 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA4 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA5 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA6 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA7 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA8 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_CNTL -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC0_RB_CNTL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC0_RB_BASE -#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_BASE_HI -#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC0_RB_RPTR -#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_HI -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR -#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_HI -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_CNTL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC0_RB_RPTR_ADDR_HI -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_ADDR_LO -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_IB_CNTL -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC0_IB_RPTR -#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_OFFSET -#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_BASE_LO -#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC0_IB_BASE_HI -#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SIZE -#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC0_SKIP_CNTL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC0_CONTEXT_STATUS -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC0_DOORBELL -#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC0_STATUS -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC0_DOORBELL_LOG -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC0_WATERMARK -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC0_DOORBELL_OFFSET -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC0_CSA_ADDR_LO -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_CSA_ADDR_HI -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SUB_REMAIN -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC0_PREEMPT -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC0_DUMMY_REG -#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_RB_AQL_CNTL -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC0_MINOR_PTR_UPDATE -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC0_MIDCMD_DATA0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA1 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA2 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA3 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA4 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA5 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA6 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA7 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA8 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_CNTL -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC1_RB_CNTL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC1_RB_BASE -#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_BASE_HI -#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC1_RB_RPTR -#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_HI -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR -#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_HI -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_CNTL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC1_RB_RPTR_ADDR_HI -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_ADDR_LO -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_IB_CNTL -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC1_IB_RPTR -#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_OFFSET -#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_BASE_LO -#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC1_IB_BASE_HI -#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SIZE -#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC1_SKIP_CNTL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC1_CONTEXT_STATUS -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC1_DOORBELL -#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC1_STATUS -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC1_DOORBELL_LOG -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC1_WATERMARK -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC1_DOORBELL_OFFSET -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC1_CSA_ADDR_LO -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_CSA_ADDR_HI -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SUB_REMAIN -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC1_PREEMPT -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC1_DUMMY_REG -#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_RB_AQL_CNTL -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC1_MINOR_PTR_UPDATE -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC1_MIDCMD_DATA0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA1 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA2 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA3 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA4 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA5 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA6 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA7 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA8 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_CNTL -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h deleted file mode 100644 index 5793a10e3dc2..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_default.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _vcn_1_0_DEFAULT_HEADER -#define _vcn_1_0_DEFAULT_HEADER - - -// addressBlock: uvd_uvd_pg_dec -#define mmUVD_PGFSM_CONFIG_DEFAULT 0x00000000 -#define mmUVD_PGFSM_STATUS_DEFAULT 0x002aaaaa -#define mmUVD_POWER_STATUS_DEFAULT 0x00000801 -#define mmCC_UVD_HARVESTING_DEFAULT 0x00000000 -#define mmUVD_SCRATCH1_DEFAULT 0x00000000 -#define mmUVD_SCRATCH2_DEFAULT 0x00000000 -#define mmUVD_SCRATCH3_DEFAULT 0x00000000 -#define mmUVD_SCRATCH4_DEFAULT 0x00000000 -#define mmUVD_SCRATCH5_DEFAULT 0x00000000 -#define mmUVD_SCRATCH6_DEFAULT 0x00000000 -#define mmUVD_SCRATCH7_DEFAULT 0x00000000 -#define mmUVD_SCRATCH8_DEFAULT 0x00000000 -#define mmUVD_SCRATCH9_DEFAULT 0x00000000 -#define mmUVD_SCRATCH10_DEFAULT 0x00000000 -#define mmUVD_SCRATCH11_DEFAULT 0x00000000 -#define mmUVD_SCRATCH12_DEFAULT 0x00000000 -#define mmUVD_SCRATCH13_DEFAULT 0x00000000 -#define mmUVD_SCRATCH14_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 - - -// addressBlock: uvd_uvdgendec -#define mmUVD_LCM_CGC_CNTRL_DEFAULT 0xa0f00000 - - -// addressBlock: uvd_uvdnpdec -#define mmUVD_JPEG_CNTL_DEFAULT 0x00000004 -#define mmUVD_JPEG_RB_BASE_DEFAULT 0x00000000 -#define mmUVD_JPEG_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_RB_SIZE_DEFAULT 0x00000000 -#define mmUVD_JPEG_UV_TILING_CTRL_DEFAULT 0x02104800 -#define mmUVD_JPEG_TILING_CTRL_DEFAULT 0x02104800 -#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_JPEG_GPCOM_CMD_DEFAULT 0x00000000 -#define mmUVD_JPEG_GPCOM_DATA0_DEFAULT 0x00000000 -#define mmUVD_JPEG_GPCOM_DATA1_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_BASE_LO_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_BASE_HI_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_SIZE_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_RPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_JRB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JPEG_UV_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_SEMA_ADDR_LOW_DEFAULT 0x00000000 -#define mmUVD_SEMA_ADDR_HIGH_DEFAULT 0x00000000 -#define mmUVD_SEMA_CMD_DEFAULT 0x00000080 -#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000 -#define mmUVD_UDEC_DBW_UV_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000 -#define mmUVD_SUVD_CGC_STATUS_DEFAULT 0x00000000 -#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_NO_OP_DEFAULT 0x00000000 -#define mmUVD_JPEG_CNTL2_DEFAULT 0x00000000 -#define mmUVD_VERSION_DEFAULT 0x00010000 -#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH9_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH10_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH11_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH12_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH13_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH14_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH15_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH16_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH17_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH18_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH19_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH20_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH21_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH22_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH23_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE2_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR4_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 - - -// addressBlock: uvd_uvddec -#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003 -#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_JRBC_IB_VMID_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_CNTL_DEFAULT 0x00000100 -#define mmUVD_JRBC_IB_SIZE_DEFAULT 0x00000000 -#define mmUVD_JRBC_LMI_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_JRBC_SOFT_RESET_DEFAULT 0x00000000 -#define mmUVD_JRBC_STATUS_DEFAULT 0x00000003 -#define mmUVD_RB_RPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE3_DEFAULT 0x00000000 -#define mmJPEG_CGC_GATE_DEFAULT 0x00300000 -#define mmUVD_CTX_INDEX_DEFAULT 0x00000000 -#define mmUVD_CTX_DATA_DEFAULT 0x00000000 -#define mmUVD_CGC_GATE_DEFAULT 0x000fffff -#define mmUVD_CGC_STATUS_DEFAULT 0x00000000 -#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d -#define mmUVD_GP_SCRATCH0_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH1_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH2_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH3_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH5_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH6_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH7_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_VMID_DEFAULT 0x00000000 -#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000 -#define mmUVD_MASTINT_EN_DEFAULT 0x00000000 -#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d -#define mmUVD_LMI_CTRL_DEFAULT 0x00104340 -#define mmUVD_LMI_STATUS_DEFAULT 0x003fff7f -#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088 -#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000 -#define mmUVD_GPCOM_SYS_CMD_DEFAULT 0x00000000 -#define mmUVD_GPCOM_SYS_DATA0_DEFAULT 0x00000000 -#define mmUVD_GPCOM_SYS_DATA1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000 -#define mmUVD_SOFT_RESET_DEFAULT 0x00000008 -#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000 -#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101 -#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000 -#define mmUVD_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000 -#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000 -#define mmUVD_RBC_WPTR_POLL_CNTL_DEFAULT 0x00400100 -#define mmUVD_RBC_WPTR_POLL_ADDR_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO4_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI4_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE4_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR4_DEFAULT 0x00000000 - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h new file mode 100644 index 000000000000..4be3cb5c4556 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_0_DEFAULT_HEADER +#define _sdma0_4_0_DEFAULT_HEADER + + +// addressBlock: sdma0_sdma0dec +#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 +#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 +#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 +#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 +#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f +#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff +#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff +#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 +#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 +#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 +#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 +#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000 +#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 +#define mmSDMA0_CNTL_DEFAULT 0x00000002 +#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 +#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 +#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 +#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define mmSDMA0_PROGRAM_DEFAULT 0x00000000 +#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 +#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff +#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 +#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 +#define mmSDMA0_FREEZE_DEFAULT 0x00000000 +#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA_POWER_GATING_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 +#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 +#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 +#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define mmSDMA0_ID_DEFAULT 0x00000001 +#define mmSDMA0_VERSION_DEFAULT 0x00000400 +#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 +#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 +#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 +#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 +#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe +#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff +#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff +#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 +#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 +#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 +#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 +#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 +#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 +#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 +#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f +#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 +#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 +#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd +#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 +#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 +#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 +#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 +#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h new file mode 100644 index 000000000000..99758695f019 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h @@ -0,0 +1,547 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_0_OFFSET_HEADER +#define _sdma0_4_0_OFFSET_HEADER + + + +// addressBlock: sdma0_sdma0dec +// base address: 0x4980 +#define mmSDMA0_UCODE_ADDR 0x0000 +#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA0_UCODE_DATA 0x0001 +#define mmSDMA0_UCODE_DATA_BASE_IDX 0 +#define mmSDMA0_VM_CNTL 0x0004 +#define mmSDMA0_VM_CNTL_BASE_IDX 0 +#define mmSDMA0_VM_CTX_LO 0x0005 +#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA0_VM_CTX_HI 0x0006 +#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA0_ACTIVE_FCN_ID 0x0007 +#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA0_VM_CTX_CNTL 0x0008 +#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA0_VIRT_RESET_REQ 0x0009 +#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA0_VF_ENABLE 0x000a +#define mmSDMA0_VF_ENABLE_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE0 0x000f +#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE1 0x0010 +#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE2 0x0011 +#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE3 0x0012 +#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_MMHUB_CNTL 0x0013 +#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL 0x001a +#define mmSDMA0_POWER_CNTL_BASE_IDX 0 +#define mmSDMA0_CLK_CTRL 0x001b +#define mmSDMA0_CLK_CTRL_BASE_IDX 0 +#define mmSDMA0_CNTL 0x001c +#define mmSDMA0_CNTL_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS 0x001d +#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG 0x001e +#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH 0x0022 +#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA0_IB_OFFSET_FETCH 0x0023 +#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA0_PROGRAM 0x0024 +#define mmSDMA0_PROGRAM_BASE_IDX 0 +#define mmSDMA0_STATUS_REG 0x0025 +#define mmSDMA0_STATUS_REG_BASE_IDX 0 +#define mmSDMA0_STATUS1_REG 0x0026 +#define mmSDMA0_STATUS1_REG_BASE_IDX 0 +#define mmSDMA0_RD_BURST_CNTL 0x0027 +#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA0_UCODE_CHECKSUM 0x0029 +#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA0_F32_CNTL 0x002a +#define mmSDMA0_F32_CNTL_BASE_IDX 0 +#define mmSDMA0_FREEZE 0x002b +#define mmSDMA0_FREEZE_BASE_IDX 0 +#define mmSDMA0_PHASE0_QUANTUM 0x002c +#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA0_PHASE1_QUANTUM 0x002d +#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA_POWER_GATING 0x002e +#define mmSDMA_POWER_GATING_BASE_IDX 0 +#define mmSDMA_PGFSM_CONFIG 0x002f +#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 +#define mmSDMA_PGFSM_WRITE 0x0030 +#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 +#define mmSDMA_PGFSM_READ 0x0031 +#define mmSDMA_PGFSM_READ_BASE_IDX 0 +#define mmSDMA0_EDC_CONFIG 0x0032 +#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA0_BA_THRESHOLD 0x0033 +#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA0_ID 0x0034 +#define mmSDMA0_ID_BASE_IDX 0 +#define mmSDMA0_VERSION 0x0035 +#define mmSDMA0_VERSION_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER 0x0036 +#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA0_STATUS2_REG 0x0038 +#define mmSDMA0_STATUS2_REG_BASE_IDX 0 +#define mmSDMA0_ATOMIC_CNTL 0x0039 +#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_LO 0x003a +#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_HI 0x003b +#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA0_UTCL1_CNTL 0x003c +#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA0_UTCL1_WATERMK 0x003d +#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_STATUS 0x003e +#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_STATUS 0x003f +#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV0 0x0040 +#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV1 0x0041 +#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV2 0x0042 +#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_TIMEOUT 0x0047 +#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA0_UTCL1_PAGE 0x0048 +#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL_IDLE 0x0049 +#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA0_RELAX_ORDERING_LUT 0x004a +#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS_2 0x004b +#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA0_STATUS3_REG 0x004c +#define mmSDMA0_STATUS3_REG_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PHASE2_QUANTUM 0x004f +#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA0_ERROR_LOG 0x0050 +#define mmSDMA0_ERROR_LOG_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG0 0x0051 +#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG1 0x0052 +#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG2 0x0053 +#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG3 0x0054 +#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA0_F32_COUNTER 0x0055 +#define mmSDMA0_F32_COUNTER_BASE_IDX 0 +#define mmSDMA0_UNBREAKABLE 0x0056 +#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA0_PERFMON_CNTL 0x0057 +#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA0_CRD_CNTL 0x005b +#define mmSDMA0_CRD_CNTL_BASE_IDX 0 +#define mmSDMA0_MMHUB_TRUSTLVL 0x005c +#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA0_ULV_CNTL 0x005e +#define mmSDMA0_ULV_CNTL_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA0_GFX_RB_CNTL 0x0080 +#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE 0x0081 +#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE_HI 0x0082 +#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR 0x0083 +#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR 0x0085 +#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_CNTL 0x008a +#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_IB_RPTR 0x008b +#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_IB_OFFSET 0x008c +#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_LO 0x008d +#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_HI 0x008e +#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SIZE 0x008f +#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_GFX_SKIP_CNTL 0x0090 +#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL 0x0092 +#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_STATUS 0x00a8 +#define mmSDMA0_GFX_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_GFX_WATERMARK 0x00aa +#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_GFX_PREEMPT 0x00b0 +#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA0_GFX_DUMMY_REG 0x00b1 +#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_CNTL 0x00e0 +#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE 0x00e1 +#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 +#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR 0x00e3 +#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 +#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR 0x00e5 +#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 +#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_CNTL 0x00ea +#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_RPTR 0x00eb +#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_OFFSET 0x00ec +#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed +#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee +#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SIZE 0x00ef +#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 +#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 +#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL 0x00f2 +#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA0_PAGE_STATUS 0x0108 +#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 +#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_PAGE_WATERMARK 0x010a +#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b +#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c +#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d +#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f +#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_PAGE_PREEMPT 0x0110 +#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA0_PAGE_DUMMY_REG 0x0111 +#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 +#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 +#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 +#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 +#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 +#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 +#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 +#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 +#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 +#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 +#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 +#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_CNTL 0x0140 +#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE 0x0141 +#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE_HI 0x0142 +#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR 0x0143 +#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 +#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR 0x0145 +#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 +#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_CNTL 0x014a +#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_RPTR 0x014b +#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_OFFSET 0x014c +#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_LO 0x014d +#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_HI 0x014e +#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SIZE 0x014f +#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC0_SKIP_CNTL 0x0150 +#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 +#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL 0x0152 +#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC0_STATUS 0x0168 +#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 +#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC0_WATERMARK 0x016a +#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b +#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c +#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d +#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f +#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC0_PREEMPT 0x0170 +#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC0_DUMMY_REG 0x0171 +#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 +#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 +#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 +#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 +#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 +#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 +#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 +#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 +#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 +#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 +#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 +#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_CNTL 0x01a0 +#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE 0x01a1 +#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 +#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR 0x01a3 +#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 +#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR 0x01a5 +#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 +#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_CNTL 0x01aa +#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_RPTR 0x01ab +#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_OFFSET 0x01ac +#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad +#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae +#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SIZE 0x01af +#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 +#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 +#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL 0x01b2 +#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC1_STATUS 0x01c8 +#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 +#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC1_WATERMARK 0x01ca +#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb +#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc +#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd +#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf +#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC1_PREEMPT 0x01d0 +#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC1_DUMMY_REG 0x01d1 +#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 +#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 +#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 +#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 +#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 +#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 +#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 +#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 +#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 +#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 +#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 +#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h new file mode 100644 index 000000000000..f846cc8268d8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h @@ -0,0 +1,1852 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_0_SH_MASK_HEADER +#define _sdma0_4_0_SH_MASK_HEADER + + +// addressBlock: sdma0_sdma0dec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_VM_CNTL +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_VM_CTX_LO +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_VM_CTX_HI +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_ACTIVE_FCN_ID +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA0_VM_CTX_CNTL +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA0_VIRT_RESET_REQ +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_VF_ENABLE +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA0_CONTEXT_REG_TYPE0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA0_CONTEXT_REG_TYPE1 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA0_CONTEXT_REG_TYPE2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA0_CONTEXT_REG_TYPE3 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_PUB_REG_TYPE0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL +//SDMA0_MMHUB_CNTL +#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA0_CONTEXT_GROUP_BOUNDARY +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA0_CLK_CTRL +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA0_RD_BURST_CNTL +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PHASE0_QUANTUM +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_PHASE1_QUANTUM +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA_POWER_GATING +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L +//SDMA_PGFSM_CONFIG +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L +//SDMA_PGFSM_WRITE +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL +//SDMA_PGFSM_READ +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL +//SDMA0_EDC_CONFIG +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA0_EDC_COUNTER_CLEAR +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA0_POWER_CNTL_IDLE +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_PHASE2_QUANTUM +#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_UNBREAKABLE +#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA0_PERFMON_CNTL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA0_PERFCOUNTER0_RESULT +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_RESULT +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA0_MMHUB_TRUSTLVL +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L +#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L +//SDMA0_GPU_IOV_VIOLATION_LOG +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//SDMA0_ULV_CNTL +#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_GFX_RB_CNTL +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_GFX_RB_BASE +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_BASE_HI +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_GFX_RB_RPTR +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_HI +#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_HI +#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_CNTL +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_GFX_RB_RPTR_ADDR_HI +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_ADDR_LO +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_IB_CNTL +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_GFX_IB_RPTR +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_OFFSET +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_BASE_LO +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_GFX_IB_BASE_HI +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SIZE +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_SKIP_CNTL +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_GFX_CONTEXT_STATUS +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_GFX_DOORBELL +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_GFX_CONTEXT_CNTL +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA0_GFX_STATUS +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_GFX_DOORBELL_LOG +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_GFX_WATERMARK +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_GFX_DOORBELL_OFFSET +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_GFX_CSA_ADDR_LO +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_CSA_ADDR_HI +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SUB_REMAIN +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_GFX_PREEMPT +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_GFX_DUMMY_REG +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_RB_AQL_CNTL +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_GFX_MINOR_PTR_UPDATE +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_GFX_MIDCMD_DATA0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA1 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA2 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA3 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA4 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA5 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA6 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA7 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA8 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_CNTL +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_PAGE_RB_CNTL +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_PAGE_RB_BASE +#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_BASE_HI +#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_PAGE_RB_RPTR +#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_HI +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR +#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_HI +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_CNTL +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_PAGE_RB_RPTR_ADDR_HI +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_ADDR_LO +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_IB_CNTL +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_PAGE_IB_RPTR +#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_OFFSET +#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_BASE_LO +#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_PAGE_IB_BASE_HI +#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SIZE +#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_SKIP_CNTL +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_PAGE_CONTEXT_STATUS +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_PAGE_DOORBELL +#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_PAGE_STATUS +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_PAGE_DOORBELL_LOG +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_PAGE_WATERMARK +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_PAGE_DOORBELL_OFFSET +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_PAGE_CSA_ADDR_LO +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_CSA_ADDR_HI +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SUB_REMAIN +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_PAGE_PREEMPT +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_PAGE_DUMMY_REG +#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_RB_AQL_CNTL +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_PAGE_MINOR_PTR_UPDATE +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_PAGE_MIDCMD_DATA0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA1 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA2 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA3 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA4 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA5 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA6 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA7 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA8 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_CNTL +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC0_RB_CNTL +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC0_RB_BASE +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_BASE_HI +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC0_RB_RPTR +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_HI +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_HI +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_CNTL +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC0_RB_RPTR_ADDR_HI +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_ADDR_LO +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_IB_CNTL +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC0_IB_RPTR +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_OFFSET +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_BASE_LO +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC0_IB_BASE_HI +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SIZE +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_SKIP_CNTL +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_RLC0_CONTEXT_STATUS +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC0_DOORBELL +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC0_STATUS +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC0_DOORBELL_LOG +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC0_WATERMARK +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC0_DOORBELL_OFFSET +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC0_CSA_ADDR_LO +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_CSA_ADDR_HI +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SUB_REMAIN +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_RLC0_PREEMPT +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC0_DUMMY_REG +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_RB_AQL_CNTL +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC0_MINOR_PTR_UPDATE +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC0_MIDCMD_DATA0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA1 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA2 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA3 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA4 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA5 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA6 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA7 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA8 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_CNTL +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC1_RB_CNTL +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC1_RB_BASE +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_BASE_HI +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC1_RB_RPTR +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_HI +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_HI +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_CNTL +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC1_RB_RPTR_ADDR_HI +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_ADDR_LO +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_IB_CNTL +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC1_IB_RPTR +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_OFFSET +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_BASE_LO +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC1_IB_BASE_HI +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SIZE +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_SKIP_CNTL +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA0_RLC1_CONTEXT_STATUS +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC1_DOORBELL +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC1_STATUS +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC1_DOORBELL_LOG +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC1_WATERMARK +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC1_DOORBELL_OFFSET +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC1_CSA_ADDR_LO +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_CSA_ADDR_HI +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SUB_REMAIN +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_RLC1_PREEMPT +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC1_DUMMY_REG +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_RB_AQL_CNTL +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC1_MINOR_PTR_UPDATE +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC1_MIDCMD_DATA0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA1 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA2 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA3 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA4 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA5 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA6 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA7 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA8 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_CNTL +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h index bafcecbad451..bafcecbad451 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h index 1544af6a1efc..1544af6a1efc 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/SDMA0/sdma0_4_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h new file mode 100644 index 000000000000..934733762ddf --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_0_DEFAULT_HEADER +#define _sdma1_4_0_DEFAULT_HEADER + + +// addressBlock: sdma1_sdma1dec +#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 +#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 +#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 +#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 +#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 +#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f +#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff +#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff +#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 +#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 +#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 +#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 +#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 +#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 +#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 +#define mmSDMA1_CNTL_DEFAULT 0x00000002 +#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 +#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 +#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 +#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 +#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 +#define mmSDMA1_PROGRAM_DEFAULT 0x00000000 +#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 +#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff +#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 +#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 +#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 +#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 +#define mmSDMA1_FREEZE_DEFAULT 0x00000000 +#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 +#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff +#define mmSDMA1_ID_DEFAULT 0x00000001 +#define mmSDMA1_VERSION_DEFAULT 0x00000400 +#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 +#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 +#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 +#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 +#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 +#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 +#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe +#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff +#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff +#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 +#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 +#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 +#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 +#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 +#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 +#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 +#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 +#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 +#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f +#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 +#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 +#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 +#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 +#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 +#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 +#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd +#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 +#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 +#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 +#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 +#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 +#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 +#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 +#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 +#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 +#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h new file mode 100644 index 000000000000..f2c151a7935d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h @@ -0,0 +1,539 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_0_OFFSET_HEADER +#define _sdma1_4_0_OFFSET_HEADER + + + +// addressBlock: sdma1_sdma1dec +// base address: 0x5180 +#define mmSDMA1_UCODE_ADDR 0x0000 +#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA1_UCODE_DATA 0x0001 +#define mmSDMA1_UCODE_DATA_BASE_IDX 0 +#define mmSDMA1_VM_CNTL 0x0004 +#define mmSDMA1_VM_CNTL_BASE_IDX 0 +#define mmSDMA1_VM_CTX_LO 0x0005 +#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA1_VM_CTX_HI 0x0006 +#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA1_ACTIVE_FCN_ID 0x0007 +#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA1_VM_CTX_CNTL 0x0008 +#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA1_VIRT_RESET_REQ 0x0009 +#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA1_VF_ENABLE 0x000a +#define mmSDMA1_VF_ENABLE_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE0 0x000f +#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE1 0x0010 +#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE2 0x0011 +#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE3 0x0012 +#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_MMHUB_CNTL 0x0013 +#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL 0x001a +#define mmSDMA1_POWER_CNTL_BASE_IDX 0 +#define mmSDMA1_CLK_CTRL 0x001b +#define mmSDMA1_CLK_CTRL_BASE_IDX 0 +#define mmSDMA1_CNTL 0x001c +#define mmSDMA1_CNTL_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS 0x001d +#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG 0x001e +#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH 0x0022 +#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA1_IB_OFFSET_FETCH 0x0023 +#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA1_PROGRAM 0x0024 +#define mmSDMA1_PROGRAM_BASE_IDX 0 +#define mmSDMA1_STATUS_REG 0x0025 +#define mmSDMA1_STATUS_REG_BASE_IDX 0 +#define mmSDMA1_STATUS1_REG 0x0026 +#define mmSDMA1_STATUS1_REG_BASE_IDX 0 +#define mmSDMA1_RD_BURST_CNTL 0x0027 +#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA1_UCODE_CHECKSUM 0x0029 +#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA1_F32_CNTL 0x002a +#define mmSDMA1_F32_CNTL_BASE_IDX 0 +#define mmSDMA1_FREEZE 0x002b +#define mmSDMA1_FREEZE_BASE_IDX 0 +#define mmSDMA1_PHASE0_QUANTUM 0x002c +#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA1_PHASE1_QUANTUM 0x002d +#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA1_EDC_CONFIG 0x0032 +#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA1_BA_THRESHOLD 0x0033 +#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA1_ID 0x0034 +#define mmSDMA1_ID_BASE_IDX 0 +#define mmSDMA1_VERSION 0x0035 +#define mmSDMA1_VERSION_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER 0x0036 +#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA1_STATUS2_REG 0x0038 +#define mmSDMA1_STATUS2_REG_BASE_IDX 0 +#define mmSDMA1_ATOMIC_CNTL 0x0039 +#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_LO 0x003a +#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_HI 0x003b +#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA1_UTCL1_CNTL 0x003c +#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA1_UTCL1_WATERMK 0x003d +#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_STATUS 0x003e +#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_STATUS 0x003f +#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV0 0x0040 +#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV1 0x0041 +#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV2 0x0042 +#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_TIMEOUT 0x0047 +#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA1_UTCL1_PAGE 0x0048 +#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL_IDLE 0x0049 +#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA1_RELAX_ORDERING_LUT 0x004a +#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS_2 0x004b +#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA1_STATUS3_REG 0x004c +#define mmSDMA1_STATUS3_REG_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PHASE2_QUANTUM 0x004f +#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA1_ERROR_LOG 0x0050 +#define mmSDMA1_ERROR_LOG_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG0 0x0051 +#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG1 0x0052 +#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG2 0x0053 +#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG3 0x0054 +#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA1_F32_COUNTER 0x0055 +#define mmSDMA1_F32_COUNTER_BASE_IDX 0 +#define mmSDMA1_UNBREAKABLE 0x0056 +#define mmSDMA1_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA1_PERFMON_CNTL 0x0057 +#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA1_CRD_CNTL 0x005b +#define mmSDMA1_CRD_CNTL_BASE_IDX 0 +#define mmSDMA1_MMHUB_TRUSTLVL 0x005c +#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA1_ULV_CNTL 0x005e +#define mmSDMA1_ULV_CNTL_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA1_GFX_RB_CNTL 0x0080 +#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE 0x0081 +#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE_HI 0x0082 +#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR 0x0083 +#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR 0x0085 +#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_CNTL 0x008a +#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_IB_RPTR 0x008b +#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_IB_OFFSET 0x008c +#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_LO 0x008d +#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_HI 0x008e +#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SIZE 0x008f +#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_GFX_SKIP_CNTL 0x0090 +#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL 0x0092 +#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_STATUS 0x00a8 +#define mmSDMA1_GFX_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_GFX_WATERMARK 0x00aa +#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_GFX_PREEMPT 0x00b0 +#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA1_GFX_DUMMY_REG 0x00b1 +#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_CNTL 0x00e0 +#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE 0x00e1 +#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 +#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR 0x00e3 +#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 +#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR 0x00e5 +#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 +#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_CNTL 0x00ea +#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_RPTR 0x00eb +#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_OFFSET 0x00ec +#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed +#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee +#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SIZE 0x00ef +#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 +#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 +#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL 0x00f2 +#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA1_PAGE_STATUS 0x0108 +#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 +#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_PAGE_WATERMARK 0x010a +#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b +#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c +#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d +#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f +#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_PAGE_PREEMPT 0x0110 +#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA1_PAGE_DUMMY_REG 0x0111 +#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 +#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 +#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 +#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 +#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 +#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 +#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 +#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 +#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 +#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 +#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 +#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_CNTL 0x0140 +#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE 0x0141 +#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE_HI 0x0142 +#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR 0x0143 +#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 +#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR 0x0145 +#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 +#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_CNTL 0x014a +#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_RPTR 0x014b +#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_OFFSET 0x014c +#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_LO 0x014d +#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_HI 0x014e +#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SIZE 0x014f +#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC0_SKIP_CNTL 0x0150 +#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 +#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL 0x0152 +#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC0_STATUS 0x0168 +#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 +#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC0_WATERMARK 0x016a +#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b +#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c +#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d +#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f +#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC0_PREEMPT 0x0170 +#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC0_DUMMY_REG 0x0171 +#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 +#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 +#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 +#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 +#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 +#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 +#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 +#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 +#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 +#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 +#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 +#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_CNTL 0x01a0 +#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE 0x01a1 +#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 +#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR 0x01a3 +#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 +#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR 0x01a5 +#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 +#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_CNTL 0x01aa +#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_RPTR 0x01ab +#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_OFFSET 0x01ac +#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad +#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae +#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SIZE 0x01af +#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 +#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 +#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL 0x01b2 +#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC1_STATUS 0x01c8 +#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 +#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC1_WATERMARK 0x01ca +#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb +#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc +#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd +#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf +#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC1_PREEMPT 0x01d0 +#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC1_DUMMY_REG 0x01d1 +#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 +#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 +#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 +#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 +#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 +#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 +#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 +#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 +#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 +#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 +#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 +#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h new file mode 100644 index 000000000000..99849e0dde5e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h @@ -0,0 +1,1810 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_0_SH_MASK_HEADER +#define _sdma1_4_0_SH_MASK_HEADER + + +// addressBlock: sdma1_sdma1dec +//SDMA1_UCODE_ADDR +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA1_UCODE_DATA +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_VM_CNTL +#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA1_VM_CTX_LO +#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_VM_CTX_HI +#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_ACTIVE_FCN_ID +#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA1_VM_CTX_CNTL +#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA1_VIRT_RESET_REQ +#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA1_VF_ENABLE +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA1_CONTEXT_REG_TYPE0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA1_CONTEXT_REG_TYPE1 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA1_CONTEXT_REG_TYPE2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA1_CONTEXT_REG_TYPE3 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_PUB_REG_TYPE0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE3 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL +//SDMA1_MMHUB_CNTL +#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA1_CONTEXT_GROUP_BOUNDARY +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_POWER_CNTL +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA1_CLK_CTRL +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA1_CNTL +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA1_CHICKEN_BITS +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA1_GB_ADDR_CONFIG +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_GB_ADDR_CONFIG_READ +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_RB_RPTR_FETCH_HI +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA1_RB_RPTR_FETCH +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_IB_OFFSET_FETCH +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_PROGRAM +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_STATUS_REG +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_STATUS1_REG +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA1_RD_BURST_CNTL +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +//SDMA1_HBM_PAGE_CONFIG +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA1_UCODE_CHECKSUM +#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_F32_CNTL +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L +//SDMA1_FREEZE +#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA1_PHASE0_QUANTUM +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_PHASE1_QUANTUM +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_EDC_CONFIG +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA1_BA_THRESHOLD +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA1_ID +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_VERSION +#define SDMA1_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_VERSION__REV__SHIFT 0x10 +#define SDMA1_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_VERSION__REV_MASK 0x003F0000L +//SDMA1_EDC_COUNTER +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L +//SDMA1_EDC_COUNTER_CLEAR +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA1_STATUS2_REG +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_ATOMIC_CNTL +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_ATOMIC_PREOP_LO +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_ATOMIC_PREOP_HI +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_CNTL +#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA1_UTCL1_WATERMK +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L +//SDMA1_UTCL1_RD_STATUS +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA1_UTCL1_WR_STATUS +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA1_UTCL1_INV0 +#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA1_UTCL1_INV1 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_INV2 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK1 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_WR_XNACK0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_WR_XNACK1 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_TIMEOUT +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA1_UTCL1_PAGE +#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA1_POWER_CNTL_IDLE +#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA1_RELAX_ORDERING_LUT +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA1_CHICKEN_BITS_2 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA1_STATUS3_REG +#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +//SDMA1_PHYSICAL_ADDR_LO +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA1_PHYSICAL_ADDR_HI +#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA1_PHASE2_QUANTUM +#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_ERROR_LOG +#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_PUB_DUMMY_REG0 +#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG1 +#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG2 +#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG3 +#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_COUNTER +#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_UNBREAKABLE +#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA1_PERFMON_CNTL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA1_PERFCOUNTER0_RESULT +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER1_RESULT +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA1_CRD_CNTL +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA1_MMHUB_TRUSTLVL +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L +#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L +//SDMA1_GPU_IOV_VIOLATION_LOG +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 +#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L +//SDMA1_ULV_CNTL +#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA1_EA_DBIT_ADDR_DATA +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_EA_DBIT_ADDR_INDEX +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA1_GFX_RB_CNTL +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_GFX_RB_BASE +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_BASE_HI +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_GFX_RB_RPTR +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_HI +#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_HI +#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_CNTL +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_GFX_RB_RPTR_ADDR_HI +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_ADDR_LO +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_IB_CNTL +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_GFX_IB_RPTR +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_OFFSET +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_BASE_LO +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_GFX_IB_BASE_HI +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SIZE +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_SKIP_CNTL +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_GFX_CONTEXT_STATUS +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_GFX_DOORBELL +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_GFX_CONTEXT_CNTL +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA1_GFX_STATUS +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_GFX_DOORBELL_LOG +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_GFX_WATERMARK +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_GFX_DOORBELL_OFFSET +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_GFX_CSA_ADDR_LO +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_CSA_ADDR_HI +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SUB_REMAIN +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_GFX_PREEMPT +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_GFX_DUMMY_REG +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_RB_AQL_CNTL +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_GFX_MINOR_PTR_UPDATE +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_GFX_MIDCMD_DATA0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA1 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA2 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA3 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA4 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA5 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA6 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA7 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA8 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_CNTL +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_PAGE_RB_CNTL +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_PAGE_RB_BASE +#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_BASE_HI +#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_PAGE_RB_RPTR +#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_HI +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR +#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_HI +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_CNTL +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_PAGE_RB_RPTR_ADDR_HI +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_ADDR_LO +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_IB_CNTL +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_PAGE_IB_RPTR +#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_OFFSET +#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_BASE_LO +#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_PAGE_IB_BASE_HI +#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SIZE +#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_SKIP_CNTL +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_PAGE_CONTEXT_STATUS +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_PAGE_DOORBELL +#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_PAGE_STATUS +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_PAGE_DOORBELL_LOG +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_PAGE_WATERMARK +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_PAGE_DOORBELL_OFFSET +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_PAGE_CSA_ADDR_LO +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_CSA_ADDR_HI +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SUB_REMAIN +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_PAGE_PREEMPT +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_PAGE_DUMMY_REG +#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_RB_AQL_CNTL +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_PAGE_MINOR_PTR_UPDATE +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_PAGE_MIDCMD_DATA0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA1 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA2 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA3 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA4 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA5 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA6 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA7 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA8 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_CNTL +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC0_RB_CNTL +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC0_RB_BASE +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_BASE_HI +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC0_RB_RPTR +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_HI +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_HI +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_CNTL +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC0_RB_RPTR_ADDR_HI +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_ADDR_LO +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_IB_CNTL +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC0_IB_RPTR +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_OFFSET +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_BASE_LO +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC0_IB_BASE_HI +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SIZE +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_SKIP_CNTL +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_RLC0_CONTEXT_STATUS +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC0_DOORBELL +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC0_STATUS +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC0_DOORBELL_LOG +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC0_WATERMARK +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC0_DOORBELL_OFFSET +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC0_CSA_ADDR_LO +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_CSA_ADDR_HI +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SUB_REMAIN +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_RLC0_PREEMPT +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC0_DUMMY_REG +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_RB_AQL_CNTL +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC0_MINOR_PTR_UPDATE +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC0_MIDCMD_DATA0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA1 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA2 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA3 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA4 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA5 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA6 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA7 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA8 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_CNTL +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC1_RB_CNTL +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC1_RB_BASE +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_BASE_HI +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC1_RB_RPTR +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_HI +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_HI +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_CNTL +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC1_RB_RPTR_ADDR_HI +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_ADDR_LO +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_IB_CNTL +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC1_IB_RPTR +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_OFFSET +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_BASE_LO +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC1_IB_BASE_HI +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SIZE +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_SKIP_CNTL +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL +//SDMA1_RLC1_CONTEXT_STATUS +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC1_DOORBELL +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC1_STATUS +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC1_DOORBELL_LOG +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC1_WATERMARK +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC1_DOORBELL_OFFSET +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC1_CSA_ADDR_LO +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_CSA_ADDR_HI +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SUB_REMAIN +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_RLC1_PREEMPT +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC1_DUMMY_REG +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_RB_AQL_CNTL +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC1_MINOR_PTR_UPDATE +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC1_MIDCMD_DATA0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA1 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA2 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA3 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA4 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA5 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA6 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA7 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA8 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_CNTL +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h index c1006fe58daa..c1006fe58daa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h index a0be5c9bfc10..a0be5c9bfc10 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h index 1a3c4864ae66..1a3c4864ae66 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h index 6af3e6fa2f23..6af3e6fa2f23 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h index b8cadcf78da6..b8cadcf78da6 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h index 0cbae8bafbf2..0cbae8bafbf2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h index 3053fd34d216..3053fd34d216 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h index f0306c5e3da3..f0306c5e3da3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_9_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h new file mode 100644 index 000000000000..128a18f1e362 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _umc_6_0_DEFAULT_HEADER +#define _umc_6_0_DEFAULT_HEADER + +#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000 + +#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203 + +#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h new file mode 100644 index 000000000000..6985dbba39f5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _umc_6_0_OFFSET_H_ +#define _umc_6_0_OFFSET_H_ + +#define mmUMCCH0_0_EccCtrl 0x0053 +#define mmUMCCH0_0_EccCtrl_BASE_IDX 0 +#define mmUMCCH1_0_EccCtrl 0x0853 +#define mmUMCCH1_0_EccCtrl_BASE_IDX 0 +#define mmUMCCH2_0_EccCtrl 0x1053 +#define mmUMCCH2_0_EccCtrl_BASE_IDX 0 +#define mmUMCCH3_0_EccCtrl 0x1853 +#define mmUMCCH3_0_EccCtrl_BASE_IDX 0 + +#define mmUMCCH0_0_UMC_CONFIG 0x0040 +#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0 +#define mmUMCCH1_0_UMC_CONFIG 0x0840 +#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0 +#define mmUMCCH2_0_UMC_CONFIG 0x1040 +#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0 +#define mmUMCCH3_0_UMC_CONFIG 0x1840 +#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0 + +#define mmUMCCH0_0_UmcLocalCap 0x0306 +#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0 +#define mmUMCCH1_0_UmcLocalCap 0x0b06 +#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0 +#define mmUMCCH2_0_UmcLocalCap 0x1306 +#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0 +#define mmUMCCH3_0_UmcLocalCap 0x1b06 +#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h new file mode 100644 index 000000000000..3e857d1613f0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _umc_6_0_SH_MASK_HEADER +#define _umc_6_0_SH_MASK_HEADER + +#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L +#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa +#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L +#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0 + +#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L +#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f + +#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L +#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h index 07aceffb108a..07aceffb108a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h index b427f73bd536..b427f73bd536 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h index c2a46c7c448c..c2a46c7c448c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h index 109303e1b08d..109303e1b08d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h index 4cf6e4424198..4cf6e4424198 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h index 18a32477ed1d..18a32477ed1d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h index d6ba26922275..d6ba26922275 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/raven1/VCN/vcn_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h deleted file mode 100644 index 1650dc369f7d..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _athub_1_0_DEFAULT_HEADER -#define _athub_1_0_DEFAULT_HEADER - - -// addressBlock: athub_atsdec -#define mmATC_ATS_CNTL_DEFAULT 0x009a0800 -#define mmATC_ATS_STATUS_DEFAULT 0x00000000 -#define mmATC_ATS_FAULT_CNTL_DEFAULT 0x000001ff -#define mmATC_ATS_FAULT_STATUS_INFO_DEFAULT 0x00000000 -#define mmATC_ATS_FAULT_STATUS_ADDR_DEFAULT 0x00000000 -#define mmATC_ATS_DEFAULT_PAGE_LOW_DEFAULT 0x00000000 -#define mmATC_TRANS_FAULT_RSPCNTRL_DEFAULT 0xffffffff -#define mmATC_ATS_FAULT_STATUS_INFO2_DEFAULT 0x00000000 -#define mmATHUB_MISC_CNTL_DEFAULT 0x00040200 -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_DEFAULT 0x00000000 -#define mmATC_VMID0_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID1_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID2_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID3_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID4_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID5_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID6_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID7_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID8_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID9_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID10_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID11_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID12_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID13_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID14_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID15_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_ATS_VMID_STATUS_DEFAULT 0x00000000 -#define mmATC_ATS_GFX_ATCL2_STATUS_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmATC_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmATC_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_DEFAULT 0x00000000 -#define mmATHUB_PCIE_PASID_CNTL_DEFAULT 0x00000000 -#define mmATHUB_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 -#define mmATHUB_COMMAND_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 -#define mmATHUB_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 -#define mmATHUB_MEM_POWER_LS_DEFAULT 0x00000208 -#define mmATS_IH_CREDIT_DEFAULT 0x00150002 -#define mmATHUB_IH_CREDIT_DEFAULT 0x00020002 -#define mmATC_VMID16_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID17_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID18_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID19_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID20_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID21_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID22_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID23_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID24_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID25_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID26_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID27_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID28_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID29_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID30_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_VMID31_PASID_MAPPING_DEFAULT 0x00000000 -#define mmATC_ATS_MMHUB_ATCL2_STATUS_DEFAULT 0x00000000 -#define mmATHUB_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmATHUB_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmATC_ATS_SDPPORT_CNTL_DEFAULT 0x03ffa210 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_DEFAULT 0x00000000 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_DEFAULT 0x00000000 - - -// addressBlock: athub_xpbdec -#define mmXPB_RTR_SRC_APRTR0_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR1_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR2_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR3_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR4_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR5_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR6_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR7_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR8_DEFAULT 0x00000000 -#define mmXPB_RTR_SRC_APRTR9_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR0_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR1_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR2_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_SRC_APRTR3_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP0_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP1_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP2_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP3_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP4_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP5_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP6_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP7_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP8_DEFAULT 0x00000000 -#define mmXPB_RTR_DEST_MAP9_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP0_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP1_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP2_DEFAULT 0x00000000 -#define mmXPB_XDMA_RTR_DEST_MAP3_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG0_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG1_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG2_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG3_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG4_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG5_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG6_DEFAULT 0x00000000 -#define mmXPB_CLG_CFG7_DEFAULT 0x00000000 -#define mmXPB_CLG_EXTRA_DEFAULT 0x00000000 -#define mmXPB_CLG_EXTRA_MSK_DEFAULT 0x00000000 -#define mmXPB_LB_ADDR_DEFAULT 0x00000000 -#define mmXPB_WCB_STS_DEFAULT 0x00000000 -#define mmXPB_HST_CFG_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_CFG_DEFAULT 0x0000000f -#define mmXPB_P2P_BAR0_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR1_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR2_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR3_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR4_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR5_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR6_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR7_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_SETUP_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_DELTA_ABOVE_DEFAULT 0x00000000 -#define mmXPB_P2P_BAR_DELTA_BELOW_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR0_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR1_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR2_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR3_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR4_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR5_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR6_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR7_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR8_DEFAULT 0x00000000 -#define mmXPB_PEER_SYS_BAR9_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR0_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR1_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR2_DEFAULT 0x00000000 -#define mmXPB_XDMA_PEER_SYS_BAR3_DEFAULT 0x00000000 -#define mmXPB_CLK_GAT_DEFAULT 0x00040400 -#define mmXPB_INTF_CFG_DEFAULT 0x000f1040 -#define mmXPB_INTF_STS_DEFAULT 0x00000000 -#define mmXPB_PIPE_STS_DEFAULT 0x00000000 -#define mmXPB_SUB_CTRL_DEFAULT 0x00000000 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_DEFAULT 0x00000000 -#define mmXPB_PERF_KNOBS_DEFAULT 0x00000000 -#define mmXPB_STICKY_DEFAULT 0x00000000 -#define mmXPB_STICKY_W1C_DEFAULT 0x00000000 -#define mmXPB_MISC_CFG_DEFAULT 0x4d585042 -#define mmXPB_INTF_CFG2_DEFAULT 0x00000040 -#define mmXPB_CLG_EXTRA_RD_DEFAULT 0x00000000 -#define mmXPB_CLG_EXTRA_MSK_RD_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_MATCH_DEFAULT 0x03000000 -#define mmXPB_CLG_GFX_MATCH_MSK_DEFAULT 0x00000000 -#define mmXPB_CLG_MM_MATCH_DEFAULT 0x03000000 -#define mmXPB_CLG_MM_MATCH_MSK_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_UNITID_MAPPING0_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_UNITID_MAPPING1_DEFAULT 0x00000040 -#define mmXPB_CLG_GFX_UNITID_MAPPING2_DEFAULT 0x00000080 -#define mmXPB_CLG_GFX_UNITID_MAPPING3_DEFAULT 0x000000c0 -#define mmXPB_CLG_GFX_UNITID_MAPPING4_DEFAULT 0x00000100 -#define mmXPB_CLG_GFX_UNITID_MAPPING5_DEFAULT 0x00000140 -#define mmXPB_CLG_GFX_UNITID_MAPPING6_DEFAULT 0x00000000 -#define mmXPB_CLG_GFX_UNITID_MAPPING7_DEFAULT 0x000001c0 -#define mmXPB_CLG_MM_UNITID_MAPPING0_DEFAULT 0x00000000 -#define mmXPB_CLG_MM_UNITID_MAPPING1_DEFAULT 0x00000040 -#define mmXPB_CLG_MM_UNITID_MAPPING2_DEFAULT 0x00000080 -#define mmXPB_CLG_MM_UNITID_MAPPING3_DEFAULT 0x000000c0 - - -// addressBlock: athub_rpbdec -#define mmRPB_PASSPW_CONF_DEFAULT 0x00000230 -#define mmRPB_BLOCKLEVEL_CONF_DEFAULT 0x000000f0 -#define mmRPB_TAG_CONF_DEFAULT 0x00204020 -#define mmRPB_EFF_CNTL_DEFAULT 0x00001010 -#define mmRPB_ARB_CNTL_DEFAULT 0x00040404 -#define mmRPB_ARB_CNTL2_DEFAULT 0x00040104 -#define mmRPB_BIF_CNTL_DEFAULT 0x01000404 -#define mmRPB_WR_SWITCH_CNTL_DEFAULT 0x02040810 -#define mmRPB_RD_SWITCH_CNTL_DEFAULT 0x02040810 -#define mmRPB_CID_QUEUE_WR_DEFAULT 0x00000000 -#define mmRPB_CID_QUEUE_RD_DEFAULT 0x00000000 -#define mmRPB_CID_QUEUE_EX_DEFAULT 0x00000000 -#define mmRPB_CID_QUEUE_EX_DATA_DEFAULT 0x00000000 -#define mmRPB_SWITCH_CNTL2_DEFAULT 0x02040810 -#define mmRPB_DEINTRLV_COMBINE_CNTL_DEFAULT 0x00000004 -#define mmRPB_VC_SWITCH_RDWR_DEFAULT 0x00004040 -#define mmRPB_PERFCOUNTER_LO_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER_HI_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER0_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER1_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER2_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER3_CFG_DEFAULT 0x00000000 -#define mmRPB_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 -#define mmRPB_RD_QUEUE_CNTL_DEFAULT 0x00000000 -#define mmRPB_RD_QUEUE_CNTL2_DEFAULT 0x00000000 -#define mmRPB_WR_QUEUE_CNTL_DEFAULT 0x00000000 -#define mmRPB_WR_QUEUE_CNTL2_DEFAULT 0x00000000 -#define mmRPB_EA_QUEUE_WR_DEFAULT 0x00000000 -#define mmRPB_ATS_CNTL_DEFAULT 0x58088422 -#define mmRPB_ATS_CNTL2_DEFAULT 0x00050b13 -#define mmRPB_SDPPORT_CNTL_DEFAULT 0x0fd14814 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h deleted file mode 100644 index 80042e1c8770..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h +++ /dev/null @@ -1,453 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _athub_1_0_OFFSET_HEADER -#define _athub_1_0_OFFSET_HEADER - - - -// addressBlock: athub_atsdec -// base address: 0x3080 -#define mmATC_ATS_CNTL 0x0000 -#define mmATC_ATS_CNTL_BASE_IDX 0 -#define mmATC_ATS_STATUS 0x0003 -#define mmATC_ATS_STATUS_BASE_IDX 0 -#define mmATC_ATS_FAULT_CNTL 0x0004 -#define mmATC_ATS_FAULT_CNTL_BASE_IDX 0 -#define mmATC_ATS_FAULT_STATUS_INFO 0x0005 -#define mmATC_ATS_FAULT_STATUS_INFO_BASE_IDX 0 -#define mmATC_ATS_FAULT_STATUS_ADDR 0x0006 -#define mmATC_ATS_FAULT_STATUS_ADDR_BASE_IDX 0 -#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0007 -#define mmATC_ATS_DEFAULT_PAGE_LOW_BASE_IDX 0 -#define mmATC_TRANS_FAULT_RSPCNTRL 0x0008 -#define mmATC_TRANS_FAULT_RSPCNTRL_BASE_IDX 0 -#define mmATC_ATS_FAULT_STATUS_INFO2 0x0009 -#define mmATC_ATS_FAULT_STATUS_INFO2_BASE_IDX 0 -#define mmATHUB_MISC_CNTL 0x000a -#define mmATHUB_MISC_CNTL_BASE_IDX 0 -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x000b -#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS_BASE_IDX 0 -#define mmATC_VMID0_PASID_MAPPING 0x000c -#define mmATC_VMID0_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID1_PASID_MAPPING 0x000d -#define mmATC_VMID1_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID2_PASID_MAPPING 0x000e -#define mmATC_VMID2_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID3_PASID_MAPPING 0x000f -#define mmATC_VMID3_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID4_PASID_MAPPING 0x0010 -#define mmATC_VMID4_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID5_PASID_MAPPING 0x0011 -#define mmATC_VMID5_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID6_PASID_MAPPING 0x0012 -#define mmATC_VMID6_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID7_PASID_MAPPING 0x0013 -#define mmATC_VMID7_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID8_PASID_MAPPING 0x0014 -#define mmATC_VMID8_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID9_PASID_MAPPING 0x0015 -#define mmATC_VMID9_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID10_PASID_MAPPING 0x0016 -#define mmATC_VMID10_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID11_PASID_MAPPING 0x0017 -#define mmATC_VMID11_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID12_PASID_MAPPING 0x0018 -#define mmATC_VMID12_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID13_PASID_MAPPING 0x0019 -#define mmATC_VMID13_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID14_PASID_MAPPING 0x001a -#define mmATC_VMID14_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID15_PASID_MAPPING 0x001b -#define mmATC_VMID15_PASID_MAPPING_BASE_IDX 0 -#define mmATC_ATS_VMID_STATUS 0x001c -#define mmATC_ATS_VMID_STATUS_BASE_IDX 0 -#define mmATC_ATS_GFX_ATCL2_STATUS 0x001d -#define mmATC_ATS_GFX_ATCL2_STATUS_BASE_IDX 0 -#define mmATC_PERFCOUNTER0_CFG 0x001e -#define mmATC_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER1_CFG 0x001f -#define mmATC_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER2_CFG 0x0020 -#define mmATC_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER3_CFG 0x0021 -#define mmATC_PERFCOUNTER3_CFG_BASE_IDX 0 -#define mmATC_PERFCOUNTER_RSLT_CNTL 0x0022 -#define mmATC_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmATC_PERFCOUNTER_LO 0x0023 -#define mmATC_PERFCOUNTER_LO_BASE_IDX 0 -#define mmATC_PERFCOUNTER_HI 0x0024 -#define mmATC_PERFCOUNTER_HI_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL 0x0025 -#define mmATHUB_PCIE_ATS_CNTL_BASE_IDX 0 -#define mmATHUB_PCIE_PASID_CNTL 0x0026 -#define mmATHUB_PCIE_PASID_CNTL_BASE_IDX 0 -#define mmATHUB_PCIE_PAGE_REQ_CNTL 0x0027 -#define mmATHUB_PCIE_PAGE_REQ_CNTL_BASE_IDX 0 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x0028 -#define mmATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 0 -#define mmATHUB_COMMAND 0x0029 -#define mmATHUB_COMMAND_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_0 0x002a -#define mmATHUB_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_1 0x002b -#define mmATHUB_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_2 0x002c -#define mmATHUB_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_3 0x002d -#define mmATHUB_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_4 0x002e -#define mmATHUB_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_5 0x002f -#define mmATHUB_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_6 0x0030 -#define mmATHUB_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_7 0x0031 -#define mmATHUB_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_8 0x0032 -#define mmATHUB_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_9 0x0033 -#define mmATHUB_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_10 0x0034 -#define mmATHUB_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_11 0x0035 -#define mmATHUB_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_12 0x0036 -#define mmATHUB_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_13 0x0037 -#define mmATHUB_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_14 0x0038 -#define mmATHUB_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 -#define mmATHUB_PCIE_ATS_CNTL_VF_15 0x0039 -#define mmATHUB_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 -#define mmATHUB_MEM_POWER_LS 0x003a -#define mmATHUB_MEM_POWER_LS_BASE_IDX 0 -#define mmATS_IH_CREDIT 0x003b -#define mmATS_IH_CREDIT_BASE_IDX 0 -#define mmATHUB_IH_CREDIT 0x003c -#define mmATHUB_IH_CREDIT_BASE_IDX 0 -#define mmATC_VMID16_PASID_MAPPING 0x003d -#define mmATC_VMID16_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID17_PASID_MAPPING 0x003e -#define mmATC_VMID17_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID18_PASID_MAPPING 0x003f -#define mmATC_VMID18_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID19_PASID_MAPPING 0x0040 -#define mmATC_VMID19_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID20_PASID_MAPPING 0x0041 -#define mmATC_VMID20_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID21_PASID_MAPPING 0x0042 -#define mmATC_VMID21_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID22_PASID_MAPPING 0x0043 -#define mmATC_VMID22_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID23_PASID_MAPPING 0x0044 -#define mmATC_VMID23_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID24_PASID_MAPPING 0x0045 -#define mmATC_VMID24_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID25_PASID_MAPPING 0x0046 -#define mmATC_VMID25_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID26_PASID_MAPPING 0x0047 -#define mmATC_VMID26_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID27_PASID_MAPPING 0x0048 -#define mmATC_VMID27_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID28_PASID_MAPPING 0x0049 -#define mmATC_VMID28_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID29_PASID_MAPPING 0x004a -#define mmATC_VMID29_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID30_PASID_MAPPING 0x004b -#define mmATC_VMID30_PASID_MAPPING_BASE_IDX 0 -#define mmATC_VMID31_PASID_MAPPING 0x004c -#define mmATC_VMID31_PASID_MAPPING_BASE_IDX 0 -#define mmATC_ATS_MMHUB_ATCL2_STATUS 0x004d -#define mmATC_ATS_MMHUB_ATCL2_STATUS_BASE_IDX 0 -#define mmATHUB_SHARED_VIRT_RESET_REQ 0x004e -#define mmATHUB_SHARED_VIRT_RESET_REQ_BASE_IDX 0 -#define mmATHUB_SHARED_ACTIVE_FCN_ID 0x004f -#define mmATHUB_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmATC_ATS_SDPPORT_CNTL 0x0050 -#define mmATC_ATS_SDPPORT_CNTL_BASE_IDX 0 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT 0x0052 -#define mmATC_ATS_VMID_SNAPSHOT_GFX_STAT_BASE_IDX 0 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 0x0053 -#define mmATC_ATS_VMID_SNAPSHOT_MMHUB_STAT_BASE_IDX 0 - - -// addressBlock: athub_xpbdec -// base address: 0x31f0 -#define mmXPB_RTR_SRC_APRTR0 0x005c -#define mmXPB_RTR_SRC_APRTR0_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR1 0x005d -#define mmXPB_RTR_SRC_APRTR1_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR2 0x005e -#define mmXPB_RTR_SRC_APRTR2_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR3 0x005f -#define mmXPB_RTR_SRC_APRTR3_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR4 0x0060 -#define mmXPB_RTR_SRC_APRTR4_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR5 0x0061 -#define mmXPB_RTR_SRC_APRTR5_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR6 0x0062 -#define mmXPB_RTR_SRC_APRTR6_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR7 0x0063 -#define mmXPB_RTR_SRC_APRTR7_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR8 0x0064 -#define mmXPB_RTR_SRC_APRTR8_BASE_IDX 0 -#define mmXPB_RTR_SRC_APRTR9 0x0065 -#define mmXPB_RTR_SRC_APRTR9_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR0 0x0066 -#define mmXPB_XDMA_RTR_SRC_APRTR0_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR1 0x0067 -#define mmXPB_XDMA_RTR_SRC_APRTR1_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR2 0x0068 -#define mmXPB_XDMA_RTR_SRC_APRTR2_BASE_IDX 0 -#define mmXPB_XDMA_RTR_SRC_APRTR3 0x0069 -#define mmXPB_XDMA_RTR_SRC_APRTR3_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP0 0x006a -#define mmXPB_RTR_DEST_MAP0_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP1 0x006b -#define mmXPB_RTR_DEST_MAP1_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP2 0x006c -#define mmXPB_RTR_DEST_MAP2_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP3 0x006d -#define mmXPB_RTR_DEST_MAP3_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP4 0x006e -#define mmXPB_RTR_DEST_MAP4_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP5 0x006f -#define mmXPB_RTR_DEST_MAP5_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP6 0x0070 -#define mmXPB_RTR_DEST_MAP6_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP7 0x0071 -#define mmXPB_RTR_DEST_MAP7_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP8 0x0072 -#define mmXPB_RTR_DEST_MAP8_BASE_IDX 0 -#define mmXPB_RTR_DEST_MAP9 0x0073 -#define mmXPB_RTR_DEST_MAP9_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP0 0x0074 -#define mmXPB_XDMA_RTR_DEST_MAP0_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP1 0x0075 -#define mmXPB_XDMA_RTR_DEST_MAP1_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP2 0x0076 -#define mmXPB_XDMA_RTR_DEST_MAP2_BASE_IDX 0 -#define mmXPB_XDMA_RTR_DEST_MAP3 0x0077 -#define mmXPB_XDMA_RTR_DEST_MAP3_BASE_IDX 0 -#define mmXPB_CLG_CFG0 0x0078 -#define mmXPB_CLG_CFG0_BASE_IDX 0 -#define mmXPB_CLG_CFG1 0x0079 -#define mmXPB_CLG_CFG1_BASE_IDX 0 -#define mmXPB_CLG_CFG2 0x007a -#define mmXPB_CLG_CFG2_BASE_IDX 0 -#define mmXPB_CLG_CFG3 0x007b -#define mmXPB_CLG_CFG3_BASE_IDX 0 -#define mmXPB_CLG_CFG4 0x007c -#define mmXPB_CLG_CFG4_BASE_IDX 0 -#define mmXPB_CLG_CFG5 0x007d -#define mmXPB_CLG_CFG5_BASE_IDX 0 -#define mmXPB_CLG_CFG6 0x007e -#define mmXPB_CLG_CFG6_BASE_IDX 0 -#define mmXPB_CLG_CFG7 0x007f -#define mmXPB_CLG_CFG7_BASE_IDX 0 -#define mmXPB_CLG_EXTRA 0x0080 -#define mmXPB_CLG_EXTRA_BASE_IDX 0 -#define mmXPB_CLG_EXTRA_MSK 0x0081 -#define mmXPB_CLG_EXTRA_MSK_BASE_IDX 0 -#define mmXPB_LB_ADDR 0x0082 -#define mmXPB_LB_ADDR_BASE_IDX 0 -#define mmXPB_WCB_STS 0x0083 -#define mmXPB_WCB_STS_BASE_IDX 0 -#define mmXPB_HST_CFG 0x0084 -#define mmXPB_HST_CFG_BASE_IDX 0 -#define mmXPB_P2P_BAR_CFG 0x0085 -#define mmXPB_P2P_BAR_CFG_BASE_IDX 0 -#define mmXPB_P2P_BAR0 0x0086 -#define mmXPB_P2P_BAR0_BASE_IDX 0 -#define mmXPB_P2P_BAR1 0x0087 -#define mmXPB_P2P_BAR1_BASE_IDX 0 -#define mmXPB_P2P_BAR2 0x0088 -#define mmXPB_P2P_BAR2_BASE_IDX 0 -#define mmXPB_P2P_BAR3 0x0089 -#define mmXPB_P2P_BAR3_BASE_IDX 0 -#define mmXPB_P2P_BAR4 0x008a -#define mmXPB_P2P_BAR4_BASE_IDX 0 -#define mmXPB_P2P_BAR5 0x008b -#define mmXPB_P2P_BAR5_BASE_IDX 0 -#define mmXPB_P2P_BAR6 0x008c -#define mmXPB_P2P_BAR6_BASE_IDX 0 -#define mmXPB_P2P_BAR7 0x008d -#define mmXPB_P2P_BAR7_BASE_IDX 0 -#define mmXPB_P2P_BAR_SETUP 0x008e -#define mmXPB_P2P_BAR_SETUP_BASE_IDX 0 -#define mmXPB_P2P_BAR_DELTA_ABOVE 0x0090 -#define mmXPB_P2P_BAR_DELTA_ABOVE_BASE_IDX 0 -#define mmXPB_P2P_BAR_DELTA_BELOW 0x0091 -#define mmXPB_P2P_BAR_DELTA_BELOW_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR0 0x0092 -#define mmXPB_PEER_SYS_BAR0_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR1 0x0093 -#define mmXPB_PEER_SYS_BAR1_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR2 0x0094 -#define mmXPB_PEER_SYS_BAR2_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR3 0x0095 -#define mmXPB_PEER_SYS_BAR3_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR4 0x0096 -#define mmXPB_PEER_SYS_BAR4_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR5 0x0097 -#define mmXPB_PEER_SYS_BAR5_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR6 0x0098 -#define mmXPB_PEER_SYS_BAR6_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR7 0x0099 -#define mmXPB_PEER_SYS_BAR7_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR8 0x009a -#define mmXPB_PEER_SYS_BAR8_BASE_IDX 0 -#define mmXPB_PEER_SYS_BAR9 0x009b -#define mmXPB_PEER_SYS_BAR9_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR0 0x009c -#define mmXPB_XDMA_PEER_SYS_BAR0_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR1 0x009d -#define mmXPB_XDMA_PEER_SYS_BAR1_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR2 0x009e -#define mmXPB_XDMA_PEER_SYS_BAR2_BASE_IDX 0 -#define mmXPB_XDMA_PEER_SYS_BAR3 0x009f -#define mmXPB_XDMA_PEER_SYS_BAR3_BASE_IDX 0 -#define mmXPB_CLK_GAT 0x00a0 -#define mmXPB_CLK_GAT_BASE_IDX 0 -#define mmXPB_INTF_CFG 0x00a1 -#define mmXPB_INTF_CFG_BASE_IDX 0 -#define mmXPB_INTF_STS 0x00a2 -#define mmXPB_INTF_STS_BASE_IDX 0 -#define mmXPB_PIPE_STS 0x00a3 -#define mmXPB_PIPE_STS_BASE_IDX 0 -#define mmXPB_SUB_CTRL 0x00a4 -#define mmXPB_SUB_CTRL_BASE_IDX 0 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB 0x00a5 -#define mmXPB_MAP_INVERT_FLUSH_NUM_LSB_BASE_IDX 0 -#define mmXPB_PERF_KNOBS 0x00a6 -#define mmXPB_PERF_KNOBS_BASE_IDX 0 -#define mmXPB_STICKY 0x00a7 -#define mmXPB_STICKY_BASE_IDX 0 -#define mmXPB_STICKY_W1C 0x00a8 -#define mmXPB_STICKY_W1C_BASE_IDX 0 -#define mmXPB_MISC_CFG 0x00a9 -#define mmXPB_MISC_CFG_BASE_IDX 0 -#define mmXPB_INTF_CFG2 0x00aa -#define mmXPB_INTF_CFG2_BASE_IDX 0 -#define mmXPB_CLG_EXTRA_RD 0x00ab -#define mmXPB_CLG_EXTRA_RD_BASE_IDX 0 -#define mmXPB_CLG_EXTRA_MSK_RD 0x00ac -#define mmXPB_CLG_EXTRA_MSK_RD_BASE_IDX 0 -#define mmXPB_CLG_GFX_MATCH 0x00ad -#define mmXPB_CLG_GFX_MATCH_BASE_IDX 0 -#define mmXPB_CLG_GFX_MATCH_MSK 0x00ae -#define mmXPB_CLG_GFX_MATCH_MSK_BASE_IDX 0 -#define mmXPB_CLG_MM_MATCH 0x00af -#define mmXPB_CLG_MM_MATCH_BASE_IDX 0 -#define mmXPB_CLG_MM_MATCH_MSK 0x00b0 -#define mmXPB_CLG_MM_MATCH_MSK_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING0 0x00b1 -#define mmXPB_CLG_GFX_UNITID_MAPPING0_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING1 0x00b2 -#define mmXPB_CLG_GFX_UNITID_MAPPING1_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING2 0x00b3 -#define mmXPB_CLG_GFX_UNITID_MAPPING2_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING3 0x00b4 -#define mmXPB_CLG_GFX_UNITID_MAPPING3_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING4 0x00b5 -#define mmXPB_CLG_GFX_UNITID_MAPPING4_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING5 0x00b6 -#define mmXPB_CLG_GFX_UNITID_MAPPING5_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING6 0x00b7 -#define mmXPB_CLG_GFX_UNITID_MAPPING6_BASE_IDX 0 -#define mmXPB_CLG_GFX_UNITID_MAPPING7 0x00b8 -#define mmXPB_CLG_GFX_UNITID_MAPPING7_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING0 0x00b9 -#define mmXPB_CLG_MM_UNITID_MAPPING0_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING1 0x00ba -#define mmXPB_CLG_MM_UNITID_MAPPING1_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING2 0x00bb -#define mmXPB_CLG_MM_UNITID_MAPPING2_BASE_IDX 0 -#define mmXPB_CLG_MM_UNITID_MAPPING3 0x00bc -#define mmXPB_CLG_MM_UNITID_MAPPING3_BASE_IDX 0 - - -// addressBlock: athub_rpbdec -// base address: 0x33b0 -#define mmRPB_PASSPW_CONF 0x00cc -#define mmRPB_PASSPW_CONF_BASE_IDX 0 -#define mmRPB_BLOCKLEVEL_CONF 0x00cd -#define mmRPB_BLOCKLEVEL_CONF_BASE_IDX 0 -#define mmRPB_TAG_CONF 0x00cf -#define mmRPB_TAG_CONF_BASE_IDX 0 -#define mmRPB_EFF_CNTL 0x00d1 -#define mmRPB_EFF_CNTL_BASE_IDX 0 -#define mmRPB_ARB_CNTL 0x00d2 -#define mmRPB_ARB_CNTL_BASE_IDX 0 -#define mmRPB_ARB_CNTL2 0x00d3 -#define mmRPB_ARB_CNTL2_BASE_IDX 0 -#define mmRPB_BIF_CNTL 0x00d4 -#define mmRPB_BIF_CNTL_BASE_IDX 0 -#define mmRPB_WR_SWITCH_CNTL 0x00d5 -#define mmRPB_WR_SWITCH_CNTL_BASE_IDX 0 -#define mmRPB_RD_SWITCH_CNTL 0x00d7 -#define mmRPB_RD_SWITCH_CNTL_BASE_IDX 0 -#define mmRPB_CID_QUEUE_WR 0x00d8 -#define mmRPB_CID_QUEUE_WR_BASE_IDX 0 -#define mmRPB_CID_QUEUE_RD 0x00d9 -#define mmRPB_CID_QUEUE_RD_BASE_IDX 0 -#define mmRPB_CID_QUEUE_EX 0x00dc -#define mmRPB_CID_QUEUE_EX_BASE_IDX 0 -#define mmRPB_CID_QUEUE_EX_DATA 0x00dd -#define mmRPB_CID_QUEUE_EX_DATA_BASE_IDX 0 -#define mmRPB_SWITCH_CNTL2 0x00de -#define mmRPB_SWITCH_CNTL2_BASE_IDX 0 -#define mmRPB_DEINTRLV_COMBINE_CNTL 0x00df -#define mmRPB_DEINTRLV_COMBINE_CNTL_BASE_IDX 0 -#define mmRPB_VC_SWITCH_RDWR 0x00e0 -#define mmRPB_VC_SWITCH_RDWR_BASE_IDX 0 -#define mmRPB_PERFCOUNTER_LO 0x00e1 -#define mmRPB_PERFCOUNTER_LO_BASE_IDX 0 -#define mmRPB_PERFCOUNTER_HI 0x00e2 -#define mmRPB_PERFCOUNTER_HI_BASE_IDX 0 -#define mmRPB_PERFCOUNTER0_CFG 0x00e3 -#define mmRPB_PERFCOUNTER0_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER1_CFG 0x00e4 -#define mmRPB_PERFCOUNTER1_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER2_CFG 0x00e5 -#define mmRPB_PERFCOUNTER2_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER3_CFG 0x00e6 -#define mmRPB_PERFCOUNTER3_CFG_BASE_IDX 0 -#define mmRPB_PERFCOUNTER_RSLT_CNTL 0x00e7 -#define mmRPB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 -#define mmRPB_RD_QUEUE_CNTL 0x00e9 -#define mmRPB_RD_QUEUE_CNTL_BASE_IDX 0 -#define mmRPB_RD_QUEUE_CNTL2 0x00ea -#define mmRPB_RD_QUEUE_CNTL2_BASE_IDX 0 -#define mmRPB_WR_QUEUE_CNTL 0x00eb -#define mmRPB_WR_QUEUE_CNTL_BASE_IDX 0 -#define mmRPB_WR_QUEUE_CNTL2 0x00ec -#define mmRPB_WR_QUEUE_CNTL2_BASE_IDX 0 -#define mmRPB_EA_QUEUE_WR 0x00ed -#define mmRPB_EA_QUEUE_WR_BASE_IDX 0 -#define mmRPB_ATS_CNTL 0x00ee -#define mmRPB_ATS_CNTL_BASE_IDX 0 -#define mmRPB_ATS_CNTL2 0x00ef -#define mmRPB_ATS_CNTL2_BASE_IDX 0 -#define mmRPB_SDPPORT_CNTL 0x00f0 -#define mmRPB_SDPPORT_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h deleted file mode 100644 index 777b05c89708..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h +++ /dev/null @@ -1,2045 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _athub_1_0_SH_MASK_HEADER -#define _athub_1_0_SH_MASK_HEADER - - -// addressBlock: athub_atsdec -//ATC_ATS_CNTL -#define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 -#define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 -#define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 -#define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 -#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 -#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 -#define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 -#define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L -#define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L -#define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L -#define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L -#define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L -#define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L -#define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L -//ATC_ATS_STATUS -#define ATC_ATS_STATUS__BUSY__SHIFT 0x0 -#define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 -#define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 -#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 -#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 -#define ATC_ATS_STATUS__BUSY_MASK 0x00000001L -#define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L -#define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L -#define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L -#define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L -//ATC_ATS_FAULT_CNTL -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 -#define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL -#define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L -#define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L -//ATC_ATS_FAULT_STATUS_INFO -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 -#define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 -#define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 -#define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL -#define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L -#define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L -#define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L -#define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L -#define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L -//ATC_ATS_FAULT_STATUS_ADDR -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 -#define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL -//ATC_ATS_DEFAULT_PAGE_LOW -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 -#define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL -//ATC_TRANS_FAULT_RSPCNTRL -#define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa -#define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb -#define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc -#define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd -#define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe -#define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf -#define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 -#define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a -#define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b -#define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c -#define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d -#define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e -#define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f -#define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L -#define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L -//ATC_ATS_FAULT_STATUS_INFO2 -#define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 -#define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 -#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 -#define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L -#define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL -#define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L -//ATHUB_MISC_CNTL -#define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 -#define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 -#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 -#define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 -#define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 -#define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b -#define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c -#define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L -#define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L -#define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L -#define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L -#define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L -#define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L -#define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L -//ATC_VMID_PASID_MAPPING_UPDATE_STATUS -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L -#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L -//ATC_VMID0_PASID_MAPPING -#define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID1_PASID_MAPPING -#define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID2_PASID_MAPPING -#define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID3_PASID_MAPPING -#define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID4_PASID_MAPPING -#define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID5_PASID_MAPPING -#define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID6_PASID_MAPPING -#define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID7_PASID_MAPPING -#define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID8_PASID_MAPPING -#define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID9_PASID_MAPPING -#define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID10_PASID_MAPPING -#define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID11_PASID_MAPPING -#define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID12_PASID_MAPPING -#define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID13_PASID_MAPPING -#define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID14_PASID_MAPPING -#define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID15_PASID_MAPPING -#define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_ATS_VMID_STATUS -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf -#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 -#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 -#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 -#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 -#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 -#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 -#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 -#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 -#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 -#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 -#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a -#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b -#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c -#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d -#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e -#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f -#define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L -#define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L -#define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L -#define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L -#define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L -#define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L -#define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L -#define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L -#define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L -#define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L -#define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L -#define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L -#define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L -#define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L -#define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L -#define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L -#define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L -#define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L -#define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L -#define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L -#define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L -#define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L -#define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L -#define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L -#define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L -#define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L -#define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L -#define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L -#define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L -#define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L -#define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L -#define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L -//ATC_ATS_GFX_ATCL2_STATUS -#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 -#define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L -//ATC_PERFCOUNTER0_CFG -#define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER1_CFG -#define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER2_CFG -#define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER3_CFG -#define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//ATC_PERFCOUNTER_RSLT_CNTL -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//ATC_PERFCOUNTER_LO -#define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//ATC_PERFCOUNTER_HI -#define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//ATHUB_PCIE_ATS_CNTL -#define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 -#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L -#define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_PASID_CNTL -#define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 -#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 -#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 -#define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L -#define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L -#define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L -//ATHUB_PCIE_PAGE_REQ_CNTL -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L -#define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L -//ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC -#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 -#define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL -//ATHUB_COMMAND -#define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 -#define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L -//ATHUB_PCIE_ATS_CNTL_VF_0 -#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_1 -#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_2 -#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_3 -#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_4 -#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_5 -#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_6 -#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_7 -#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_8 -#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_9 -#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_10 -#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_11 -#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_12 -#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_13 -#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_14 -#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L -//ATHUB_PCIE_ATS_CNTL_VF_15 -#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f -#define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L -//ATHUB_MEM_POWER_LS -#define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 -#define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 -#define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL -#define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L -//ATS_IH_CREDIT -#define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 -#define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L -//ATHUB_IH_CREDIT -#define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 -#define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L -//ATC_VMID16_PASID_MAPPING -#define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID17_PASID_MAPPING -#define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID18_PASID_MAPPING -#define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID19_PASID_MAPPING -#define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID20_PASID_MAPPING -#define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID21_PASID_MAPPING -#define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID22_PASID_MAPPING -#define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID23_PASID_MAPPING -#define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID24_PASID_MAPPING -#define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID25_PASID_MAPPING -#define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID26_PASID_MAPPING -#define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID27_PASID_MAPPING -#define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID28_PASID_MAPPING -#define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID29_PASID_MAPPING -#define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID30_PASID_MAPPING -#define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_VMID31_PASID_MAPPING -#define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 -#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e -#define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f -#define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL -#define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L -#define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L -//ATC_ATS_MMHUB_ATCL2_STATUS -#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 -#define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L -//ATHUB_SHARED_VIRT_RESET_REQ -#define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L -//ATHUB_SHARED_ACTIVE_FCN_ID -#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//ATC_ATS_SDPPORT_CNTL -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe -#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L -#define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L -#define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L -//ATC_ATS_VMID_SNAPSHOT_GFX_STAT -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L -#define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L -//ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L -#define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L - - -// addressBlock: athub_xpbdec -//XPB_RTR_SRC_APRTR0 -#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR1 -#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR2 -#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR3 -#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR4 -#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR5 -#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR6 -#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR7 -#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR8 -#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_SRC_APRTR9 -#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 -#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR0 -#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR1 -#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR2 -#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_XDMA_RTR_SRC_APRTR3 -#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 -#define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL -//XPB_RTR_DEST_MAP0 -#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP1 -#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP2 -#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP3 -#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP4 -#define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP5 -#define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP6 -#define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP7 -#define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP8 -#define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L -//XPB_RTR_DEST_MAP9 -#define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 -#define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 -#define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 -#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a -#define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L -#define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L -#define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP0 -#define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP1 -#define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP2 -#define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L -//XPB_XDMA_RTR_DEST_MAP3 -#define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 -#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a -#define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L -#define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L -#define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L -#define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L -//XPB_CLG_CFG0 -#define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG1 -#define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG2 -#define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG3 -#define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG4 -#define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG5 -#define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG6 -#define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_CFG7 -#define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 -#define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 -#define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa -#define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL -#define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L -#define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L -//XPB_CLG_EXTRA -#define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA__VLD0__SHIFT 0xb -#define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc -#define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf -#define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 -#define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a -#define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b -#define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L -#define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L -#define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L -#define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L -#define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L -#define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L -//XPB_CLG_EXTRA_MSK -#define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb -#define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 -#define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L -#define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L -//XPB_LB_ADDR -#define XPB_LB_ADDR__CMP0__SHIFT 0x0 -#define XPB_LB_ADDR__MASK0__SHIFT 0xa -#define XPB_LB_ADDR__CMP1__SHIFT 0x14 -#define XPB_LB_ADDR__MASK1__SHIFT 0x1a -#define XPB_LB_ADDR__CMP0_MASK 0x000003FFL -#define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L -#define XPB_LB_ADDR__CMP1_MASK 0x03F00000L -#define XPB_LB_ADDR__MASK1_MASK 0xFC000000L -//XPB_WCB_STS -#define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 -#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 -#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 -#define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL -#define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L -#define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L -//XPB_HST_CFG -#define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 -#define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L -//XPB_P2P_BAR_CFG -#define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 -#define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 -#define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 -#define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 -#define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 -#define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 -#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa -#define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb -#define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc -#define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL -#define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L -#define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L -#define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L -#define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L -#define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L -#define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L -#define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L -#define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L -//XPB_P2P_BAR0 -#define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR0__VALID__SHIFT 0xc -#define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR0__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR0__VALID_MASK 0x00001000L -#define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR1 -#define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR1__VALID__SHIFT 0xc -#define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR1__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR1__VALID_MASK 0x00001000L -#define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR2 -#define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR2__VALID__SHIFT 0xc -#define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR2__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR2__VALID_MASK 0x00001000L -#define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR3 -#define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR3__VALID__SHIFT 0xc -#define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR3__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR3__VALID_MASK 0x00001000L -#define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR4 -#define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR4__VALID__SHIFT 0xc -#define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR4__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR4__VALID_MASK 0x00001000L -#define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR5 -#define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR5__VALID__SHIFT 0xc -#define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR5__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR5__VALID_MASK 0x00001000L -#define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR6 -#define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR6__VALID__SHIFT 0xc -#define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR6__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR6__VALID_MASK 0x00001000L -#define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR7 -#define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 -#define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 -#define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR7__VALID__SHIFT 0xc -#define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR7__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL -#define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L -#define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR7__VALID_MASK 0x00001000L -#define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR_SETUP -#define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 -#define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 -#define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc -#define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd -#define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe -#define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf -#define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 -#define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL -#define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L -#define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L -#define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L -#define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L -#define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L -#define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L -//XPB_P2P_BAR_DELTA_ABOVE -#define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 -#define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 -#define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL -#define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L -//XPB_P2P_BAR_DELTA_BELOW -#define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 -#define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 -#define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL -#define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L -//XPB_PEER_SYS_BAR0 -#define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR1 -#define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR2 -#define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR3 -#define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR4 -#define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR5 -#define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR6 -#define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR7 -#define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR8 -#define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL -//XPB_PEER_SYS_BAR9 -#define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 -#define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 -#define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L -#define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR0 -#define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR1 -#define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR2 -#define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL -//XPB_XDMA_PEER_SYS_BAR3 -#define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 -#define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 -#define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L -#define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL -//XPB_CLK_GAT -#define XPB_CLK_GAT__ONDLY__SHIFT 0x0 -#define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 -#define XPB_CLK_GAT__RDYDLY__SHIFT 0xc -#define XPB_CLK_GAT__ENABLE__SHIFT 0x12 -#define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 -#define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL -#define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L -#define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L -#define XPB_CLK_GAT__ENABLE_MASK 0x00040000L -#define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L -//XPB_INTF_CFG -#define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 -#define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 -#define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 -#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 -#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 -#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 -#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a -#define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b -#define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d -#define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e -#define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f -#define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL -#define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L -#define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L -#define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L -#define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L -#define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L -#define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L -#define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L -#define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L -#define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L -#define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L -//XPB_INTF_STS -#define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 -#define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 -#define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf -#define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 -#define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 -#define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 -#define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 -#define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL -#define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L -#define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L -#define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L -#define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L -#define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L -#define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L -//XPB_PIPE_STS -#define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 -#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 -#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 -#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf -#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 -#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 -#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 -#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 -#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 -#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 -#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 -#define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 -#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 -#define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L -#define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL -#define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L -#define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L -#define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L -#define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L -#define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L -#define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L -#define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L -#define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L -#define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L -#define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L -#define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L -//XPB_SUB_CTRL -#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 -#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 -#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 -#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 -#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 -#define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 -#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 -#define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 -#define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 -#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 -#define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa -#define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb -#define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc -#define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd -#define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe -#define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf -#define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 -#define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 -#define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 -#define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 -#define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L -#define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L -#define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L -#define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L -#define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L -#define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L -#define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L -#define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L -#define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L -#define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L -#define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L -#define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L -#define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L -#define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L -#define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L -#define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L -#define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L -#define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L -#define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L -#define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L -//XPB_MAP_INVERT_FLUSH_NUM_LSB -#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 -#define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL -//XPB_PERF_KNOBS -#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 -#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 -#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc -#define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL -#define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L -#define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L -//XPB_STICKY -#define XPB_STICKY__BITS__SHIFT 0x0 -#define XPB_STICKY__BITS_MASK 0xFFFFFFFFL -//XPB_STICKY_W1C -#define XPB_STICKY_W1C__BITS__SHIFT 0x0 -#define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL -//XPB_MISC_CFG -#define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 -#define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 -#define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 -#define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 -#define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f -#define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL -#define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L -#define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L -#define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L -#define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L -//XPB_INTF_CFG2 -#define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 -#define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL -//XPB_CLG_EXTRA_RD -#define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb -#define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc -#define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf -#define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 -#define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a -#define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b -#define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L -#define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L -#define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L -#define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L -#define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L -#define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L -//XPB_CLG_EXTRA_MSK_RD -#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 -#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 -#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb -#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 -#define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL -#define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L -#define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L -#define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L -//XPB_CLG_GFX_MATCH -#define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 -#define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 -#define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc -#define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 -#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 -#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 -#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a -#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b -#define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL -#define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L -#define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L -#define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L -#define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L -#define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L -#define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L -#define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L -//XPB_CLG_GFX_MATCH_MSK -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L -#define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L -//XPB_CLG_MM_MATCH -#define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 -#define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 -#define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc -#define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 -#define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 -#define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 -#define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a -#define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b -#define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL -#define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L -#define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L -#define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L -#define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L -#define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L -#define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L -#define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L -//XPB_CLG_MM_MATCH_MSK -#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc -#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 -#define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL -#define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L -#define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L -#define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L -//XPB_CLG_GFX_UNITID_MAPPING0 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING1 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING2 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING3 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING4 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING5 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING6 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_GFX_UNITID_MAPPING7 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING0 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING1 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING2 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L -//XPB_CLG_MM_UNITID_MAPPING3 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 -#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL -#define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L -#define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L - - -// addressBlock: athub_rpbdec -//RPB_PASSPW_CONF -#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 -#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 -#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 -#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 -#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 -#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 -#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 -#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 -#define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L -#define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L -#define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L -#define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L -#define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L -#define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L -#define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L -#define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L -#define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L -#define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L -#define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L -#define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L -#define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L -//RPB_BLOCKLEVEL_CONF -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 -#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 -#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 -#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L -#define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL -#define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L -#define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L -#define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L -#define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L -#define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L -#define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L -//RPB_TAG_CONF -#define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 -#define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 -#define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 -#define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL -#define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L -#define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L -//RPB_EFF_CNTL -#define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 -#define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 -#define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL -#define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L -//RPB_ARB_CNTL -#define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 -#define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 -#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 -#define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 -#define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 -#define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL -#define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L -#define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L -#define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L -#define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L -//RPB_ARB_CNTL2 -#define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 -#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 -#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 -#define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL -#define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L -#define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L -//RPB_BIF_CNTL -#define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 -#define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 -#define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 -#define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 -#define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 -#define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 -#define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b -#define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c -#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d -#define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e -#define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL -#define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L -#define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L -#define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L -#define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L -#define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L -#define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L -#define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L -#define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L -#define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L -//RPB_WR_SWITCH_CNTL -#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 -#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 -#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe -#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 -#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c -#define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL -#define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L -#define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L -#define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L -#define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L -//RPB_RD_SWITCH_CNTL -#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 -#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 -#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe -#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 -#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c -#define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL -#define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L -#define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L -#define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L -#define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L -//RPB_CID_QUEUE_WR -#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 -#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 -#define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb -#define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc -#define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf -#define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 -#define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL -#define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L -#define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L -#define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L -#define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L -#define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L -//RPB_CID_QUEUE_RD -#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 -#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 -#define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb -#define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe -#define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL -#define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L -#define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L -#define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L -//RPB_CID_QUEUE_EX -#define RPB_CID_QUEUE_EX__START__SHIFT 0x0 -#define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 -#define RPB_CID_QUEUE_EX__START_MASK 0x00000001L -#define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL -//RPB_CID_QUEUE_EX_DATA -#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 -#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 -#define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL -#define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L -//RPB_SWITCH_CNTL2 -#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 -#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 -#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe -#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 -#define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL -#define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L -#define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L -#define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L -//RPB_DEINTRLV_COMBINE_CNTL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL -#define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L -#define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L -//RPB_VC_SWITCH_RDWR -#define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 -#define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 -#define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa -#define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L -#define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL -#define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L -//RPB_PERFCOUNTER_LO -#define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 -#define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL -//RPB_PERFCOUNTER_HI -#define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 -#define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 -#define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL -#define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L -//RPB_PERFCOUNTER0_CFG -#define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER1_CFG -#define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER2_CFG -#define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER3_CFG -#define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 -#define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 -#define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c -#define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL -#define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L -#define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L -#define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L -#define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L -//RPB_PERFCOUNTER_RSLT_CNTL -#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 -#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 -#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 -#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a -#define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL -#define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L -#define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L -#define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L -#define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L -//RPB_RD_QUEUE_CNTL -#define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 -#define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 -#define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 -#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 -#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 -#define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L -#define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L -#define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L -#define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L -#define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L -#define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L -#define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L -//RPB_RD_QUEUE_CNTL2 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL -#define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L -#define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L -//RPB_WR_QUEUE_CNTL -#define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 -#define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 -#define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 -#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 -#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 -#define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L -#define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L -#define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L -#define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L -#define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L -#define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L -#define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L -//RPB_WR_QUEUE_CNTL2 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL -#define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L -#define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L -//RPB_EA_QUEUE_WR -#define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 -#define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 -#define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 -#define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb -#define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL -#define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L -#define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L -#define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L -//RPB_ATS_CNTL -#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 -#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 -#define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 -#define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 -#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf -#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 -#define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 -#define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 -#define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L -#define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L -#define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL -#define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L -#define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L -#define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L -#define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L -#define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L -//RPB_ATS_CNTL2 -#define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 -#define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 -#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc -#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf -#define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 -#define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL -#define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L -#define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L -#define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L -#define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L -//RPB_SDPPORT_CNTL -#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 -#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 -#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 -#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa -#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf -#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 -#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 -#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b -#define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L -#define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L -#define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L -#define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L -#define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L -#define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L -#define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L -#define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L -#define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L -#define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L -#define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h deleted file mode 100644 index 8a0007ce43dc..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h +++ /dev/null @@ -1,9868 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _dce_12_0_DEFAULT_HEADER -#define _dce_12_0_DEFAULT_HEADER - - -// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR -#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR -#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon0_dispdec -#define mmDC_PERFMON0_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON0_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON0_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon13_dispdec -#define mmDC_PERFMON13_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON13_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON13_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_displaypllregs_dispdec -#define mmPPLL_VREG_CFG_DEFAULT 0x00000000 -#define mmPPLL_MODE_CNTL_DEFAULT 0x00020100 -#define mmPPLL_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmPPLL_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmPPLL_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmPPLL_FREQ_CTRL3_DEFAULT 0x00190040 -#define mmPPLL_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmPPLL_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmPPLL_CAL_CTRL_DEFAULT 0x64000002 -#define mmPPLL_LOOP_CTRL_DEFAULT 0x00000090 -#define mmPPLL_REFCLK_CNTL_DEFAULT 0x00018004 -#define mmPPLL_CLKOUT_CNTL_DEFAULT 0x00022500 -#define mmPPLL_DFT_CNTL_DEFAULT 0x00000004 -#define mmPPLL_ANALOG_CNTL_DEFAULT 0x00000000 -#define mmPPLL_POSTDIV_DEFAULT 0x00000400 -#define mmPPLL_OBSERVE0_DEFAULT 0x00000000 -#define mmPPLL_OBSERVE1_DEFAULT 0x04b00000 -#define mmPPLL_UPDATE_CNTL_DEFAULT 0x00000000 -#define mmPPLL_OBSERVE0_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dccg_pll0_dispdec -#define mmPLL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmPLL_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon1_dispdec -#define mmDC_PERFMON1_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON1_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON1_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_mcif_wb0_dispdec -#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB0_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mcif_wb1_dispdec -#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB1_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_mcif_wb2_dispdec -#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_DEFAULT 0x04000400 -#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_DEFAULT 0x00000008 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_DEFAULT 0x000f0000 -#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_DEFAULT 0x00000040 -#define mmMCIF_WB2_MCIF_WB_WATERMARK_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_DEFAULT 0x00001000 -#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_DEFAULT 0x00000002 -#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_DEFAULT 0x00000080 -#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_DEFAULT 0x000fffff -#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_DEFAULT 0x000fffff - - -// addressBlock: dce_dc_cwb0_dispdec -#define mmCWB0_CWB_CTRL_DEFAULT 0x00000110 -#define mmCWB0_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff -#define mmCWB0_CWB_FENCE_PAR1_DEFAULT 0x000102ff -#define mmCWB0_CWB_CRC_CTRL_DEFAULT 0x00000000 -#define mmCWB0_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmCWB0_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff -#define mmCWB0_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000 -#define mmCWB0_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_cwb1_dispdec -#define mmCWB1_CWB_CTRL_DEFAULT 0x00000110 -#define mmCWB1_CWB_FENCE_PAR0_DEFAULT 0x03ff03ff -#define mmCWB1_CWB_FENCE_PAR1_DEFAULT 0x000102ff -#define mmCWB1_CWB_CRC_CTRL_DEFAULT 0x00000000 -#define mmCWB1_CWB_CRC_RED_GREEN_MASK_DEFAULT 0xffffffff -#define mmCWB1_CWB_CRC_BLUE_MASK_DEFAULT 0x0000ffff -#define mmCWB1_CWB_CRC_RED_GREEN_RESULT_DEFAULT 0x00000000 -#define mmCWB1_CWB_CRC_BLUE_RESULT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon9_dispdec -#define mmDC_PERFMON9_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON9_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON9_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dispdec -#define mmVGA_MEM_WRITE_PAGE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEM_READ_PAGE_ADDR_DEFAULT 0x00000000 -#define mmVGA_RENDER_CONTROL_DEFAULT 0x0000000f -#define mmVGA_SEQUENCER_RESET_CONTROL_DEFAULT 0x00003f3f -#define mmVGA_MODE_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SURFACE_PITCH_SELECT_DEFAULT 0x00000002 -#define mmVGA_MEMORY_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmVGA_DISPBUF1_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_DISPBUF2_SURFACE_ADDR_DEFAULT 0x00000000 -#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmVGA_HDP_CONTROL_DEFAULT 0x00000000 -#define mmVGA_CACHE_CONTROL_DEFAULT 0x00000000 -#define mmD1VGA_CONTROL_DEFAULT 0x00000000 -#define mmD2VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmVGA_STATUS_CLEAR_DEFAULT 0x00000000 -#define mmVGA_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmVGA_MAIN_CONTROL_DEFAULT 0x00005018 -#define mmVGA_TEST_CONTROL_DEFAULT 0x00000000 -#define mmVGA_QOS_CTRL_DEFAULT 0x00000000 -#define mmCRTC8_IDX_DEFAULT 0x00000000 -#define mmCRTC8_DATA_DEFAULT 0x00000000 -#define mmGENFC_WT_DEFAULT 0x00000000 -#define mmGENS1_DEFAULT 0x00000000 -#define mmATTRDW_DEFAULT 0x00000000 -#define mmATTRX_DEFAULT 0x00000000 -#define mmATTRDR_DEFAULT 0x00000000 -#define mmGENMO_WT_DEFAULT 0x00000000 -#define mmGENS0_DEFAULT 0x00000000 -#define mmGENENB_DEFAULT 0x00000000 -#define mmSEQ8_IDX_DEFAULT 0x00000000 -#define mmSEQ8_DATA_DEFAULT 0x00000000 -#define mmDAC_MASK_DEFAULT 0x00000000 -#define mmDAC_R_INDEX_DEFAULT 0x00000000 -#define mmDAC_W_INDEX_DEFAULT 0x00000000 -#define mmDAC_DATA_DEFAULT 0x00000000 -#define mmGENFC_RD_DEFAULT 0x00000000 -#define mmGENMO_RD_DEFAULT 0x00000000 -#define mmGRPH8_IDX_DEFAULT 0x00000000 -#define mmGRPH8_DATA_DEFAULT 0x00000000 -#define mmCRTC8_IDX_1_DEFAULT 0x00000000 -#define mmCRTC8_DATA_1_DEFAULT 0x00000000 -#define mmGENFC_WT_1_DEFAULT 0x00000000 -#define mmGENS1_1_DEFAULT 0x00000000 -#define mmD3VGA_CONTROL_DEFAULT 0x00000000 -#define mmD4VGA_CONTROL_DEFAULT 0x00000000 -#define mmD5VGA_CONTROL_DEFAULT 0x00000000 -#define mmD6VGA_CONTROL_DEFAULT 0x00000000 -#define mmVGA_SOURCE_SELECT_DEFAULT 0x00000100 -#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCFEV0_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCFEV1_CRTC_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmSYMCLKLPA_CLOCK_ENABLE_DEFAULT 0x00000000 -#define mmSYMCLKLPB_CLOCK_ENABLE_DEFAULT 0x00000100 -#define mmDPREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmREFCLK_CNTL_DEFAULT 0x00000000 -#define mmMIPI_CLK_CNTL_DEFAULT 0x00000000 -#define mmREFCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDSICLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CBUS_WRCMD_DELAY_DEFAULT 0x00000003 -#define mmDCCG_DS_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_DS_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_DS_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DS_HW_CAL_INTERVAL_DEFAULT 0x00989680 -#define mmSYMCLKG_CLOCK_ENABLE_DEFAULT 0x00000600 -#define mmDPREFCLK_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK0_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK1_CNTL_DEFAULT 0x00000000 -#define mmAOMCLK2_CNTL_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO2_MODULO_DEFAULT 0x00000001 -#define mmDCE_VERSION_DEFAULT 0x00000000 -#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_INCR_DEFAULT 0x00000000 -#define mmDCCG_GTC_DTO_MODULO_DEFAULT 0x00000000 -#define mmDCCG_GTC_CURRENT_DEFAULT 0x00000000 -#define mmDENTIST_DISPCLK_CNTL_DEFAULT 0x64010064 -#define mmMIPI_DTO_CNTL_DEFAULT 0x00000000 -#define mmMIPI_DTO_PHASE_DEFAULT 0x00000000 -#define mmMIPI_DTO_MODULO_DEFAULT 0x00000000 -#define mmDAC_CLK_ENABLE_DEFAULT 0x00000000 -#define mmDVO_CLK_ENABLE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_WRITE_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_CONTROL_DEFAULT 0x00000000 -#define mmDMCU_SMU_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmSMU_CONTROL_DEFAULT 0x00000000 -#define mmSMU_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmAVSYNC_COUNTER_READ_DEFAULT 0x00000000 -#define mmMILLISECOND_TIME_BASE_DIV_DEFAULT 0x001186a0 -#define mmDISPCLK_FREQ_CHANGE_CNTL_DEFAULT 0x08010028 -#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x00000001 -#define mmDCCG_PERFMON_CNTL_DEFAULT 0xfffff800 -#define mmDCCG_GATE_DISABLE_CNTL_DEFAULT 0x74ee00fd -#define mmDISPCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmSCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmDCCG_CAC_STATUS_DEFAULT 0x00000000 -#define mmPIXCLK1_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK2_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmPIXCLK0_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmMICROSECOND_TIME_BASE_DIV_DEFAULT 0x00120464 -#define mmDCCG_GATE_DISABLE_CNTL2_DEFAULT 0x037f037f -#define mmSYMCLK_CGTT_BLK_CTRL_REG_DEFAULT 0x00000200 -#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_DEFAULT 0x00000000 -#define mmDCCG_DISP_CNTL_REG_DEFAULT 0x00000000 -#define mmCRTC0_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO0_MODULO_DEFAULT 0x00000000 -#define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO1_MODULO_DEFAULT 0x00000000 -#define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO2_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO2_MODULO_DEFAULT 0x00000000 -#define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO3_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO3_MODULO_DEFAULT 0x00000000 -#define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO4_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO4_MODULO_DEFAULT 0x00000000 -#define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP_DTO5_PHASE_DEFAULT 0x00000000 -#define mmDP_DTO5_MODULO_DEFAULT 0x00000000 -#define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCCG_SOFT_RESET_DEFAULT 0x00000000 -#define mmSYMCLKA_CLOCK_ENABLE_DEFAULT 0x00000000 -#define mmSYMCLKB_CLOCK_ENABLE_DEFAULT 0x00000100 -#define mmSYMCLKC_CLOCK_ENABLE_DEFAULT 0x00000200 -#define mmSYMCLKD_CLOCK_ENABLE_DEFAULT 0x00000300 -#define mmSYMCLKE_CLOCK_ENABLE_DEFAULT 0x00000400 -#define mmSYMCLKF_CLOCK_ENABLE_DEFAULT 0x00000500 -#define mmDVOACLKD_CNTL_DEFAULT 0x00070000 -#define mmDVOACLKC_MVP_CNTL_DEFAULT 0x00030000 -#define mmDVOACLKC_CNTL_DEFAULT 0x00030000 -#define mmDCCG_AUDIO_DTO_SOURCE_DEFAULT 0x00000030 -#define mmDCCG_AUDIO_DTO0_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO0_MODULE_DEFAULT 0x00000001 -#define mmDCCG_AUDIO_DTO1_PHASE_DEFAULT 0x00000000 -#define mmDCCG_AUDIO_DTO1_MODULE_DEFAULT 0x00000001 -#define mmDCCG_TEST_CLK_SEL_DEFAULT 0x01ff01ff -#define mmFBC_CNTL_DEFAULT 0x00000500 -#define mmFBC_IDLE_FORCE_CLEAR_MASK_DEFAULT 0x00000000 -#define mmFBC_START_STOP_DELAY_DEFAULT 0x00000000 -#define mmFBC_COMP_CNTL_DEFAULT 0x0000000f -#define mmFBC_COMP_MODE_DEFAULT 0x00000000 -#define mmFBC_IND_LUT0_DEFAULT 0x00000000 -#define mmFBC_IND_LUT1_DEFAULT 0x00000000 -#define mmFBC_IND_LUT2_DEFAULT 0x00000000 -#define mmFBC_IND_LUT3_DEFAULT 0x00000000 -#define mmFBC_IND_LUT4_DEFAULT 0x00000000 -#define mmFBC_IND_LUT5_DEFAULT 0x00000000 -#define mmFBC_IND_LUT6_DEFAULT 0x00000000 -#define mmFBC_IND_LUT7_DEFAULT 0x00000000 -#define mmFBC_IND_LUT8_DEFAULT 0x00000000 -#define mmFBC_IND_LUT9_DEFAULT 0x00000000 -#define mmFBC_IND_LUT10_DEFAULT 0x00000000 -#define mmFBC_IND_LUT11_DEFAULT 0x00000000 -#define mmFBC_IND_LUT12_DEFAULT 0x00000000 -#define mmFBC_IND_LUT13_DEFAULT 0x00000000 -#define mmFBC_IND_LUT14_DEFAULT 0x00000000 -#define mmFBC_IND_LUT15_DEFAULT 0x00000000 -#define mmFBC_CSM_REGION_OFFSET_01_DEFAULT 0x00000000 -#define mmFBC_CSM_REGION_OFFSET_23_DEFAULT 0x00000000 -#define mmFBC_CLIENT_REGION_MASK_DEFAULT 0x00000000 -#define mmFBC_DEBUG_COMP_DEFAULT 0x00000000 -#define mmFBC_MISC_DEFAULT 0x0c306008 -#define mmFBC_STATUS_DEFAULT 0x00000000 -#define mmFBC_ALPHA_CNTL_DEFAULT 0x00000000 -#define mmFBC_ALPHA_RGB_OVERRIDE_DEFAULT 0x00000000 -#define mmPIPE0_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE0_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE0_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE1_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE1_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE1_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE2_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE2_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE2_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE3_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE3_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE3_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE4_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE4_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE4_PG_STATUS_DEFAULT 0x00000000 -#define mmPIPE5_PG_CONFIG_DEFAULT 0x00000001 -#define mmPIPE5_PG_ENABLE_DEFAULT 0x00000000 -#define mmPIPE5_PG_STATUS_DEFAULT 0x00000000 -#define mmDSI_PG_CONFIG_DEFAULT 0x00000001 -#define mmDSI_PG_ENABLE_DEFAULT 0x00000000 -#define mmDSI_PG_STATUS_DEFAULT 0x00000000 -#define mmDCFEV0_PG_CONFIG_DEFAULT 0x00000001 -#define mmDCFEV0_PG_ENABLE_DEFAULT 0x00000000 -#define mmDCFEV0_PG_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCPG_INTERRUPT_CONTROL2_DEFAULT 0x00000000 -#define mmDCFEV1_PG_CONFIG_DEFAULT 0x00000001 -#define mmDCFEV1_PG_ENABLE_DEFAULT 0x00000000 -#define mmDCFEV1_PG_STATUS_DEFAULT 0x00000000 -#define mmDC_IP_REQUEST_CNTL_DEFAULT 0x00000000 -#define mmDC_PGCNTL_STATUS_REG_DEFAULT 0x00000000 -#define mmDMIFV_STATUS_DEFAULT 0x00000000 -#define mmDMIF_CONTROL_DEFAULT 0x00000c04 -#define mmDMIF_STATUS_DEFAULT 0x0ff00000 -#define mmDMIF_ARBITRATION_CONTROL_DEFAULT 0x00042710 -#define mmPIPE0_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE1_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE2_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE3_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE4_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE5_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmDMIF_P_VMID_DEFAULT 0x00000000 -#define mmDMIF_ADDR_CALC_DEFAULT 0x00000000 -#define mmDMIF_STATUS2_DEFAULT 0x00000000 -#define mmPIPE0_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE1_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE2_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE3_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE4_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE5_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmLOW_POWER_TILING_CONTROL_DEFAULT 0x00001000 -#define mmMCIF_CONTROL_DEFAULT 0x00000000 -#define mmMCIF_WRITE_COMBINE_CONTROL_DEFAULT 0x00000080 -#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmCC_DC_PIPE_DIS_DEFAULT 0x00000000 -#define mmSMU_WM_CONTROL_DEFAULT 0x00000000 -#define mmRBBMIF_TIMEOUT_DEFAULT 0x20000a00 -#define mmRBBMIF_STATUS_DEFAULT 0x80000000 -#define mmRBBMIF_TIMEOUT_DIS_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_STATUS2_DEFAULT 0x00000000 -#define mmDCI_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCI_CLK_CNTL2_DEFAULT 0x00020020 -#define mmDCI_MEM_PWR_CNTL_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_CNTL2_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_CNTL3_DEFAULT 0x00000000 -#define mmPIPE0_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE1_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE2_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE3_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE4_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmPIPE5_DMIF_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmRBBMIF_STATUS_FLAG_DEFAULT 0x00000000 -#define mmDCI_SOFT_RESET_DEFAULT 0x00000000 -#define mmDMIF_URG_OVERRIDE_DEFAULT 0x00000000 -#define mmPIPE6_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE7_ARBITRATION_CONTROL3_DEFAULT 0x00000000 -#define mmPIPE6_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmPIPE7_MAX_REQUESTS_DEFAULT 0x000003ff -#define mmDVMM_REG_RD_STATUS_DEFAULT 0x00000000 -#define mmDVMM_REG_RD_DATA_DEFAULT 0x00000000 -#define mmDVMM_PTE_REQ_DEFAULT 0x000120ff -#define mmDVMM_CNTL_DEFAULT 0x00000000 -#define mmDVMM_FAULT_STATUS_DEFAULT 0x00000000 -#define mmDVMM_FAULT_ADDR_DEFAULT 0x00000000 -#define mmFMON_CTRL_DEFAULT 0x0000f040 -#define mmDVMM_PTE_PGMEM_CONTROL_DEFAULT 0x00000000 -#define mmDVMM_PTE_PGMEM_STATE_DEFAULT 0x00000000 -#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_WB_PHASE0_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmMCIF_WB_PHASE1_OUTSTANDING_COUNTER_DEFAULT 0x00000000 -#define mmDCI_MEM_PWR_CNTL4_DEFAULT 0x0000003f -#define mmMCIF_WB_MISC_CTRL_DEFAULT 0x00010001 -#define mmDCI_MEM_PWR_STATUS3_DEFAULT 0x00000000 -#define mmDMIF_CURSOR_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_CURSOR_MEM_CONTROL_DEFAULT 0x00000000 -#define mmDCHUB_FB_LOCATION_DEFAULT 0x00000000 -#define mmDCHUB_FB_OFFSET_DEFAULT 0x00000000 -#define mmDCHUB_AGP_BASE_DEFAULT 0x00000000 -#define mmDCHUB_AGP_BOT_DEFAULT 0x00000000 -#define mmDCHUB_AGP_TOP_DEFAULT 0x00000000 -#define mmDCHUB_DRAM_APER_BASE_DEFAULT 0x00000000 -#define mmDCHUB_DRAM_APER_DEF_DEFAULT 0x00000000 -#define mmDCHUB_DRAM_APER_TOP_DEFAULT 0x00000000 -#define mmDCHUB_CONTROL_STATUS_DEFAULT 0x00c00000 -#define mmWB_ENABLE_DEFAULT 0x00000000 -#define mmWB_EC_CONFIG_DEFAULT 0x55000000 -#define mmCNV_MODE_DEFAULT 0x00000000 -#define mmCNV_WINDOW_START_DEFAULT 0x00000000 -#define mmCNV_WINDOW_SIZE_DEFAULT 0x00100010 -#define mmCNV_UPDATE_DEFAULT 0x00000000 -#define mmCNV_SOURCE_SIZE_DEFAULT 0x00100010 -#define mmCNV_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCNV_CSC_C11_C12_DEFAULT 0x00000000 -#define mmCNV_CSC_C13_C14_DEFAULT 0x00000000 -#define mmCNV_CSC_C21_C22_DEFAULT 0x00000000 -#define mmCNV_CSC_C23_C24_DEFAULT 0x00000000 -#define mmCNV_CSC_C31_C32_DEFAULT 0x00000000 -#define mmCNV_CSC_C33_C34_DEFAULT 0x00000000 -#define mmCNV_CSC_ROUND_OFFSET_R_DEFAULT 0x00000000 -#define mmCNV_CSC_ROUND_OFFSET_G_DEFAULT 0x00000000 -#define mmCNV_CSC_ROUND_OFFSET_B_DEFAULT 0x00000000 -#define mmCNV_CSC_CLAMP_R_DEFAULT 0x00000fff -#define mmCNV_CSC_CLAMP_G_DEFAULT 0x00000fff -#define mmCNV_CSC_CLAMP_B_DEFAULT 0x00000fff -#define mmCNV_TEST_CNTL_DEFAULT 0x00000000 -#define mmCNV_TEST_CRC_RED_DEFAULT 0x0000fff0 -#define mmCNV_TEST_CRC_GREEN_DEFAULT 0x0000fff0 -#define mmCNV_TEST_CRC_BLUE_DEFAULT 0x0000fff0 -#define mmCNV_INPUT_SELECT_DEFAULT 0x00000000 -#define mmWB_SOFT_RESET_DEFAULT 0x00000000 -#define mmWB_WARM_UP_MODE_CTL1_DEFAULT 0x88700100 -#define mmWB_WARM_UP_MODE_CTL2_DEFAULT 0x00000100 -#define mmWBSCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmWBSCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmWBSCL_MODE_DEFAULT 0x00000000 -#define mmWBSCL_TAP_CONTROL_DEFAULT 0x00001111 -#define mmWBSCL_DEST_SIZE_DEFAULT 0x00010001 -#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL_HORZ_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00080000 -#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_DEFAULT 0x01000000 -#define mmWBSCL_VERT_FILTER_INIT_CBCR_DEFAULT 0x01000000 -#define mmWBSCL_ROUND_OFFSET_DEFAULT 0x00800010 -#define mmWBSCL_CLAMP_DEFAULT 0x01fe01fe -#define mmWBSCL_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmWBSCL_OUTSIDE_PIX_STRATEGY_DEFAULT 0x80108000 -#define mmWBSCL_TEST_CNTL_DEFAULT 0x00000000 -#define mmWBSCL_TEST_CRC_RED_DEFAULT 0x0000ff00 -#define mmWBSCL_TEST_CRC_GREEN_DEFAULT 0x0000ffff -#define mmWBSCL_TEST_CRC_BLUE_DEFAULT 0x0000ff00 -#define mmWBSCL_BACKPRESSURE_CNT_EN_DEFAULT 0x00000000 -#define mmWB_MCIF_BACKPRESSURE_CNT_DEFAULT 0x00000000 -#define mmWBSCL_RAM_SHUTDOWN_DEFAULT 0x00000000 -#define mmDMCU_CTRL_DEFAULT 0xffff0101 -#define mmDMCU_STATUS_DEFAULT 0x00000001 -#define mmDMCU_PC_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_START_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_END_ADDR_DEFAULT 0x00000000 -#define mmDMCU_FW_ISR_START_ADDR_DEFAULT 0x00000004 -#define mmDMCU_FW_CS_HI_DEFAULT 0x00000000 -#define mmDMCU_FW_CS_LO_DEFAULT 0x00000000 -#define mmDMCU_RAM_ACCESS_CTRL_DEFAULT 0x00000000 -#define mmDMCU_ERAM_WR_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_ERAM_RD_CTRL_DEFAULT 0x000f0000 -#define mmDMCU_ERAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_WR_DATA_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_CTRL_DEFAULT 0x00000000 -#define mmDMCU_IRAM_RD_DATA_DEFAULT 0x00000000 -#define mmDMCU_EVENT_TRIGGER_DEFAULT 0x00000000 -#define mmDMCU_UC_INTERNAL_INT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_DEFAULT 0x00000000 -#define mmDC_DMCU_SCRATCH_DEFAULT 0x00000000 -#define mmDMCU_INT_CNT_DEFAULT 0x00000000 -#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_DEFAULT 0x00000000 -#define mmDMCU_UC_CLK_GATING_CNTL_DEFAULT 0x00010102 -#define mmMASTER_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmMASTER_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmMASTER_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmMASTER_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG1_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG2_DEFAULT 0x00000000 -#define mmSLAVE_COMM_DATA_REG3_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CMD_REG_DEFAULT 0x00000000 -#define mmSLAVE_COMM_CNTL_REG_DEFAULT 0x00000000 -#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_USER_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_TARGET_ABM_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_CURRENT_ABM_LEVEL_DEFAULT 0x00000000 -#define mmBL1_PWM_FINAL_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_DEFAULT 0x00000000 -#define mmBL1_PWM_ABM_CNTL_DEFAULT 0x00000000 -#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmBL1_PWM_GRP2_REG_LOCK_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_DEFAULT 0x00000000 -#define mmDMCU_INTERRUPT_STATUS_1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDC_ABM1_CNTL_DEFAULT 0x00000000 -#define mmDC_ABM1_IPCSC_COEFF_SEL_DEFAULT 0x00000000 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_DEFAULT 0x00000400 -#define mmDC_ABM1_ACE_THRES_12_DEFAULT 0x00000000 -#define mmDC_ABM1_ACE_THRES_34_DEFAULT 0x00000000 -#define mmDC_ABM1_ACE_CNTL_MISC_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_STATUS4_DEFAULT 0x00000000 -#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_MISC_CTRL_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_SUM_OF_LUMA_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_PIXEL_COUNT_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_OVR_SCAN_BIN_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmDC_ABM1_LS_SAMPLE_RATE_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_1_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_2_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_3_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_4_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_5_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_6_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_7_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_8_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_9_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_10_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_11_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_12_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_13_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_14_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_15_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_16_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_17_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_18_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_19_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_20_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_21_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_22_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_23_DEFAULT 0x00000000 -#define mmDC_ABM1_HG_RESULT_24_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_DEFAULT 0x00000000 -#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_DEFAULT 0x00000000 -#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE_DEFAULT 0x00000000 -#define mmDC_ABM1_BL_MASTER_LOCK_DEFAULT 0x00000000 -#define mmAZALIA_CONTROLLER_CLOCK_GATING_DEFAULT 0x00000000 -#define mmAZALIA_AUDIO_DTO_DEFAULT 0x001b0018 -#define mmAZALIA_AUDIO_DTO_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_SOCCLK_CONTROL_DEFAULT 0x00000001 -#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_DEFAULT 0x00000000 -#define mmAZALIA_DATA_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_BDL_DMA_CONTROL_DEFAULT 0x0000000a -#define mmAZALIA_RIRB_AND_DP_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_CORB_DMA_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_DEFAULT 0x00000000 -#define mmAZALIA_CYCLIC_BUFFER_SYNC_DEFAULT 0x00000000 -#define mmAZALIA_GLOBAL_CAPABILITIES_DEFAULT 0x00000000 -#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000060 -#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_DEFAULT 0x00080008 -#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_DEFAULT 0x00000080 -#define mmAZALIA_INPUT_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_INPUT_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC0_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL0_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL1_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL2_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_CONTROL3_DEFAULT 0x00000000 -#define mmAZALIA_CRC1_RESULT_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmAZALIA_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x1002aa01 -#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00100700 -#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_DEFAULT 0x0000000d -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0xc0000009 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000200 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00aa0100 -#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET0_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET1_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET2_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET3_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET4_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET5_DEFAULT 0x00000000 -#define mmAZALIA_F0_GTC_GROUP_OFFSET6_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_DEFAULT 0x00000000 -#define mmDAC_ENABLE_DEFAULT 0x00000004 -#define mmDAC_SOURCE_SELECT_DEFAULT 0x00000000 -#define mmDAC_CRC_EN_DEFAULT 0x00000000 -#define mmDAC_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_CRC_SIG_RGB_MASK_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_MASK_DEFAULT 0x0000003f -#define mmDAC_CRC_SIG_RGB_DEFAULT 0x3fffffff -#define mmDAC_CRC_SIG_CONTROL_DEFAULT 0x0000003f -#define mmDAC_SYNC_TRISTATE_CONTROL_DEFAULT 0x00000000 -#define mmDAC_STEREOSYNC_SELECT_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_CONTROL_DEFAULT 0x00070000 -#define mmDAC_AUTODETECT_CONTROL2_DEFAULT 0x0000000b -#define mmDAC_AUTODETECT_CONTROL3_DEFAULT 0x00000519 -#define mmDAC_AUTODETECT_STATUS_DEFAULT 0x00000000 -#define mmDAC_AUTODETECT_INT_CONTROL_DEFAULT 0x00000000 -#define mmDAC_FORCE_OUTPUT_CNTL_DEFAULT 0x00000000 -#define mmDAC_FORCE_DATA_DEFAULT 0x000001e6 -#define mmDAC_POWERDOWN_DEFAULT 0x01010100 -#define mmDAC_CONTROL_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_ENABLE_DEFAULT 0x00000000 -#define mmDAC_COMPARATOR_OUTPUT_DEFAULT 0x00000000 -#define mmDAC_PWR_CNTL_DEFAULT 0x00000000 -#define mmDAC_DFT_CONFIG_DEFAULT 0x00000000 -#define mmDAC_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_ARBITRATION_DEFAULT 0x00000001 -#define mmDC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDC_I2C_SW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDC1_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC1_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC2_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC2_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC3_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC3_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC4_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC4_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC5_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC5_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_DDC6_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDC6_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION0_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION1_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION2_DEFAULT 0x00000000 -#define mmDC_I2C_TRANSACTION3_DEFAULT 0x00000000 -#define mmDC_I2C_DATA_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_HW_STATUS_DEFAULT 0x00000000 -#define mmDC_I2C_DDCVGA_SPEED_DEFAULT 0x00000002 -#define mmDC_I2C_DDCVGA_SETUP_DEFAULT 0x00000000 -#define mmDC_I2C_EDID_DETECT_CTRL_DEFAULT 0x004001f4 -#define mmDC_I2C_READ_REQUEST_INTERRUPT_DEFAULT 0x40000000 -#define mmGENERIC_I2C_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmGENERIC_I2C_STATUS_DEFAULT 0x00000000 -#define mmGENERIC_I2C_SPEED_DEFAULT 0x00000002 -#define mmGENERIC_I2C_SETUP_DEFAULT 0x00000000 -#define mmGENERIC_I2C_TRANSACTION_DEFAULT 0x00000000 -#define mmGENERIC_I2C_DATA_DEFAULT 0x00000000 -#define mmGENERIC_I2C_PIN_SELECTION_DEFAULT 0x00000000 -#define mmDCO_SCRATCH0_DEFAULT 0x00000000 -#define mmDCO_SCRATCH1_DEFAULT 0x00000000 -#define mmDCO_SCRATCH2_DEFAULT 0x00000000 -#define mmDCO_SCRATCH3_DEFAULT 0x00000000 -#define mmDCO_SCRATCH4_DEFAULT 0x00000000 -#define mmDCO_SCRATCH5_DEFAULT 0x00000000 -#define mmDCO_SCRATCH6_DEFAULT 0x00000000 -#define mmDCO_SCRATCH7_DEFAULT 0x00000000 -#define mmDCE_VCE_CONTROL_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE2_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE3_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE4_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE5_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE6_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE7_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE8_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE9_DEFAULT 0x00000000 -#define mmDCO_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCO_MEM_PWR_CTRL_DEFAULT 0x6db6d800 -#define mmDCO_MEM_PWR_CTRL2_DEFAULT 0x001b0000 -#define mmDCO_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCO_POWER_MANAGEMENT_CNTL_DEFAULT 0x00000000 -#define mmDIG_SOFT_RESET_2_DEFAULT 0x00000000 -#define mmDCO_STEREOSYNC_SEL_DEFAULT 0x00000000 -#define mmDCO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDIG_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCO_MEM_PWR_STATUS1_DEFAULT 0x00000000 -#define mmDISP_INTERRUPT_STATUS_CONTINUE10_DEFAULT 0x00000000 -#define mmDCO_CLK_CNTL2_DEFAULT 0x00000000 -#define mmDCO_CLK_CNTL3_DEFAULT 0x00000000 -#define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL_DEFAULT 0x00000000 -#define mmDCO_PSP_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCO_PSP_INTERRUPT_CLEAR_DEFAULT 0x00000000 -#define mmDCO_GENERIC_INTERRUPT_MESSAGE_DEFAULT 0x00000000 -#define mmDCO_GENERIC_INTERRUPT_CLEAR_DEFAULT 0x00000000 -#define mmFMT_MEMORY0_CONTROL_DEFAULT 0x00000030 -#define mmFMT_MEMORY1_CONTROL_DEFAULT 0x00000031 -#define mmFMT_MEMORY2_CONTROL_DEFAULT 0x00000032 -#define mmFMT_MEMORY3_CONTROL_DEFAULT 0x00000033 -#define mmFMT_MEMORY4_CONTROL_DEFAULT 0x00000034 -#define mmFMT_MEMORY5_CONTROL_DEFAULT 0x00000035 -#define mmDISP_INTERRUPT_STATUS_CONTINUE11_DEFAULT 0x00000000 -#define mmDC_GENERICA_DEFAULT 0x00000000 -#define mmDC_GENERICB_DEFAULT 0x00000000 -#define mmDC_PAD_EXTERN_SIG_DEFAULT 0x00000000 -#define mmDC_REF_CLK_CNTL_DEFAULT 0x00000000 -#define mmDC_GPIO_DEBUG_DEFAULT 0x00000101 -#define mmUNIPHYA_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYB_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYC_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYC_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYD_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYD_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYE_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYE_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYF_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYF_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYG_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYG_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmDCIO_WRCMD_DELAY_DEFAULT 0x00033333 -#define mmDC_DVODATA_CONFIG_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_CNTL_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_STATE_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_REF_DIV_DEFAULT 0x00010000 -#define mmLVTMA_PWRSEQ_DELAY1_DEFAULT 0x00000000 -#define mmLVTMA_PWRSEQ_DELAY2_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL_DEFAULT 0x00000000 -#define mmBL_PWM_CNTL2_DEFAULT 0x00000000 -#define mmBL_PWM_PERIOD_CNTL_DEFAULT 0x00000001 -#define mmBL_PWM_GRP1_REG_LOCK_DEFAULT 0x00000000 -#define mmDCIO_GSL_GENLK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL0_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL1_CNTL_DEFAULT 0x00000000 -#define mmDCIO_GSL2_CNTL_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_START_POSITION_P_FLIP_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_DEFAULT 0x00000000 -#define mmDC_GPU_TIMER_READ_CNTL_DEFAULT 0x00000000 -#define mmDCIO_CLOCK_CNTL_DEFAULT 0x00000000 -#define mmDCO_DCFE_EXT_VSYNC_CNTL_DEFAULT 0x00000000 -#define mmDCIO_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCIO_DPHY_SEL_DEFAULT 0x000000e4 -#define mmUNIPHY_IMPCAL_LINKA_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKB_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_PERIOD_DEFAULT 0x00000000 -#define mmAUXP_IMPCAL_DEFAULT 0x0a000000 -#define mmAUXN_IMPCAL_DEFAULT 0x04000000 -#define mmDCIO_IMPCAL_CNTL_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_AB_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKC_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKD_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_CD_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_LINKE_DEFAULT 0x0f000000 -#define mmUNIPHY_IMPCAL_LINKF_DEFAULT 0x0f000000 -#define mmDCIO_IMPCAL_CNTL_EF_DEFAULT 0x00000000 -#define mmUNIPHY_IMPCAL_PSW_EF_DEFAULT 0x00000000 -#define mmUNIPHYLPA_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYLPB_LINK_CNTL_DEFAULT 0x01100100 -#define mmUNIPHYLPA_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmUNIPHYLPB_CHANNEL_XBAR_CNTL_DEFAULT 0x03020100 -#define mmDCIO_DPCS_TX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_DPCS_RX_INTERRUPT_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE0_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE1_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE2_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE3_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE4_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE5_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE6_DEFAULT 0x00000000 -#define mmDCIO_SEMAPHORE7_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_MASK_DEFAULT 0x04444444 -#define mmDC_GPIO_GENERIC_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENERIC_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DVODATA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC1_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC1_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC2_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC2_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC3_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC3_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC4_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC4_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC5_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC5_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDC6_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDC6_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_MASK_DEFAULT 0xcf400000 -#define mmDC_GPIO_DDCVGA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_DDCVGA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_MASK_DEFAULT 0x00004040 -#define mmDC_GPIO_SYNCA_A_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_SYNCA_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_MASK_DEFAULT 0x10101a10 -#define mmDC_GPIO_GENLK_A_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_GENLK_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_MASK_DEFAULT 0x44440440 -#define mmDC_GPIO_HPD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_HPD_EN_DEFAULT 0x22220202 -#define mmDC_GPIO_HPD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_MASK_DEFAULT 0x66404040 -#define mmDC_GPIO_PWRSEQ_A_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_PWRSEQ_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_PAD_STRENGTH_1_DEFAULT 0x47ac470f -#define mmDC_GPIO_PAD_STRENGTH_2_DEFAULT 0x00472147 -#define mmPHY_AUX_CNTL_DEFAULT 0x00010001 -#define mmDC_GPIO_I2CPAD_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2CPAD_STRENGTH_DEFAULT 0x0000004c -#define mmDVO_STRENGTH_CONTROL_DEFAULT 0x31116060 -#define mmDVO_VREF_CONTROL_DEFAULT 0x00000000 -#define mmDVO_SKEW_ADJUST_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_MASK_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_A_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_EN_DEFAULT 0x00008000 -#define mmDC_GPIO_I2S_SPDIF_Y_DEFAULT 0x00000000 -#define mmDC_GPIO_I2S_SPDIF_STRENGTH_DEFAULT 0x01021202 -#define mmDC_GPIO_TX12_EN_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_0_DEFAULT 0x00000000 -#define mmDC_GPIO_AUX_CTRL_1_DEFAULT 0x00500000 -#define mmDC_GPIO_AUX_CTRL_2_DEFAULT 0x00000000 -#define mmDC_GPIO_RXEN_DEFAULT 0x007fff7f -#define mmBPHYC_DAC_MACRO_CNTL_DEFAULT 0x00202002 -#define mmDAC_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmBPHYC_DAC_AUTO_CALIB_CONTROL_DEFAULT 0x00700255 -#define mmDAC_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDAC_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDISP_DSI_DUAL_CTRL_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDPRX_AUX_REFERENCE_PULSE_DIV_DEFAULT 0x0a640064 -#define mmDPRX_AUX_CONTROL_DEFAULT 0x01012c00 -#define mmDPRX_AUX_HPD_CONTROL1_DEFAULT 0x00001407 -#define mmDPRX_AUX_HPD_CONTROL2_DEFAULT 0x00000000 -#define mmDPRX_AUX_RX_STATUS_DEFAULT 0x00000000 -#define mmDPRX_AUX_RX_ERROR_MASK_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDPRX_AUX_DPHY_TX_CONTROL_DEFAULT 0x00001002 -#define mmDPRX_AUX_DPHY_RX_CONTROL0_DEFAULT 0x203d1210 -#define mmDPRX_AUX_DPHY_RX_CONTROL1_DEFAULT 0x0a00fa00 -#define mmDPRX_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDPRX_AUX_DMCU_HW_INT_STATUS_DEFAULT 0x00003f00 -#define mmDPRX_AUX_DMCU_HW_INT_ACK_DEFAULT 0x00000000 -#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT1_DEFAULT 0x00000000 -#define mmDPRX_AUX_CPU_TO_DMCU_INTERRUPT2_DEFAULT 0x00000001 -#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT1_DEFAULT 0x00000000 -#define mmDPRX_AUX_DMCU_TO_CPU_INTERRUPT2_DEFAULT 0x00000000 -#define mmDPRX_AUX_AUX_BUF_INDEX_DEFAULT 0x00000000 -#define mmDPRX_AUX_AUX_BUF_DATA_DEFAULT 0x00000000 -#define mmDPRX_AUX_EDID_INDEX_DEFAULT 0x00000000 -#define mmDPRX_AUX_EDID_DATA_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_INDEX1_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_DATA1_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_INDEX2_DEFAULT 0x00000000 -#define mmDPRX_AUX_DPCD_DATA2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_INDEX1_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_DATA1_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_INDEX2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_DATA2_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_INDEX1_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_DATA1_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_INDEX2_DEFAULT 0x00000000 -#define mmDPRX_AUX_KSV_DATA2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_TIMEOUT_CONTROL_DEFAULT 0x00000032 -#define mmDPRX_AUX_MSG_BUF_CONTROL1_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG_BUF_CONTROL2_DEFAULT 0x00000000 -#define mmDPRX_AUX_SCRATCH1_DEFAULT 0x00000000 -#define mmDPRX_AUX_SCRATCH2_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG1_PENDING_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG2_PENDING_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG3_PENDING_DEFAULT 0x00000000 -#define mmDPRX_AUX_MSG4_PENDING_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LANE_COUNT_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_TRAINING_PATTERN_SET_DEFAULT 0x00000003 -#define mmDPRX_DPHY_DPCD_MSTM_CTRL_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE0_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE1_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE2_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_SET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DPCD_LINK_QUAL_LANE3_STATUS_DEFAULT 0x20000000 -#define mmDPRX_DPHY_READY_DEFAULT 0x00000000 -#define mmDPRX_DPHY_COMMA_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANE_ALIGN_ERROR_STATUS_UPDATED_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANE_ALIGN_STATUS_UPDATED_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE2_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_THRESH_A_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_A_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_B_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ERROR_COUNT_C_LANE3_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_ERROR_THRESH_GLOBAL_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SR_ERROR_COUNT_A_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_ERROR_COUNT_A_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_ERROR_COUNT_B_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANESETUP0_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LANESETUP1_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LFSRADV_DEFAULT 0x00000039 -#define mmDPRX_DPHY_SEVENSYMBOLWINDOW_ERROR_DETECT_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SET_ENABLE_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ECF_LSB_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ECF_MSB_DEFAULT 0x00000000 -#define mmDPRX_DPHY_ENHANCED_FRAME_EN_DEFAULT 0x00000001 -#define mmDPRX_DPHY_MTP_HEADER_COUNT_FORCE_DEFAULT 0x000a6800 -#define mmDPRX_DPHY_DYNAMIC_DESKEW_DATA_DEFAULT 0xbcbcbcbc -#define mmDPRX_DPHY_DYNAMIC_DESKEW_CONTROL_DEFAULT 0x800071c5 -#define mmDPRX_DPHY_BYPASS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_INT_RESET_DEFAULT 0x00000000 -#define mmDPRX_DPHY_BS_INTERVAL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SYMBOL_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DISPARITY_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_TEST_PATTERN_ERROR_THRESH_EXCEEDED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DETECT_SR_LOCK_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LOSS_OF_ALIGN_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_LOSS_OF_DESKEW_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_EXCESSIVE_ERROR_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_DESKEW_FIFO_OVERFLOW_STATUS_DEFAULT 0x00000000 -#define mmDPRX_DPHY_SPARE_DEFAULT 0x00000000 -#define mmDCRX_GATE_DISABLE_CNTL_DEFAULT 0x00001f0f -#define mmDCRX_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCRX_LIGHT_SLEEP_CNTL_DEFAULT 0x00000101 -#define mmDCRX_DISPCLK_GATE_CNTL_DEFAULT 0x00000200 -#define mmDCRX_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCRX_TEST_CLK_CNTL_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED160_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED161_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED162_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED163_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED164_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED165_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED166_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED167_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED168_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED169_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED170_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED171_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED172_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED173_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED174_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED175_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED176_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED177_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED178_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED179_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED180_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED181_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED182_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED183_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED184_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED185_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED186_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED187_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED188_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED189_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED190_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED191_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED192_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED193_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED194_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED195_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED196_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED197_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED198_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED199_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED200_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED201_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED202_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED203_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED204_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED205_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED206_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED207_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED208_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED209_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED210_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED211_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED212_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED213_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED214_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED215_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED216_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED217_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED218_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED219_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED220_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED221_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED222_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED223_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED224_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED225_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED226_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED227_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED228_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED229_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED230_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED231_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED232_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED233_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED234_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED235_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED236_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED237_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED238_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED239_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED240_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED241_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED242_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED243_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED244_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED245_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED246_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED247_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED248_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED249_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED250_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED251_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED252_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED253_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED254_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED255_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED256_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED257_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED258_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED259_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED260_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED261_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED262_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED263_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED264_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED265_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED266_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED267_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED268_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED269_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED270_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED271_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED272_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED273_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED274_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED275_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED276_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED277_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED278_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED279_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED280_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED281_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED282_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED283_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED284_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED285_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED286_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED287_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED288_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED289_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED290_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED291_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED292_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED293_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED294_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED295_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED296_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED297_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED298_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED299_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED300_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED301_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED302_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED303_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED304_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED305_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED306_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED307_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED308_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED309_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED310_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED311_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED312_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED313_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED314_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED315_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED316_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED317_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED318_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED319_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED320_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED321_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED322_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED323_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED324_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED325_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED326_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED327_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED328_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED329_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED330_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED331_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED332_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED333_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED334_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED335_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED336_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED337_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED338_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED339_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED340_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED341_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED342_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED343_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED344_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED345_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED346_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED347_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED348_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED349_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED350_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED351_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED352_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED353_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED354_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED355_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED356_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED357_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED358_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED359_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED360_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED361_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED362_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED363_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED364_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED365_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED366_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED367_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED368_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED369_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED370_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED371_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED372_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED373_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED374_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED375_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED376_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED377_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED378_DEFAULT 0x00000000 -#define mmDCRX_PHY_MACRO_CNTL_RESERVED379_DEFAULT 0x00000000 -#define mmI2S0_CNTL_DEFAULT 0x00010000 -#define mmSPDIF0_CNTL_DEFAULT 0x00000000 -#define mmI2S1_CNTL_DEFAULT 0x00010000 -#define mmSPDIF1_CNTL_DEFAULT 0x00000000 -#define mmI2S0_STATUS_DEFAULT 0x00000000 -#define mmI2S1_STATUS_DEFAULT 0x00000000 -#define mmI2S0_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmI2S0_CRC_TEST_DATA_01_DEFAULT 0x00000000 -#define mmI2S0_CRC_TEST_DATA_23_DEFAULT 0x00000000 -#define mmI2S1_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmI2S1_CRC_TEST_DATA_0_DEFAULT 0x00000000 -#define mmSPDIF0_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmSPDIF0_CRC_TEST_DATA_0_DEFAULT 0x00000000 -#define mmSPDIF1_CRC_TEST_CNTL_DEFAULT 0x00000100 -#define mmSPDIF1_CRC_TEST_DATA_DEFAULT 0x00000000 -#define mmCRC_I2S_CONT_REPEAT_NUM_DEFAULT 0x00000000 -#define mmCRC_SPDIF_CONT_REPEAT_NUM_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmZCAL_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream0_dispdec -#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM0_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream1_dispdec -#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM1_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream2_dispdec -#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM2_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream3_dispdec -#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM3_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream4_dispdec -#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM4_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream5_dispdec -#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM5_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream6_dispdec -#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM6_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream7_dispdec -#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM7_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint0_dispdec -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint1_dispdec -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint2_dispdec -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint3_dispdec -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint4_dispdec -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint5_dispdec -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint6_dispdec -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0endpoint7_dispdec -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream8_dispdec -#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM8_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream9_dispdec -#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM9_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream10_dispdec -#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM10_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream11_dispdec -#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM11_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream12_dispdec -#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM12_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream13_dispdec -#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM13_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream14_dispdec -#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM14_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0stream15_dispdec -#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_DEFAULT 0x00000000 -#define mmAZF0STREAM15_AZALIA_STREAM_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint0_dispdec -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint1_dispdec -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint2_dispdec -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint3_dispdec -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint4_dispdec -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint5_dispdec -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint6_dispdec -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azf0inputendpoint7_dispdec -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_DEFAULT 0x00000000 -#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp0_dispdec -#define mmDCP0_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP0_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP0_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP0_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP0_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP0_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP0_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP0_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP0_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP0_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP0_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP0_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP0_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP0_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP0_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP0_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP0_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP0_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP0_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP0_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP0_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP0_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP0_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP0_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP0_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP0_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP0_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP0_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP0_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP0_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP0_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP0_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP0_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP0_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP0_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP0_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP0_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP0_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP0_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP0_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP0_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP0_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP0_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP0_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP0_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP0_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP0_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP0_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP0_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP0_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP0_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP0_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP0_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb0_dispdec -#define mmLB0_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB0_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB0_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB0_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB0_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB0_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB0_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB0_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB0_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB0_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB0_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB0_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB0_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB0_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB0_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB0_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB0_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB0_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe0_dispdec -#define mmDCFE0_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE0_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE0_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon3_dispdec -#define mmDC_PERFMON3_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON3_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON3_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg0_dispdec -#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG0_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl0_dispdec -#define mmSCL0_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL0_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL0_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL0_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL0_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL0_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL0_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL0_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL0_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL0_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL0_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL0_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL0_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL0_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd0_dispdec -#define mmBLND0_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND0_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND0_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND0_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND0_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND0_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND0_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc0_dispdec -#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC0_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC0_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC0_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC0_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC0_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC0_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC0_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC0_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC0_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC0_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt0_dispdec -#define mmFMT0_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT0_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT0_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT0_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT0_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT0_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT0_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT0_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT0_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp1_dispdec -#define mmDCP1_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP1_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP1_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP1_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP1_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP1_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP1_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP1_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP1_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP1_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP1_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP1_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP1_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP1_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP1_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP1_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP1_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP1_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP1_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP1_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP1_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP1_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP1_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP1_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP1_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP1_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP1_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP1_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP1_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP1_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP1_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP1_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP1_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP1_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP1_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP1_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP1_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP1_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP1_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP1_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP1_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP1_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP1_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP1_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP1_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP1_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP1_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP1_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP1_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP1_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP1_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP1_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP1_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb1_dispdec -#define mmLB1_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB1_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB1_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB1_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB1_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB1_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB1_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB1_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB1_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB1_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB1_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB1_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB1_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB1_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB1_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB1_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB1_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB1_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe1_dispdec -#define mmDCFE1_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE1_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE1_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon4_dispdec -#define mmDC_PERFMON4_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON4_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON4_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg1_dispdec -#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG1_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl1_dispdec -#define mmSCL1_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL1_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL1_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL1_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL1_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL1_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL1_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL1_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL1_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL1_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL1_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL1_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL1_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL1_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd1_dispdec -#define mmBLND1_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND1_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND1_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND1_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND1_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND1_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND1_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc1_dispdec -#define mmCRTC1_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC1_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC1_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC1_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC1_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC1_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC1_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC1_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC1_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC1_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC1_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt1_dispdec -#define mmFMT1_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT1_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT1_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT1_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT1_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT1_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT1_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT1_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT1_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp2_dispdec -#define mmDCP2_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP2_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP2_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP2_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP2_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP2_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP2_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP2_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP2_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP2_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP2_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP2_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP2_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP2_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP2_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP2_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP2_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP2_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP2_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP2_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP2_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP2_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP2_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP2_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP2_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP2_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP2_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP2_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP2_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP2_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP2_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP2_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP2_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP2_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP2_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP2_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP2_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP2_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP2_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP2_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP2_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP2_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP2_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP2_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP2_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP2_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP2_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP2_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP2_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP2_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP2_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP2_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP2_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb2_dispdec -#define mmLB2_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB2_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB2_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB2_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB2_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB2_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB2_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB2_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB2_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB2_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB2_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB2_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB2_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB2_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB2_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB2_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB2_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB2_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe2_dispdec -#define mmDCFE2_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE2_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE2_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon5_dispdec -#define mmDC_PERFMON5_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON5_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON5_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg2_dispdec -#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG2_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl2_dispdec -#define mmSCL2_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL2_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL2_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL2_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL2_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL2_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL2_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL2_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL2_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL2_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL2_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL2_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL2_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL2_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd2_dispdec -#define mmBLND2_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND2_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND2_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND2_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND2_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND2_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND2_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc2_dispdec -#define mmCRTC2_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC2_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC2_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC2_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC2_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC2_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC2_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC2_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC2_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC2_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC2_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt2_dispdec -#define mmFMT2_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT2_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT2_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT2_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT2_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT2_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT2_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT2_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT2_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp3_dispdec -#define mmDCP3_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP3_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP3_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP3_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP3_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP3_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP3_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP3_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP3_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP3_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP3_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP3_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP3_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP3_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP3_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP3_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP3_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP3_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP3_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP3_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP3_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP3_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP3_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP3_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP3_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP3_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP3_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP3_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP3_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP3_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP3_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP3_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP3_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP3_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP3_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP3_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP3_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP3_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP3_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP3_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP3_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP3_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP3_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP3_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP3_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP3_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP3_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP3_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP3_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP3_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP3_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP3_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP3_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb3_dispdec -#define mmLB3_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB3_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB3_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB3_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB3_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB3_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB3_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB3_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB3_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB3_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB3_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB3_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB3_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB3_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB3_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB3_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB3_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB3_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe3_dispdec -#define mmDCFE3_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE3_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE3_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon6_dispdec -#define mmDC_PERFMON6_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON6_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON6_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg3_dispdec -#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG3_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl3_dispdec -#define mmSCL3_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL3_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL3_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL3_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL3_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL3_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL3_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL3_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL3_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL3_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL3_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL3_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL3_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL3_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd3_dispdec -#define mmBLND3_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND3_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND3_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND3_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND3_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND3_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND3_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc3_dispdec -#define mmCRTC3_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC3_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC3_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC3_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC3_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC3_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC3_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC3_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC3_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC3_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC3_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt3_dispdec -#define mmFMT3_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT3_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT3_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT3_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT3_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT3_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT3_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT3_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT3_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp4_dispdec -#define mmDCP4_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP4_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP4_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP4_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP4_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP4_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP4_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP4_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP4_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP4_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP4_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP4_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP4_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP4_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP4_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP4_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP4_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP4_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP4_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP4_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP4_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP4_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP4_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP4_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP4_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP4_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP4_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP4_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP4_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP4_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP4_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP4_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP4_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP4_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP4_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP4_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP4_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP4_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP4_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP4_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP4_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP4_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP4_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP4_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP4_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP4_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP4_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP4_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP4_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP4_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP4_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP4_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP4_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb4_dispdec -#define mmLB4_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB4_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB4_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB4_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB4_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB4_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB4_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB4_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB4_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB4_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB4_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB4_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB4_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB4_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB4_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB4_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB4_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB4_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe4_dispdec -#define mmDCFE4_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE4_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE4_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon7_dispdec -#define mmDC_PERFMON7_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON7_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON7_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg4_dispdec -#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG4_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl4_dispdec -#define mmSCL4_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL4_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL4_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL4_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL4_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL4_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL4_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL4_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL4_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL4_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL4_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL4_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL4_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL4_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd4_dispdec -#define mmBLND4_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND4_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND4_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND4_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND4_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND4_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND4_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc4_dispdec -#define mmCRTC4_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC4_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC4_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC4_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC4_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC4_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC4_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC4_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC4_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC4_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC4_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt4_dispdec -#define mmFMT4_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT4_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT4_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT4_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT4_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT4_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT4_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT4_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT4_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcp5_dispdec -#define mmDCP5_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmDCP5_GRPH_CONTROL_DEFAULT 0x20002040 -#define mmDCP5_GRPH_LUT_10BIT_BYPASS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PITCH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_OFFSET_X_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_OFFSET_Y_DEFAULT 0x00000000 -#define mmDCP5_GRPH_X_START_DEFAULT 0x00000000 -#define mmDCP5_GRPH_Y_START_DEFAULT 0x00000000 -#define mmDCP5_GRPH_X_END_DEFAULT 0x00000000 -#define mmDCP5_GRPH_Y_END_DEFAULT 0x00000000 -#define mmDCP5_INPUT_GAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmDCP5_GRPH_FLIP_CONTROL_DEFAULT 0x00000020 -#define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE_DEFAULT 0x00000000 -#define mmDCP5_GRPH_DFQ_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_DFQ_STATUS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE_DEFAULT 0x00000000 -#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_COMPRESS_PITCH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x000000ff -#define mmDCP5_PRESCALE_GRPH_CONTROL_DEFAULT 0x00000010 -#define mmDCP5_PRESCALE_VALUES_GRPH_R_DEFAULT 0x20000000 -#define mmDCP5_PRESCALE_VALUES_GRPH_G_DEFAULT 0x20000000 -#define mmDCP5_PRESCALE_VALUES_GRPH_B_DEFAULT 0x20000000 -#define mmDCP5_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_INPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_INPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_INPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_OUTPUT_CSC_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_OUTPUT_CSC_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_OUTPUT_CSC_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXA_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXA_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXA_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXB_TRANS_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_COMM_MATRIXB_TRANS_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_COMM_MATRIXB_TRANS_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_DENORM_CONTROL_DEFAULT 0x00000003 -#define mmDCP5_OUT_ROUND_CONTROL_DEFAULT 0x0000000a -#define mmDCP5_OUT_CLAMP_CONTROL_R_CR_DEFAULT 0x00003fff -#define mmDCP5_OUT_CLAMP_CONTROL_G_Y_DEFAULT 0x00003fff -#define mmDCP5_OUT_CLAMP_CONTROL_B_CB_DEFAULT 0x00003fff -#define mmDCP5_KEY_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_ALPHA_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_RED_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_GREEN_DEFAULT 0x00000000 -#define mmDCP5_KEY_RANGE_BLUE_DEFAULT 0x00000000 -#define mmDCP5_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmDCP5_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmDCP5_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmDCP5_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 -#define mmDCP5_DCP_SPATIAL_DITHER_CNTL_DEFAULT 0x00000000 -#define mmDCP5_DCP_RANDOM_SEEDS_DEFAULT 0x00000000 -#define mmDCP5_DCP_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmDCP5_CUR_CONTROL_DEFAULT 0x00000810 -#define mmDCP5_CUR_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_CUR_SIZE_DEFAULT 0x00000000 -#define mmDCP5_CUR_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_CUR_POSITION_DEFAULT 0x00000000 -#define mmDCP5_CUR_HOT_SPOT_DEFAULT 0x00000000 -#define mmDCP5_CUR_COLOR1_DEFAULT 0x00000000 -#define mmDCP5_CUR_COLOR2_DEFAULT 0x00000000 -#define mmDCP5_CUR_UPDATE_DEFAULT 0x00000000 -#define mmDCP5_CUR_REQUEST_FILTER_CNTL_DEFAULT 0x00000000 -#define mmDCP5_CUR_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_RW_MODE_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP5_DC_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_BLACK_OFFSET_RED_DEFAULT 0x00000000 -#define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE_DEFAULT 0x0000ffff -#define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN_DEFAULT 0x0000ffff -#define mmDCP5_DC_LUT_WHITE_OFFSET_RED_DEFAULT 0x0000ffff -#define mmDCP5_DCP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_DCP_CRC_MASK_DEFAULT 0x00000000 -#define mmDCP5_DCP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmDCP5_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmDCP5_DCP_CRC_LAST_DEFAULT 0x00000000 -#define mmDCP5_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmDCP5_GRPH_FLIP_RATE_CNTL_DEFAULT 0x00000000 -#define mmDCP5_DCP_GSL_CONTROL_DEFAULT 0x60000020 -#define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000035 -#define mmDCP5_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00000200 -#define mmDCP5_HW_ROTATION_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL_DEFAULT 0x00000010 -#define mmDCP5_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmDCP5_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmDCP5_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmDCP5_ALPHA_CONTROL_DEFAULT 0x00000002 -#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_FLIP_TIMEOUT_DEFAULT 0x00000000 -#define mmDCP5_GRPH_XDMA_FLIP_AVG_DELAY_DEFAULT 0x00000000 -#define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL_DEFAULT 0x00000012 -#define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_lb5_dispdec -#define mmLB5_LB_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLB5_LB_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLB5_LB_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE_START_END_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLB5_LB_V_COUNTER_DEFAULT 0x00000000 -#define mmLB5_LB_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLB5_LB_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLB5_LB_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLB5_LB_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLB5_LB_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLB5_LB_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLB5_LB_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLB5_LB_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLB5_LB_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLB5_LB_BUFFER_STATUS_DEFAULT 0x00000002 -#define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 -#define mmLB5_MVP_AFR_FLIP_MODE_DEFAULT 0x00000000 -#define mmLB5_MVP_AFR_FLIP_FIFO_CNTL_DEFAULT 0x00000000 -#define mmLB5_MVP_FLIP_LINE_NUM_INSERT_DEFAULT 0x00000002 -#define mmLB5_DC_MVP_LB_CONTROL_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dcfe5_dispdec -#define mmDCFE5_DCFE_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFE5_DCFE_MISC_DEFAULT 0x00000001 -#define mmDCFE5_DCFE_FLUSH_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon8_dispdec -#define mmDC_PERFMON8_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON8_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON8_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmif_pg5_dispdec -#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL_DEFAULT 0x000bf777 -#define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_URGENT_LEVEL_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL2_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_PIPE_LOW_POWER_CONTROL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIF_PG5_DPG_DVMM_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_scl5_dispdec -#define mmSCL5_SCL_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCL5_SCL_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_DEFAULT 0x00000000 -#define mmSCL5_SCL_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_BYPASS_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL5_SCL_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL5_SCL_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCL5_SCL_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCL5_SCL_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCL5_SCL_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCL5_SCL_UPDATE_DEFAULT 0x00000000 -#define mmSCL5_SCL_F_SHARP_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS_DEFAULT 0x00000000 -#define mmSCL5_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCL5_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCL5_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCL5_SCL_MODE_CHANGE_MASK_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blnd5_dispdec -#define mmBLND5_BLND_CONTROL_DEFAULT 0xff0220ff -#define mmBLND5_BLND_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLND5_BLND_CONTROL2_DEFAULT 0x00000010 -#define mmBLND5_BLND_UPDATE_DEFAULT 0x00000000 -#define mmBLND5_BLND_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLND5_BLND_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLND5_BLND_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtc5_dispdec -#define mmCRTC5_CRTC_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTC5_CRTC_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VBI_END_DEFAULT 0x00000003 -#define mmCRTC5_CRTC_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CONTROL_DEFAULT 0x80400110 -#define mmCRTC5_CRTC_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTC5_CRTC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTC5_CRTC_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTC5_CRTC_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTC5_CRTC_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTC5_CRTC_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_GSL_CONTROL_DEFAULT 0x00020000 -#define mmCRTC5_CRTC_RANGE_TIMING_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTC5_CRTC_DRR_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_fmt5_dispdec -#define mmFMT5_FMT_CLAMP_COMPONENT_R_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_G_DEFAULT 0x00000000 -#define mmFMT5_FMT_CLAMP_COMPONENT_B_DEFAULT 0x00000000 -#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_BIT_DEPTH_CONTROL_DEFAULT 0x00600000 -#define mmFMT5_FMT_DITHER_RAND_R_SEED_DEFAULT 0x00000000 -#define mmFMT5_FMT_DITHER_RAND_G_SEED_DEFAULT 0x00000099 -#define mmFMT5_FMT_DITHER_RAND_B_SEED_DEFAULT 0x000000dd -#define mmFMT5_FMT_CLAMP_CNTL_DEFAULT 0x00000000 -#define mmFMT5_FMT_CRC_CNTL_DEFAULT 0x01000040 -#define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK_DEFAULT 0x00ff00ff -#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK_DEFAULT 0x000700ff -#define mmFMT5_FMT_CRC_SIG_RED_GREEN_DEFAULT 0x00000000 -#define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmFMT5_FMT_420_HBLANK_EARLY_START_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_unp0_dispdec -#define mmUNP0_UNP_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmUNP0_UNP_GRPH_CONTROL_DEFAULT 0x0a008008 -#define mmUNP0_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000 -#define mmUNP0_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PITCH_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_PITCH_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_START_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_START_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_START_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_START_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_END_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_X_END_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_END_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_Y_END_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000 -#define mmUNP0_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmUNP0_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000 -#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmUNP0_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220 -#define mmUNP0_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020 -#define mmUNP0_UNP_FLIP_CONTROL_DEFAULT 0x00000001 -#define mmUNP0_UNP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmUNP0_UNP_CRC_MASK_DEFAULT 0x00000000 -#define mmUNP0_UNP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmUNP0_UNP_CRC_LAST_DEFAULT 0x00000000 -#define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100 -#define mmUNP0_UNP_HW_ROTATION_DEFAULT 0x00000010 - - -// addressBlock: dce_dc_lbv0_dispdec -#define mmLBV0_LBV_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLBV0_LBV_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLBV0_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE_START_END_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLBV0_LBV_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV0_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV0_LBV_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLBV0_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLBV0_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLBV0_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLBV0_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLBV0_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLBV0_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLBV0_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLBV0_LBV_BUFFER_STATUS_DEFAULT 0x12000002 -#define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_sclv0_dispdec -#define mmSCLV0_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCLV0_SCLV_UPDATE_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000 - - -// addressBlock: dce_dc_col_man0_dispdec -#define mmCOL_MAN0_COL_MAN_UPDATE_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN0_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN0_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_PRESCALE_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_PRESCALE_VALUES_R_DEFAULT 0x20000000 -#define mmCOL_MAN0_PRESCALE_VALUES_G_DEFAULT 0x20000000 -#define mmCOL_MAN0_PRESCALE_VALUES_B_DEFAULT 0x20000000 -#define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN0_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff -#define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff -#define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff -#define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN0_PACK_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN0_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000 -#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000 -#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000 -#define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000 -#define mmCOL_MAN0_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCOL_MAN0_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 - - -// addressBlock: dce_dc_dcfev0_dispdec -#define mmDCFEV0_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_L_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_C_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV0_DCFEV_MISC_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dc_perfmon11_dispdec -#define mmDC_PERFMON11_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON11_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON11_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmifv_pg0_dispdec -#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blndv0_dispdec -#define mmBLNDV0_BLNDV_CONTROL_DEFAULT 0xff0220ff -#define mmBLNDV0_BLNDV_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLNDV0_BLNDV_CONTROL2_DEFAULT 0x00000010 -#define mmBLNDV0_BLNDV_UPDATE_DEFAULT 0x00000000 -#define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLNDV0_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLNDV0_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtcv0_dispdec -#define mmCRTCV0_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTCV0_CRTCV_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VBI_END_DEFAULT 0x00000003 -#define mmCRTCV0_CRTCV_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CONTROL_DEFAULT 0x80400110 -#define mmCRTCV0_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTCV0_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTCV0_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTCV0_CRTCV_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTCV0_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTCV0_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTCV0_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTCV0_CRTCV_GSL_CONTROL_DEFAULT 0x00020000 - - -// addressBlock: dce_dc_unp1_dispdec -#define mmUNP1_UNP_GRPH_ENABLE_DEFAULT 0x00000001 -#define mmUNP1_UNP_GRPH_CONTROL_DEFAULT 0x0a008008 -#define mmUNP1_UNP_GRPH_CONTROL_C_DEFAULT 0x00008000 -#define mmUNP1_UNP_GRPH_CONTROL_EXP_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PITCH_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_PITCH_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_START_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_START_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_START_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_START_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_END_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_X_END_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_END_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_Y_END_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_UPDATE_DEFAULT 0x00000000 -#define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_DEFAULT 0x0000ffff -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_DEFAULT 0x00000000 -#define mmUNP1_UNP_DVMM_PTE_CONTROL_DEFAULT 0x00004000 -#define mmUNP1_UNP_DVMM_PTE_CONTROL_C_DEFAULT 0x00004000 -#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_DEFAULT 0x00002220 -#define mmUNP1_UNP_DVMM_PTE_ARB_CONTROL_C_DEFAULT 0x00002220 -#define mmUNP1_UNP_GRPH_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP_DEFAULT 0x00002020 -#define mmUNP1_UNP_FLIP_CONTROL_DEFAULT 0x00000001 -#define mmUNP1_UNP_CRC_CONTROL_DEFAULT 0x00000000 -#define mmUNP1_UNP_CRC_MASK_DEFAULT 0x00000000 -#define mmUNP1_UNP_CRC_CURRENT_DEFAULT 0x00000000 -#define mmUNP1_UNP_CRC_LAST_DEFAULT 0x00000000 -#define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK_DEFAULT 0x00000100 -#define mmUNP1_UNP_HW_ROTATION_DEFAULT 0x00000010 - - -// addressBlock: dce_dc_lbv1_dispdec -#define mmLBV1_LBV_DATA_FORMAT_DEFAULT 0x00000000 -#define mmLBV1_LBV_MEMORY_CTRL_DEFAULT 0x000006b0 -#define mmLBV1_LBV_MEMORY_SIZE_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_DESKTOP_HEIGHT_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE_START_END_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE2_START_END_DEFAULT 0x00000000 -#define mmLBV1_LBV_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_DEFAULT 0x00000000 -#define mmLBV1_LBV_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA_DEFAULT 0x00000000 -#define mmLBV1_LBV_INTERRUPT_MASK_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_VLINE2_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_VBLANK_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_SYNC_RESET_SEL_DEFAULT 0x00000002 -#define mmLBV1_LBV_BLACK_KEYER_R_CR_DEFAULT 0x00000000 -#define mmLBV1_LBV_BLACK_KEYER_G_Y_DEFAULT 0x00000000 -#define mmLBV1_LBV_BLACK_KEYER_B_CB_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_CTRL_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_R_CR_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_G_Y_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_B_CB_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_REP_R_CR_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_REP_G_Y_DEFAULT 0x00000000 -#define mmLBV1_LBV_KEYER_COLOR_REP_B_CB_DEFAULT 0x00000000 -#define mmLBV1_LBV_BUFFER_LEVEL_STATUS_DEFAULT 0xa0008000 -#define mmLBV1_LBV_BUFFER_URGENCY_CTRL_DEFAULT 0x00200010 -#define mmLBV1_LBV_BUFFER_URGENCY_STATUS_DEFAULT 0x00000000 -#define mmLBV1_LBV_BUFFER_STATUS_DEFAULT 0x12000002 -#define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_sclv1_dispdec -#define mmSCLV1_SCLV_COEF_RAM_SELECT_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_COEF_RAM_TAP_DATA_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_TAP_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_C_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_ROUND_OFFSET_DEFAULT 0x80000000 -#define mmSCLV1_SCLV_UPDATE_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_ALU_CONTROL_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_SIZE_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_VIEWPORT_SIZE_C_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_DET1_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_DET2_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_DET3_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_MODE_CHANGE_MASK_DEFAULT 0x00000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_DEFAULT 0x01000000 -#define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C_DEFAULT 0x01000000 - - -// addressBlock: dce_dc_col_man1_dispdec -#define mmCOL_MAN1_COL_MAN_UPDATE_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_INPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN1_INPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_INPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_INPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN1_INPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_PRESCALE_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_PRESCALE_VALUES_R_DEFAULT 0x20000000 -#define mmCOL_MAN1_PRESCALE_VALUES_G_DEFAULT 0x20000000 -#define mmCOL_MAN1_PRESCALE_VALUES_B_DEFAULT 0x20000000 -#define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A_DEFAULT 0x20000000 -#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A_DEFAULT 0x00002000 -#define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B_DEFAULT 0x20000000 -#define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B_DEFAULT 0x00002000 -#define mmCOL_MAN1_DENORM_CLAMP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR_DEFAULT 0x00000fff -#define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y_DEFAULT 0x00000fff -#define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB_DEFAULT 0x00000fff -#define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_LUT_WRITE_EN_MASK_DEFAULT 0x00000007 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLA_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_START_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_SLOPE_CNTL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_END_CNTL2_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_0_1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_2_3_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_4_5_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_6_7_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_8_9_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_10_11_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_12_13_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_REGAMMA_CNTLB_REGION_14_15_DEFAULT 0x00000000 -#define mmCOL_MAN1_PACK_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN1_OUTPUT_FIFO_ERROR_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA_DEFAULT 0x00000000 -#define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2_DEFAULT 0x03800000 -#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B_DEFAULT 0xffff0000 -#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G_DEFAULT 0xffff0000 -#define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R_DEFAULT 0xffff0000 -#define mmCOL_MAN1_COL_MAN_DEGAMMA_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_CONTROL_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C11_C12_DEFAULT 0x00002000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C13_C14_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C21_C22_DEFAULT 0x20000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C23_C24_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C31_C32_DEFAULT 0x00000000 -#define mmCOL_MAN1_COL_MAN_GAMUT_REMAP_C33_C34_DEFAULT 0x00002000 - - -// addressBlock: dce_dc_dcfev1_dispdec -#define mmDCFEV1_DCFEV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_SOFT_RESET_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MEM_PWR_CTRL_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MEM_PWR_CTRL2_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MEM_PWR_STATUS_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_L_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_C_FLUSH_DEFAULT 0x00000000 -#define mmDCFEV1_DCFEV_MISC_DEFAULT 0x00000001 - - -// addressBlock: dce_dc_dc_perfmon12_dispdec -#define mmDC_PERFMON12_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON12_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON12_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dmifv_pg1_dispdec -#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL_DEFAULT 0x00030303 -#define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL_DEFAULT 0x00003000 -#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH_DEFAULT 0x00000200 -#define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM_DEFAULT 0x00000000 -#define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_blndv1_dispdec -#define mmBLNDV1_BLNDV_CONTROL_DEFAULT 0xff0220ff -#define mmBLNDV1_BLNDV_SM_CONTROL2_DEFAULT 0x00000000 -#define mmBLNDV1_BLNDV_CONTROL2_DEFAULT 0x00000010 -#define mmBLNDV1_BLNDV_UPDATE_DEFAULT 0x00000000 -#define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT_DEFAULT 0x00000000 -#define mmBLNDV1_BLNDV_V_UPDATE_LOCK_DEFAULT 0x80000000 -#define mmBLNDV1_BLNDV_REG_UPDATE_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_crtcv1_dispdec -#define mmCRTCV1_CRTCV_H_BLANK_EARLY_NUM_DEFAULT 0x00000040 -#define mmCRTCV1_CRTCV_H_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_H_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VBI_END_DEFAULT 0x00000003 -#define mmCRTCV1_CRTCV_V_TOTAL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_MIN_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_MAX_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_TOTAL_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VSYNC_NOM_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_BLANK_START_END_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_A_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_A_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_V_SYNC_B_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_DTMTEST_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_DTMTEST_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGA_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGA_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGB_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TRIGB_MANUAL_TRIG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_FORCE_COUNT_NOW_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_FLOW_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STEREO_FORCE_NEXT_EYE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_AVSYNC_COUNTER_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CONTROL_DEFAULT 0x80400110 -#define mmCRTCV1_CRTCV_BLANK_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_INTERLACE_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_INTERLACE_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_FIELD_INDICATION_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK0_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_PIXEL_DATA_READBACK1_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_NOM_VERT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_FRAME_COUNT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_VF_COUNT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATUS_HV_COUNT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_COUNT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_COUNT_RESET_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERT_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STEREO_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STEREO_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_SNAPSHOT_FRAME_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_START_LINE_CONTROL_DEFAULT 0x00003002 -#define mmCRTCV1_CRTCV_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_UPDATE_LOCK_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_DOUBLE_BUFFER_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VGA_PARAMETER_CAPTURE_MODE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TEST_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TEST_PATTERN_PARAMETERS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_TEST_PATTERN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MASTER_UPDATE_LOCK_DEFAULT 0x00010000 -#define mmCRTCV1_CRTCV_MASTER_UPDATE_MODE_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MVP_INBAND_CNTL_INSERT_TIMER_DEFAULT 0x00000008 -#define mmCRTCV1_CRTCV_MVP_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_MASTER_EN_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_ALLOW_STOP_OFF_V_CNT_DEFAULT 0x00010000 -#define mmCRTCV1_CRTCV_V_UPDATE_INT_STATUS_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLANK_DATA_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLACK_COLOR_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_BLACK_COLOR_EXT_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT0_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT1_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_POSITION_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_VERTICAL_INTERRUPT2_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC_CNTL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC0_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_DATA_RG_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_CRC1_DATA_B_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_START_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_WINDOW_END_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_STATIC_SCREEN_CONTROL_DEFAULT 0x00010000 -#define mmCRTCV1_CRTCV_3D_STRUCTURE_CONTROL_DEFAULT 0x00000010 -#define mmCRTCV1_CRTCV_GSL_VSYNC_GAP_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_GSL_WINDOW_DEFAULT 0x00000000 -#define mmCRTCV1_CRTCV_GSL_CONTROL_DEFAULT 0x00020000 - - -// addressBlock: dce_dc_hpd0_dispdec -#define mmHPD0_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd1_dispdec -#define mmHPD1_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd2_dispdec -#define mmHPD2_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd3_dispdec -#define mmHPD3_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd4_dispdec -#define mmHPD4_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_hpd5_dispdec -#define mmHPD5_DC_HPD_INT_STATUS_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_INT_CONTROL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_CONTROL_DEFAULT 0x10fa09c4 -#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_DEFAULT 0x00000000 -#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon2_dispdec -#define mmDC_PERFMON2_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON2_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON2_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux0_dispdec -#define mmDP_AUX0_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX0_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux1_dispdec -#define mmDP_AUX1_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX1_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux2_dispdec -#define mmDP_AUX2_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX2_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux3_dispdec -#define mmDP_AUX3_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX3_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux4_dispdec -#define mmDP_AUX4_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX4_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp_aux5_dispdec -#define mmDP_AUX5_AUX_CONTROL_DEFAULT 0x01040000 -#define mmDP_AUX5_AUX_SW_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_ARB_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_SW_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_LS_DATA_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_DEFAULT 0x00320000 -#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_DEFAULT 0x00021002 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_DEFAULT 0x223d1210 -#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_TX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_DPHY_RX_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_DEFAULT 0x00210000 -#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_DEFAULT 0x00000000 -#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig0_dispdec -#define mmDIG0_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG0_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG0_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG0_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG0_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG0_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG0_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG0_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG0_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG0_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG0_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG0_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG0_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG0_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG0_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG0_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG0_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG0_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG0_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG0_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG0_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp0_dispdec -#define mmDP0_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP0_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP0_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP0_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP0_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP0_DP_VID_N_DEFAULT 0x00002000 -#define mmDP0_DP_VID_M_DEFAULT 0x00000000 -#define mmDP0_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP0_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP0_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP0_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP0_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP0_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP0_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP0_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP0_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP0_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP0_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP0_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP0_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP0_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig1_dispdec -#define mmDIG1_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG1_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG1_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG1_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG1_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG1_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG1_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG1_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG1_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG1_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG1_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG1_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG1_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG1_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG1_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG1_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG1_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG1_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG1_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG1_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG1_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp1_dispdec -#define mmDP1_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP1_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP1_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP1_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP1_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP1_DP_VID_N_DEFAULT 0x00002000 -#define mmDP1_DP_VID_M_DEFAULT 0x00000000 -#define mmDP1_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP1_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP1_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP1_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP1_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP1_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP1_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP1_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP1_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP1_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP1_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP1_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP1_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP1_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig2_dispdec -#define mmDIG2_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG2_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG2_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG2_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG2_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG2_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG2_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG2_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG2_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG2_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG2_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG2_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG2_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG2_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG2_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG2_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG2_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG2_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG2_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG2_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG2_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp2_dispdec -#define mmDP2_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP2_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP2_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP2_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP2_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP2_DP_VID_N_DEFAULT 0x00002000 -#define mmDP2_DP_VID_M_DEFAULT 0x00000000 -#define mmDP2_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP2_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP2_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP2_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP2_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP2_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP2_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP2_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP2_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP2_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP2_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP2_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP2_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP2_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig3_dispdec -#define mmDIG3_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG3_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG3_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG3_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG3_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG3_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG3_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG3_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG3_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG3_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG3_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG3_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG3_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG3_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG3_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG3_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG3_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG3_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG3_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG3_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG3_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp3_dispdec -#define mmDP3_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP3_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP3_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP3_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP3_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP3_DP_VID_N_DEFAULT 0x00002000 -#define mmDP3_DP_VID_M_DEFAULT 0x00000000 -#define mmDP3_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP3_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP3_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP3_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP3_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP3_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP3_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP3_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP3_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP3_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP3_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP3_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP3_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP3_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig4_dispdec -#define mmDIG4_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG4_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG4_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG4_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG4_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG4_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG4_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG4_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG4_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG4_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG4_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG4_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG4_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG4_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG4_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG4_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG4_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG4_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG4_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG4_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG4_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp4_dispdec -#define mmDP4_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP4_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP4_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP4_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP4_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP4_DP_VID_N_DEFAULT 0x00002000 -#define mmDP4_DP_VID_M_DEFAULT 0x00000000 -#define mmDP4_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP4_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP4_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP4_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP4_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP4_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP4_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP4_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP4_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP4_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP4_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP4_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP4_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP4_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig5_dispdec -#define mmDIG5_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG5_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG5_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG5_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG5_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG5_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG5_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG5_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG5_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG5_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG5_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG5_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG5_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG5_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG5_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG5_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG5_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG5_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG5_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG5_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG5_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp5_dispdec -#define mmDP5_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP5_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP5_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP5_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP5_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP5_DP_VID_N_DEFAULT 0x00002000 -#define mmDP5_DP_VID_M_DEFAULT 0x00000000 -#define mmDP5_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP5_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP5_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP5_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP5_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP5_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP5_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP5_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP5_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP5_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP5_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP5_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP5_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP5_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dig6_dispdec -#define mmDIG6_DIG_FE_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_OUTPUT_CRC_CNTL_DEFAULT 0x00000100 -#define mmDIG6_DIG_OUTPUT_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_DIG_CLOCK_PATTERN_DEFAULT 0x00000063 -#define mmDIG6_DIG_TEST_PATTERN_DEFAULT 0x00000060 -#define mmDIG6_DIG_RANDOM_PATTERN_SEED_DEFAULT 0x00222222 -#define mmDIG6_DIG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_CONTROL_DEFAULT 0x00010001 -#define mmDIG6_HDMI_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_DEFAULT 0x00000010 -#define mmDIG6_HDMI_ACR_PACKET_CONTROL_DEFAULT 0x00010000 -#define mmDIG6_HDMI_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_INFOFRAME_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INTERRUPT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GC_DEFAULT 0x00000004 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC1_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_ISRC2_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AVI_INFO3_DEFAULT 0x02000000 -#define mmDIG6_AFMT_MPEG_INFO0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_MPEG_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_HDR_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_4_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_5_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_6_DEFAULT 0x00000000 -#define mmDIG6_AFMT_GENERIC_7_DEFAULT 0x00000000 -#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_32_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_44_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_48_1_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_0_DEFAULT 0x00000000 -#define mmDIG6_HDMI_ACR_STATUS_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_INFO0_DEFAULT 0x00000170 -#define mmDIG6_AFMT_AUDIO_INFO1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL1_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_RAMP_CONTROL3_DEFAULT 0x00000000 -#define mmDIG6_AFMT_60958_2_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_CRC_RESULT_DEFAULT 0x00000000 -#define mmDIG6_AFMT_STATUS_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_DEFAULT 0x00000800 -#define mmDIG6_AFMT_VBI_PACKET_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_AFMT_INFOFRAME_CONTROL0_DEFAULT 0x00000000 -#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_DEFAULT 0x00000000 -#define mmDIG6_DIG_BE_CNTL_DEFAULT 0x00010000 -#define mmDIG6_DIG_BE_EN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CNTL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CONTROL_CHAR_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CONTROL0_FEEDBACK_DEFAULT 0x00000000 -#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_DEFAULT 0x00000000 -#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL_BITS_DEFAULT 0x00000000 -#define mmDIG6_TMDS_DCBALANCER_CONTROL_DEFAULT 0x00000001 -#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_DEFAULT 0x00000000 -#define mmDIG6_DIG_VERSION_DEFAULT 0x00000000 -#define mmDIG6_DIG_LANE_ENABLE_DEFAULT 0x00000000 -#define mmDIG6_AFMT_CNTL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dp6_dispdec -#define mmDP6_DP_LINK_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_COLORIMETRY_DEFAULT 0x00000000 -#define mmDP6_DP_CONFIG_DEFAULT 0x00000000 -#define mmDP6_DP_VID_STREAM_CNTL_DEFAULT 0x00000200 -#define mmDP6_DP_STEER_FIFO_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_MISC_DEFAULT 0x00000000 -#define mmDP6_DP_VID_TIMING_DEFAULT 0x00000000 -#define mmDP6_DP_VID_N_DEFAULT 0x00002000 -#define mmDP6_DP_VID_M_DEFAULT 0x00000000 -#define mmDP6_DP_LINK_FRAMING_CNTL_DEFAULT 0x10002000 -#define mmDP6_DP_HBR2_EYE_PATTERN_DEFAULT 0x00000000 -#define mmDP6_DP_VID_MSA_VBID_DEFAULT 0x01000000 -#define mmDP6_DP_VID_INTERRUPT_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM0_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM1_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_SYM2_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_8B10B_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_PRBS_CNTL_DEFAULT 0x7fffff00 -#define mmDP6_DP_DPHY_SCRAM_CNTL_DEFAULT 0x0101ff10 -#define mmDP6_DP_DPHY_CRC_EN_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_CNTL_DEFAULT 0x00ff0000 -#define mmDP6_DP_DPHY_CRC_RESULT_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_CRC_MST_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_FAST_TRAINING_DEFAULT 0x20020000 -#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_V_TIMING_OVERRIDE1_DEFAULT 0x00000000 -#define mmDP6_DP_MSA_V_TIMING_OVERRIDE2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_CNTL1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING1_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING2_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_FRAMING3_DEFAULT 0x00000200 -#define mmDP6_DP_SEC_FRAMING4_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_N_DEFAULT 0x00008000 -#define mmDP6_DP_SEC_AUD_N_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_AUD_M_READBACK_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_TIMESTAMP_DEFAULT 0x00000000 -#define mmDP6_DP_SEC_PACKET_CNTL_DEFAULT 0x00001100 -#define mmDP6_DP_MSE_RATE_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_RATE_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT_UPDATE_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_LINK_TIMING_DEFAULT 0x000203ff -#define mmDP6_DP_MSE_MISC_CNTL_DEFAULT 0x00000000 -#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_DEFAULT 0x00000005 -#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT0_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT1_STATUS_DEFAULT 0x00000000 -#define mmDP6_DP_MSE_SAT2_STATUS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy0_dispdec -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs0_dispdec -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs0_dispdec -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs0_dispdec -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy1_dispdec -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs1_dispdec -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs1_dispdec -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs1_dispdec -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy2_dispdec -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs2_dispdec -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs2_dispdec -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs2_dispdec -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy3_dispdec -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs3_dispdec -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs3_dispdec -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs3_dispdec -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy4_dispdec -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs4_dispdec -#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS4_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs4_dispdec -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs4_dispdec -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS4_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS4_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS4_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy5_dispdec -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs5_dispdec -#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS5_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs5_dispdec -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs5_dispdec -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS5_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS5_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS5_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy6_dispdec -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs6_dispdec -#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS6_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs6_dispdec -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs6_dispdec -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS6_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS6_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS6_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dcio_uniphy8_dispdec -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED32_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED33_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED34_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED35_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED36_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED37_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED38_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED39_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED40_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED41_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED42_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED43_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED44_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED45_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED46_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED47_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED48_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED49_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED50_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED51_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED52_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED53_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED54_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED55_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED56_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED57_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED58_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED59_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED60_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED61_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED62_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED63_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED64_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED65_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED66_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED67_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED68_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED69_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED70_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED71_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED72_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED73_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED74_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED75_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED76_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED77_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED78_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED79_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED80_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED81_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED82_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED83_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED84_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED85_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED86_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED87_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED88_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED89_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED90_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED91_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED92_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED93_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED94_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED95_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED96_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED97_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED98_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED99_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED100_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED101_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED102_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED103_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED104_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED105_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED106_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED107_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED108_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED109_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED110_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED111_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED112_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED113_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED114_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED115_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED116_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED117_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED118_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED119_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED120_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED121_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED122_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED123_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED124_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED125_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED126_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED127_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED128_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED129_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED130_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED131_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED132_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED133_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED134_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED135_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED136_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED137_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED138_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED139_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED140_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED141_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED142_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED143_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED144_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED145_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED146_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED147_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED148_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED149_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED150_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED151_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED152_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED153_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED154_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED155_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED156_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED157_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED158_DEFAULT 0x00000000 -#define mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED159_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophycmregs8_dispdec -#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_FUSE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_MAR_DEEMPH_NOM_DEFAULT 0x402a2a00 -#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_PWRMGMT_DEFAULT 0x00000004 -#define mmDC_COMBOPHYCMREGS8_COMMON_TXCNTRL_DEFAULT 0x00000007 -#define mmDC_COMBOPHYCMREGS8_COMMON_TMDP_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_LANE_RESETS_DEFAULT 0x000000ff -#define mmDC_COMBOPHYCMREGS8_COMMON_ZCALCODE_CTRL_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU4_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU5_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU6_DEFAULT 0x00000000 -#define mmDC_COMBOPHYCMREGS8_COMMON_DISP_RFU7_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophytxregs8_dispdec -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE0_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE0_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE1_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE1_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE2_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE2_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_TX_CONTROL_LANE3_DEFAULT 0x00000006 -#define mmDC_COMBOPHYTXREGS8_MARGIN_DEEMPH_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_CMD_BUS_GLOBAL_FOR_TX_LANE3_DEFAULT 0x00000040 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU0_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU1_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU2_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU3_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU4_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU5_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU6_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU7_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU8_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU9_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU10_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU11_LANE3_DEFAULT 0x00000000 -#define mmDC_COMBOPHYTXREGS8_TX_DISP_RFU12_LANE3_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_combophypllregs8_dispdec -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL0_DEFAULT 0x00280000 -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL2_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_FREQ_CTRL3_DEFAULT 0x00e80000 -#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_COARSE_DEFAULT 0x0020c4b1 -#define mmDC_COMBOPHYPLLREGS8_BW_CTRL_FINE_DEFAULT 0x00000001 -#define mmDC_COMBOPHYPLLREGS8_CAL_CTRL_DEFAULT 0x64000000 -#define mmDC_COMBOPHYPLLREGS8_LOOP_CTRL_DEFAULT 0x00000090 -#define mmDC_COMBOPHYPLLREGS8_VREG_CFG_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_OBSERVE0_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_OBSERVE1_DEFAULT 0x00000000 -#define mmDC_COMBOPHYPLLREGS8_DFT_OUT_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dsi0_dispdec -#define mmDSI0_DISP_DSI_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101 -#define mmDSI0_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e -#define mmDSI0_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900 -#define mmDSI0_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066 -#define mmDSI0_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c -#define mmDSI0_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900 -#define mmDSI0_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211 -#define mmDSI0_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02 -#define mmDSI0_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EXT_MUX_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EXT_RESET_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888 -#define mmDSI0_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff -#define mmDSI0_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff -#define mmDSI0_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08 -#define mmDSI0_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f -#define mmDSI0_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222 -#define mmDSI0_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001 -#define mmDSI0_DISP_DSI_TE_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000 -#define mmDSI0_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dsi1_dispdec -#define mmDSI1_DISP_DSI_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_CTRL_DEFAULT 0x00008000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_SYNC_DATATYPE_DEFAULT 0x31211101 -#define mmDSI1_DISP_DSI_VIDEO_MODE_VSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_HSYNC_PAYLOAD_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_VIDEO_MODE_PIXEL_DATATYPE_DEFAULT 0x3e2e1e0e -#define mmDSI1_DISP_DSI_VIDEO_MODE_BLANKING_DATATYPE_DEFAULT 0x00001900 -#define mmDSI1_DISP_DSI_VIDEO_MODE_DATA_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_COMMAND_MODE_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_COMMAND_MODE_DATA_CTRL_DEFAULT 0x00000066 -#define mmDSI1_DISP_DSI_COMMAND_MODE_DCS_CMD_CTRL_DEFAULT 0x00003c2c -#define mmDSI1_DISP_DSI_DMA_CMD_OFFSET_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_CMD_LENGTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_0_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_OFFSET_1_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_PITCH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_WIDTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_DATA_HEIGHT_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DMA_NULL_PACKET_DATA_DEFAULT 0x00000900 -#define mmDSI1_DISP_DSI_DENG_DATA_LENGTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_ACK_ERROR_REPORT_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA0_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA1_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA2_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATA3_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_DATATYPE0_DEFAULT 0x22211211 -#define mmDSI1_DISP_DSI_RDBK_DATATYPE1_DEFAULT 0x001c1a02 -#define mmDSI1_DISP_DSI_TRIG_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EXT_MUX_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EXT_TE_PULSE_DETECTION_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MODE_DMA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MODE_DENG_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MODE_BTA_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RESET_SW_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EXT_RESET_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CRC_HS_MODE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CRC_LP_MODE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PIXEL_CRC_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DLN0_PHY_ERROR_DEFAULT 0x00088888 -#define mmDSI1_DISP_DSI_LP_TIMER_CTRL_DEFAULT 0xffffffff -#define mmDSI1_DISP_DSI_HS_TIMER_CTRL_DEFAULT 0x0000ffff -#define mmDSI1_DISP_DSI_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PHY_CLK_TIMING_CTRL2_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_EOT_PACKET_DEFAULT 0x010f0f08 -#define mmDSI1_DISP_DSI_EOT_PACKET_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_GENERIC_ESC_TX_TRIGGER_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_SIZE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_BLOCK_SIZE_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_FRAME_CONFIG_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_LSFR_INIT_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_START_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_MIPI_BIST_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_ERROR_INTERRUPT_MASK_DEFAULT 0xfd37377f -#define mmDSI1_DISP_DSI_INTERRUPT_CTRL_DEFAULT 0x02222222 -#define mmDSI1_DISP_DSI_CLK_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CLK_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DENG_FIFO_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_DENG_FIFO_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_FIFO_DATA_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_FIFO_CTRL_DEFAULT 0x00000001 -#define mmDSI1_DISP_DSI_TE_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_LANE_STATUS_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_PERF_CTRL_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_HSYNC_LENGTH_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_RDBK_NUM_DEFAULT 0x00000000 -#define mmDSI1_DISP_DSI_CMD_MEM_PWR_CTRL_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dprx_sd0_dispdec -#define mmDPRX_SD0_DPRX_SD_CONTROL_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA0_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA1_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA2_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA3_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA4_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA5_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA6_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA7_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA8_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VBID_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_SAT_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD0_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff -#define mmDPRX_SD0_DPRX_SD_SDP_STEER_DEFAULT 0x00000001 -#define mmDPRX_SD0_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_DATA_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001 -#define mmDPRX_SD0_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000 -#define mmDPRX_SD0_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dprx_sd1_dispdec -#define mmDPRX_SD1_DPRX_SD_CONTROL_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_STREAM_ENABLE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA0_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA1_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA2_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA3_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA4_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA5_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA6_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA7_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA8_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VBID_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_CURRENT_LINE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_DISPLAY_TIMER_MODE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_SAT_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_FORCE_UPDATE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_SAT_ACTIVE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_V_PARAMETER_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_PIXEL_FORMAT_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSA_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VIDEO_STREAM_STATUS_TOGGLED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER0_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_LINE_NUMBER1_CONTROL_DEFAULT 0x0000ffff -#define mmDPRX_SD1_DPRX_SD_MAIN_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VBID_MAJORITY_VOTE_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SECONDARY_DEFRAMING_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_LOCKED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_VCPF_PHASE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MAJORITY_VOTE_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_PIXEL_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MAXIMUM_SDP_PAYLOAD_LENGTH_DEFAULT 0x000003ff -#define mmDPRX_SD1_DPRX_SD_SDP_STEER_DEFAULT 0x00000001 -#define mmDPRX_SD1_DPRX_SD_SDP_RECEIVED_STATUS_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_LEVEL_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_DATA_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_AUDIO_HEADER_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_AUDIO_FIFO_ERROR_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_SDP_CONTROL_DEFAULT 0x00000001 -#define mmDPRX_SD1_DPRX_SD_V_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_H_TOTAL_MEASURED_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_BS_COUNTER_DEFAULT 0x00000000 -#define mmDPRX_SD1_DPRX_SD_MSE_ACT_HANDLED_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_perfmon10_dispdec -#define mmDC_PERFMON10_PERFCOUNTER_CNTL_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFCOUNTER_STATE_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CNTL_DEFAULT 0x00000100 -#define mmDC_PERFMON10_PERFMON_CNTL2_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_HI_DEFAULT 0x00000000 -#define mmDC_PERFMON10_PERFMON_LOW_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dc_zcalregs_dispdec -#define mmCOMP_EN_CTL_DEFAULT 0x00080000 -#define mmCOMP_EN_DFX_DEFAULT 0x00000000 -#define mmZCAL_FUSES_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR - - -// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR - - -// addressBlock: dce_dc_dispdec[948..986] - - -// addressBlock: dce_dc_azdec -#define mmCORB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmCORB_READ_POINTER_DEFAULT 0x00000000 -#define mmCORB_CONTROL_DEFAULT 0x00000000 -#define mmCORB_STATUS_DEFAULT 0x00000000 -#define mmCORB_SIZE_DEFAULT 0x00000002 -#define mmRIRB_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmRIRB_WRITE_POINTER_DEFAULT 0x00000000 -#define mmRESPONSE_INTERRUPT_COUNT_DEFAULT 0x00000000 -#define mmRIRB_CONTROL_DEFAULT 0x00000000 -#define mmRIRB_STATUS_DEFAULT 0x00000000 -#define mmRIRB_SIZE_DEFAULT 0x00000002 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_DEFAULT 0x00000000 -#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_DEFAULT 0x00000000 -#define mmIMMEDIATE_COMMAND_STATUS_DEFAULT 0x00000000 -#define mmDMA_POSITION_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmDMA_POSITION_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmWALL_CLOCK_COUNTER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream0_azdec -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream1_azdec -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream2_azdec -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream3_azdec -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream4_azdec -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream5_azdec -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream6_azdec -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: dce_dc_azstream7_azdec -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_DEFAULT 0x00000000 -#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_DEFAULT 0x00000000 - - -// addressBlock: azf0stream0_streamind -#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream1_streamind -#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream2_streamind -#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream3_streamind -#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream4_streamind -#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream5_streamind -#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream6_streamind -#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream7_streamind -#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream8_streamind -#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream9_streamind -#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream10_streamind -#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream11_streamind -#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream12_streamind -#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream13_streamind -#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream14_streamind -#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0stream15_streamind -#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL_DEFAULT 0x00203004 -#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT_DEFAULT 0x00000000 -#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint0_endpointind -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint1_endpointind -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint2_endpointind -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint3_endpointind -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint4_endpointind -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint5_endpointind -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint6_endpointind -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0endpoint7_endpointind -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000221 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00300000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400380 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000094 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0_DEFAULT 0x07010701 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18560010 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0xffffffff -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS_DEFAULT 0x00000000 -#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint0_inputendpointind -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint1_inputendpointind -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint2_inputendpointind -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint3_inputendpointind -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint4_inputendpointind -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint5_inputendpointind -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint6_inputendpointind -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: azf0inputendpoint7_inputendpointind -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00100301 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00020070 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00400280 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x000000a4 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE_DEFAULT 0x7fffffff -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_DEFAULT 0x00000001 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL_DEFAULT 0x00000010 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x18d600f0 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000000 -#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 - - -// addressBlock: f2codecind -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE_DEFAULT 0x00000003 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2_DEFAULT 0x00000001 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3_DEFAULT 0x000000aa -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE_DEFAULT 0x000000b4 -#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000040 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x00000056 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7_DEFAULT 0x00000000 -#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_DEFAULT 0x00000020 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_DEFAULT 0x000000f0 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3_DEFAULT 0x000000d6 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4_DEFAULT 0x00000018 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL_DEFAULT 0x00000010 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DEFAULT 0x00000000 - - -// addressBlock: descriptorind -#define ixAUDIO_DESCRIPTOR0_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR1_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR2_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR3_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR4_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR5_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR6_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR7_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR8_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR9_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR10_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR11_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR12_DEFAULT 0x00000000 -#define ixAUDIO_DESCRIPTOR13_DEFAULT 0x00000000 - - -// addressBlock: sinkinfoind -#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0_DEFAULT 0x00000000 -#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION0_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION1_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION2_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION3_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION4_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION5_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION6_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION7_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION8_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION9_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION10_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION11_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION12_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION13_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION14_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION15_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION16_DEFAULT 0x00000000 -#define ixSINK_DESCRIPTION17_DEFAULT 0x00000000 - - -// addressBlock: azinputcrc0resultind -#define ixAZALIA_INPUT_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azinputcrc1resultind -#define ixAZALIA_INPUT_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_INPUT_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azcrc0resultind -#define ixAZALIA_CRC0_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC0_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: azcrc1resultind -#define ixAZALIA_CRC1_CHANNEL0_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL1_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL2_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL3_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL4_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL5_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL6_DEFAULT 0x00000000 -#define ixAZALIA_CRC1_CHANNEL7_DEFAULT 0x00000000 - - -// addressBlock: vgaseqind -#define ixSEQ00_DEFAULT 0x00000003 -#define ixSEQ01_DEFAULT 0x00000021 -#define ixSEQ02_DEFAULT 0x00000000 -#define ixSEQ03_DEFAULT 0x00000000 -#define ixSEQ04_DEFAULT 0x00000000 - - -// addressBlock: vgacrtind -#define ixCRT00_DEFAULT 0x00000000 -#define ixCRT01_DEFAULT 0x00000000 -#define ixCRT02_DEFAULT 0x00000000 -#define ixCRT03_DEFAULT 0x00000000 -#define ixCRT04_DEFAULT 0x00000000 -#define ixCRT05_DEFAULT 0x00000000 -#define ixCRT06_DEFAULT 0x00000000 -#define ixCRT07_DEFAULT 0x00000000 -#define ixCRT08_DEFAULT 0x00000000 -#define ixCRT09_DEFAULT 0x00000000 -#define ixCRT0A_DEFAULT 0x00000000 -#define ixCRT0B_DEFAULT 0x00000000 -#define ixCRT0C_DEFAULT 0x00000000 -#define ixCRT0D_DEFAULT 0x00000000 -#define ixCRT0E_DEFAULT 0x00000000 -#define ixCRT0F_DEFAULT 0x00000000 -#define ixCRT10_DEFAULT 0x00000000 -#define ixCRT11_DEFAULT 0x00000000 -#define ixCRT12_DEFAULT 0x00000000 -#define ixCRT13_DEFAULT 0x00000000 -#define ixCRT14_DEFAULT 0x00000000 -#define ixCRT15_DEFAULT 0x00000000 -#define ixCRT16_DEFAULT 0x00000000 -#define ixCRT17_DEFAULT 0x00000000 -#define ixCRT18_DEFAULT 0x00000000 -#define ixCRT1E_DEFAULT 0x00000000 -#define ixCRT1F_DEFAULT 0x00000000 -#define ixCRT22_DEFAULT 0x00000000 - - -// addressBlock: vgagrphind -#define ixGRA00_DEFAULT 0x00000000 -#define ixGRA01_DEFAULT 0x00000000 -#define ixGRA02_DEFAULT 0x00000000 -#define ixGRA03_DEFAULT 0x00000000 -#define ixGRA04_DEFAULT 0x00000000 -#define ixGRA05_DEFAULT 0x00000000 -#define ixGRA06_DEFAULT 0x00000000 -#define ixGRA07_DEFAULT 0x00000000 -#define ixGRA08_DEFAULT 0x00000000 - - -// addressBlock: vgaattrind -#define ixATTR00_DEFAULT 0x00000000 -#define ixATTR01_DEFAULT 0x00000000 -#define ixATTR02_DEFAULT 0x00000000 -#define ixATTR03_DEFAULT 0x00000000 -#define ixATTR04_DEFAULT 0x00000000 -#define ixATTR05_DEFAULT 0x00000000 -#define ixATTR06_DEFAULT 0x00000000 -#define ixATTR07_DEFAULT 0x00000000 -#define ixATTR08_DEFAULT 0x00000000 -#define ixATTR09_DEFAULT 0x00000000 -#define ixATTR0A_DEFAULT 0x00000000 -#define ixATTR0B_DEFAULT 0x00000000 -#define ixATTR0C_DEFAULT 0x00000000 -#define ixATTR0D_DEFAULT 0x00000000 -#define ixATTR0E_DEFAULT 0x00000000 -#define ixATTR0F_DEFAULT 0x00000000 -#define ixATTR10_DEFAULT 0x00000000 -#define ixATTR11_DEFAULT 0x00000000 -#define ixATTR12_DEFAULT 0x00000000 -#define ixATTR13_DEFAULT 0x00000000 -#define ixATTR14_DEFAULT 0x00000000 - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h deleted file mode 100644 index 864690cc910a..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _hdp_4_0_DEFAULT_HEADER -#define _hdp_4_0_DEFAULT_HEADER - - -// addressBlock: hdp_hdpdec -#define mmHDP_MMHUB_TLVL_DEFAULT 0x00006666 -#define mmHDP_MMHUB_UNITID_DEFAULT 0x00000000 -#define mmHDP_NONSURFACE_BASE_DEFAULT 0x00000000 -#define mmHDP_NONSURFACE_INFO_DEFAULT 0x00000000 -#define mmHDP_NONSURFACE_BASE_HI_DEFAULT 0x00000000 -#define mmHDP_NONSURF_FLAGS_DEFAULT 0x00000000 -#define mmHDP_NONSURF_FLAGS_CLR_DEFAULT 0x00000000 -#define mmHDP_HOST_PATH_CNTL_DEFAULT 0x00680000 -#define mmHDP_SW_SEMAPHORE_DEFAULT 0x00000000 -#define mmHDP_DEBUG0_DEFAULT 0x00000000 -#define mmHDP_LAST_SURFACE_HIT_DEFAULT 0x00000003 -#define mmHDP_READ_CACHE_INVALIDATE_DEFAULT 0x00000000 -#define mmHDP_OUTSTANDING_REQ_DEFAULT 0x00000000 -#define mmHDP_MISC_CNTL_DEFAULT 0x2d200861 -#define mmHDP_MEM_POWER_LS_DEFAULT 0x00000901 -#define mmHDP_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmHDP_EDC_CNT_DEFAULT 0x00000000 -#define mmHDP_VERSION_DEFAULT 0x00000400 -#define mmHDP_CLK_CNTL_DEFAULT 0x0000000f -#define mmHDP_MEMIO_CNTL_DEFAULT 0x00000000 -#define mmHDP_MEMIO_ADDR_DEFAULT 0x00000000 -#define mmHDP_MEMIO_STATUS_DEFAULT 0x00000000 -#define mmHDP_MEMIO_WR_DATA_DEFAULT 0x00000000 -#define mmHDP_MEMIO_RD_DATA_DEFAULT 0xdeadbeef -#define mmHDP_XDP_DIRECT2HDP_FIRST_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_FLUSH_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_BAR_UPDATE_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_3_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_4_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_5_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_6_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_7_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_8_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_9_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_10_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_11_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_12_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_13_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_14_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_15_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_16_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_17_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_18_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_19_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_20_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_21_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_22_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_23_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_24_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_25_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_26_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_27_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_28_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_29_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_30_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_31_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_32_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_33_DEFAULT 0x00000000 -#define mmHDP_XDP_D2H_RSVD_34_DEFAULT 0x00000000 -#define mmHDP_XDP_DIRECT2HDP_LAST_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR_CFG_DEFAULT 0x0000000f -#define mmHDP_XDP_P2P_MBX_OFFSET_DEFAULT 0x000011bc -#define mmHDP_XDP_P2P_MBX_ADDR0_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR1_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR2_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR3_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR4_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR5_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_MBX_ADDR6_DEFAULT 0x00000000 -#define mmHDP_XDP_HDP_MBX_MC_CFG_DEFAULT 0x00000000 -#define mmHDP_XDP_HDP_MC_CFG_DEFAULT 0x00020000 -#define mmHDP_XDP_HST_CFG_DEFAULT 0x0000001b -#define mmHDP_XDP_HDP_IPH_CFG_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR0_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR1_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR2_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR3_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR4_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR5_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR6_DEFAULT 0x00000000 -#define mmHDP_XDP_P2P_BAR7_DEFAULT 0x00000000 -#define mmHDP_XDP_FLUSH_ARMED_STS_DEFAULT 0x00000000 -#define mmHDP_XDP_FLUSH_CNTR0_STS_DEFAULT 0x00000000 -#define mmHDP_XDP_BUSY_STS_DEFAULT 0x00000000 -#define mmHDP_XDP_STICKY_DEFAULT 0x00000000 -#define mmHDP_XDP_CHKN_DEFAULT 0x48584450 -#define mmHDP_XDP_BARS_ADDR_39_36_DEFAULT 0x00000000 -#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 -#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmHDP_XDP_MMHUB_ERROR_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h deleted file mode 100644 index fbad771a569e..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _hdp_4_0_OFFSET_HEADER -#define _hdp_4_0_OFFSET_HEADER - - - -// addressBlock: hdp_hdpdec -// base address: 0x3c80 -#define mmHDP_MMHUB_TLVL 0x0000 -#define mmHDP_MMHUB_TLVL_BASE_IDX 0 -#define mmHDP_MMHUB_UNITID 0x0001 -#define mmHDP_MMHUB_UNITID_BASE_IDX 0 -#define mmHDP_NONSURFACE_BASE 0x0040 -#define mmHDP_NONSURFACE_BASE_BASE_IDX 0 -#define mmHDP_NONSURFACE_INFO 0x0041 -#define mmHDP_NONSURFACE_INFO_BASE_IDX 0 -#define mmHDP_NONSURFACE_BASE_HI 0x0042 -#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0 -#define mmHDP_NONSURF_FLAGS 0x00c8 -#define mmHDP_NONSURF_FLAGS_BASE_IDX 0 -#define mmHDP_NONSURF_FLAGS_CLR 0x00c9 -#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0 -#define mmHDP_HOST_PATH_CNTL 0x00cc -#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0 -#define mmHDP_SW_SEMAPHORE 0x00cd -#define mmHDP_SW_SEMAPHORE_BASE_IDX 0 -#define mmHDP_DEBUG0 0x00ce -#define mmHDP_DEBUG0_BASE_IDX 0 -#define mmHDP_LAST_SURFACE_HIT 0x00d0 -#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0 -#define mmHDP_READ_CACHE_INVALIDATE 0x00d1 -#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0 -#define mmHDP_OUTSTANDING_REQ 0x00d2 -#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0 -#define mmHDP_MISC_CNTL 0x00d3 -#define mmHDP_MISC_CNTL_BASE_IDX 0 -#define mmHDP_MEM_POWER_LS 0x00d4 -#define mmHDP_MEM_POWER_LS_BASE_IDX 0 -#define mmHDP_MMHUB_CNTL 0x00d5 -#define mmHDP_MMHUB_CNTL_BASE_IDX 0 -#define mmHDP_EDC_CNT 0x00d6 -#define mmHDP_EDC_CNT_BASE_IDX 0 -#define mmHDP_VERSION 0x00d7 -#define mmHDP_VERSION_BASE_IDX 0 -#define mmHDP_CLK_CNTL 0x00d8 -#define mmHDP_CLK_CNTL_BASE_IDX 0 -#define mmHDP_MEMIO_CNTL 0x00f6 -#define mmHDP_MEMIO_CNTL_BASE_IDX 0 -#define mmHDP_MEMIO_ADDR 0x00f7 -#define mmHDP_MEMIO_ADDR_BASE_IDX 0 -#define mmHDP_MEMIO_STATUS 0x00f8 -#define mmHDP_MEMIO_STATUS_BASE_IDX 0 -#define mmHDP_MEMIO_WR_DATA 0x00f9 -#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0 -#define mmHDP_MEMIO_RD_DATA 0x00fa -#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0 -#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100 -#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0 -#define mmHDP_XDP_D2H_FLUSH 0x0101 -#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0 -#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102 -#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_3 0x0103 -#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_4 0x0104 -#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_5 0x0105 -#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_6 0x0106 -#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_7 0x0107 -#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_8 0x0108 -#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_9 0x0109 -#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_10 0x010a -#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_11 0x010b -#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_12 0x010c -#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_13 0x010d -#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_14 0x010e -#define mmHDP_XDP_D2H_RSVD_14_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_15 0x010f -#define mmHDP_XDP_D2H_RSVD_15_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_16 0x0110 -#define mmHDP_XDP_D2H_RSVD_16_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_17 0x0111 -#define mmHDP_XDP_D2H_RSVD_17_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_18 0x0112 -#define mmHDP_XDP_D2H_RSVD_18_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_19 0x0113 -#define mmHDP_XDP_D2H_RSVD_19_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_20 0x0114 -#define mmHDP_XDP_D2H_RSVD_20_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_21 0x0115 -#define mmHDP_XDP_D2H_RSVD_21_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_22 0x0116 -#define mmHDP_XDP_D2H_RSVD_22_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_23 0x0117 -#define mmHDP_XDP_D2H_RSVD_23_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_24 0x0118 -#define mmHDP_XDP_D2H_RSVD_24_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_25 0x0119 -#define mmHDP_XDP_D2H_RSVD_25_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_26 0x011a -#define mmHDP_XDP_D2H_RSVD_26_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_27 0x011b -#define mmHDP_XDP_D2H_RSVD_27_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_28 0x011c -#define mmHDP_XDP_D2H_RSVD_28_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_29 0x011d -#define mmHDP_XDP_D2H_RSVD_29_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_30 0x011e -#define mmHDP_XDP_D2H_RSVD_30_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_31 0x011f -#define mmHDP_XDP_D2H_RSVD_31_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_32 0x0120 -#define mmHDP_XDP_D2H_RSVD_32_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_33 0x0121 -#define mmHDP_XDP_D2H_RSVD_33_BASE_IDX 0 -#define mmHDP_XDP_D2H_RSVD_34 0x0122 -#define mmHDP_XDP_D2H_RSVD_34_BASE_IDX 0 -#define mmHDP_XDP_DIRECT2HDP_LAST 0x0123 -#define mmHDP_XDP_DIRECT2HDP_LAST_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR_CFG 0x0124 -#define mmHDP_XDP_P2P_BAR_CFG_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_OFFSET 0x0125 -#define mmHDP_XDP_P2P_MBX_OFFSET_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR0 0x0126 -#define mmHDP_XDP_P2P_MBX_ADDR0_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR1 0x0127 -#define mmHDP_XDP_P2P_MBX_ADDR1_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR2 0x0128 -#define mmHDP_XDP_P2P_MBX_ADDR2_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR3 0x0129 -#define mmHDP_XDP_P2P_MBX_ADDR3_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR4 0x012a -#define mmHDP_XDP_P2P_MBX_ADDR4_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR5 0x012b -#define mmHDP_XDP_P2P_MBX_ADDR5_BASE_IDX 0 -#define mmHDP_XDP_P2P_MBX_ADDR6 0x012c -#define mmHDP_XDP_P2P_MBX_ADDR6_BASE_IDX 0 -#define mmHDP_XDP_HDP_MBX_MC_CFG 0x012d -#define mmHDP_XDP_HDP_MBX_MC_CFG_BASE_IDX 0 -#define mmHDP_XDP_HDP_MC_CFG 0x012e -#define mmHDP_XDP_HDP_MC_CFG_BASE_IDX 0 -#define mmHDP_XDP_HST_CFG 0x012f -#define mmHDP_XDP_HST_CFG_BASE_IDX 0 -#define mmHDP_XDP_HDP_IPH_CFG 0x0131 -#define mmHDP_XDP_HDP_IPH_CFG_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR0 0x0134 -#define mmHDP_XDP_P2P_BAR0_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR1 0x0135 -#define mmHDP_XDP_P2P_BAR1_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR2 0x0136 -#define mmHDP_XDP_P2P_BAR2_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR3 0x0137 -#define mmHDP_XDP_P2P_BAR3_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR4 0x0138 -#define mmHDP_XDP_P2P_BAR4_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR5 0x0139 -#define mmHDP_XDP_P2P_BAR5_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR6 0x013a -#define mmHDP_XDP_P2P_BAR6_BASE_IDX 0 -#define mmHDP_XDP_P2P_BAR7 0x013b -#define mmHDP_XDP_P2P_BAR7_BASE_IDX 0 -#define mmHDP_XDP_FLUSH_ARMED_STS 0x013c -#define mmHDP_XDP_FLUSH_ARMED_STS_BASE_IDX 0 -#define mmHDP_XDP_FLUSH_CNTR0_STS 0x013d -#define mmHDP_XDP_FLUSH_CNTR0_STS_BASE_IDX 0 -#define mmHDP_XDP_BUSY_STS 0x013e -#define mmHDP_XDP_BUSY_STS_BASE_IDX 0 -#define mmHDP_XDP_STICKY 0x013f -#define mmHDP_XDP_STICKY_BASE_IDX 0 -#define mmHDP_XDP_CHKN 0x0140 -#define mmHDP_XDP_CHKN_BASE_IDX 0 -#define mmHDP_XDP_BARS_ADDR_39_36 0x0144 -#define mmHDP_XDP_BARS_ADDR_39_36_BASE_IDX 0 -#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE 0x0145 -#define mmHDP_XDP_MC_VM_FB_LOCATION_BASE_BASE_IDX 0 -#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG 0x0148 -#define mmHDP_XDP_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 -#define mmHDP_XDP_MMHUB_ERROR 0x0149 -#define mmHDP_XDP_MMHUB_ERROR_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h deleted file mode 100644 index 586187576d70..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h +++ /dev/null @@ -1,601 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _hdp_4_0_SH_MASK_HEADER -#define _hdp_4_0_SH_MASK_HEADER - - -// addressBlock: hdp_hdpdec -//HDP_MMHUB_TLVL -#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 -#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 -#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 -#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc -#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 -#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L -#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L -#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L -#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L -#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L -//HDP_MMHUB_UNITID -#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 -#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 -#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 -#define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL -#define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L -#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L -//HDP_NONSURFACE_BASE -#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 -#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL -//HDP_NONSURFACE_INFO -#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 -#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 -#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L -#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L -//HDP_NONSURFACE_BASE_HI -#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 -#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL -//HDP_NONSURF_FLAGS -#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 -#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 -#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L -#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L -//HDP_NONSURF_FLAGS_CLR -#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 -#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 -#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L -#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L -//HDP_HOST_PATH_CNTL -#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 -#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 -#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d -#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e -#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f -#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L -#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L -#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L -#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L -#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L -#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L -//HDP_SW_SEMAPHORE -#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 -#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL -//HDP_DEBUG0 -#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 -#define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL -//HDP_LAST_SURFACE_HIT -#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 -#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L -//HDP_READ_CACHE_INVALIDATE -#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 -#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L -//HDP_OUTSTANDING_REQ -#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 -#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 -#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL -#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L -//HDP_MISC_CNTL -#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 -#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 -#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 -#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 -#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb -#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 -#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 -#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 -#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 -#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a -#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b -#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c -#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d -#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e -#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L -#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL -#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L -#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L -#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L -#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L -#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L -#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L -#define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L -#define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L -#define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L -#define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L -#define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L -#define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L -//HDP_MEM_POWER_LS -#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 -#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 -#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L -#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L -//HDP_MMHUB_CNTL -#define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 -#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 -#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 -#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L -#define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L -#define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L -//HDP_EDC_CNT -#define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 -#define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 -#define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L -#define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL -//HDP_VERSION -#define HDP_VERSION__MINVER__SHIFT 0x0 -#define HDP_VERSION__MAJVER__SHIFT 0x8 -#define HDP_VERSION__REV__SHIFT 0x10 -#define HDP_VERSION__MINVER_MASK 0x000000FFL -#define HDP_VERSION__MAJVER_MASK 0x0000FF00L -#define HDP_VERSION__REV_MASK 0x00FF0000L -//HDP_CLK_CNTL -#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 -#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 -#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c -#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d -#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e -#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f -#define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL -#define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L -#define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L -#define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L -#define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L -#define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L -//HDP_MEMIO_CNTL -#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 -#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 -#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 -#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 -#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 -#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 -#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe -#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf -#define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 -#define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 -#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L -#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L -#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL -#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L -#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L -#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L -#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L -#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L -#define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L -#define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L -//HDP_MEMIO_ADDR -#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 -#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL -//HDP_MEMIO_STATUS -#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 -#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 -#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 -#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 -#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L -#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L -#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L -#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L -//HDP_MEMIO_WR_DATA -#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 -#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL -//HDP_MEMIO_RD_DATA -#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 -#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL -//HDP_XDP_DIRECT2HDP_FIRST -#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 -#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_FLUSH -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L -#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L -//HDP_XDP_D2H_BAR_UPDATE -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L -#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L -//HDP_XDP_D2H_RSVD_3 -#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_4 -#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_5 -#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_6 -#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_7 -#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_8 -#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_9 -#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_10 -#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_11 -#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_12 -#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_13 -#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_14 -#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_15 -#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_16 -#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_17 -#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_18 -#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_19 -#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_20 -#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_21 -#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_22 -#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_23 -#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_24 -#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_25 -#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_26 -#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_27 -#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_28 -#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_29 -#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_30 -#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_31 -#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_32 -#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_33 -#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_D2H_RSVD_34 -#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 -#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_DIRECT2HDP_LAST -#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 -#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL -//HDP_XDP_P2P_BAR_CFG -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL -#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L -//HDP_XDP_P2P_MBX_OFFSET -#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL -//HDP_XDP_P2P_MBX_ADDR0 -#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR1 -#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR2 -#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR3 -#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR4 -#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR5 -#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_P2P_MBX_ADDR6 -#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 -#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L -//HDP_XDP_HDP_MBX_MC_CFG -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L -#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L -//HDP_XDP_HDP_MC_CFG -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L -#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L -//HDP_XDP_HST_CFG -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 -#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L -#define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L -#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L -//HDP_XDP_HDP_IPH_CFG -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L -#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L -//HDP_XDP_P2P_BAR0 -#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR1 -#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR2 -#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR3 -#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR4 -#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR5 -#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR6 -#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L -//HDP_XDP_P2P_BAR7 -#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 -#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 -#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 -#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL -#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L -#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L -//HDP_XDP_FLUSH_ARMED_STS -#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 -#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL -//HDP_XDP_FLUSH_CNTR0_STS -#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 -#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL -//HDP_XDP_BUSY_STS -#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 -#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL -//HDP_XDP_STICKY -#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 -#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 -#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL -#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L -//HDP_XDP_CHKN -#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 -#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 -#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 -#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 -#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL -#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L -#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L -#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L -//HDP_XDP_BARS_ADDR_39_36 -#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 -#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 -#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 -#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc -#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 -#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 -#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 -#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c -#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL -#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L -#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L -#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L -#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L -#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L -#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L -#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L -//HDP_XDP_MC_VM_FB_LOCATION_BASE -#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 -#define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL -//HDP_XDP_GPU_IOV_VIOLATION_LOG -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//HDP_XDP_MMHUB_ERROR -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L -#define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L -#define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L -#define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L -#define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L -#define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L -#define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h deleted file mode 100644 index 98ba7d832423..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mp_9_0_DEFAULT_HEADER -#define _mp_9_0_DEFAULT_HEADER - - -// addressBlock: mp_SmuMp0_SmnDec -#define mmMP0_SMN_C2PMSG_32_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_33_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_34_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_35_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_36_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_37_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_38_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_39_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_40_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_41_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_42_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_43_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_44_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_45_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_46_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_47_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_48_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_49_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_50_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_51_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_52_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_53_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_54_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_55_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_56_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_57_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_58_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_59_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_60_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_61_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_62_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_63_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_64_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_65_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_66_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_67_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_68_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_69_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_70_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_71_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_72_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_73_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_74_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_75_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_76_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_77_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_78_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_79_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_80_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_81_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_82_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_83_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_84_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_85_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_86_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_87_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_88_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_89_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_90_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_91_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_92_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_93_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_94_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_95_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_96_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_97_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_98_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_99_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_100_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_101_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_102_DEFAULT 0x00000000 -#define mmMP0_SMN_C2PMSG_103_DEFAULT 0x00000000 -#define mmMP0_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmMP0_SMN_IH_CREDIT_DEFAULT 0x00000000 -#define mmMP0_SMN_IH_SW_INT_DEFAULT 0x00000000 -#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 - - -// addressBlock: mp_SmuMp1_SmnDec -#define mmMP1_SMN_ACP2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_DC2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_UVD2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_VCE2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_RLC2MP_RESP_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_32_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_33_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_34_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_35_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_36_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_37_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_38_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_39_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_40_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_41_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_42_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_43_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_44_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_45_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_46_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_47_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_48_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_49_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_50_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_51_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_52_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_53_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_54_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_55_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_56_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_57_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_58_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_59_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_60_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_61_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_62_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_63_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_64_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_65_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_66_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_67_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_68_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_69_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_70_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_71_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_72_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_73_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_74_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_75_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_76_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_77_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_78_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_79_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_80_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_81_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_82_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_83_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_84_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_85_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_86_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_87_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_88_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_89_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_90_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_91_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_92_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_93_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_94_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_95_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_96_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_97_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_98_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_99_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_100_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_101_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_102_DEFAULT 0x00000000 -#define mmMP1_SMN_C2PMSG_103_DEFAULT 0x00000000 -#define mmMP1_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmMP1_SMN_IH_CREDIT_DEFAULT 0x00000000 -#define mmMP1_SMN_IH_SW_INT_DEFAULT 0x00000000 -#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 -#define mmMP1_SMN_FPS_CNT_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH0_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH1_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH2_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH3_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH4_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH5_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH6_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH7_DEFAULT 0x00000000 -#define mmMP1_SMN_EXT_SCRATCH8_DEFAULT 0x00000000 - - -// addressBlock: mp_SmuMp1Pub_CruDec -#define mmMP1_SMN_PUB_CTRL_DEFAULT 0x00000001 -#define smnMP1_FIRMWARE_FLAGS_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH0_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH1_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH2_DEFAULT 0x00000000 -#define smnMP1_PUB_SCRATCH3_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_0_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_1_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_2_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_3_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_4_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_5_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_6_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_7_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_8_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_9_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_10_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_11_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_12_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_13_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_14_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_15_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_16_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_17_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_18_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_19_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_20_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_21_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_22_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_23_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_24_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_25_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_26_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_27_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_28_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_29_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_30_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_31_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_0_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_1_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_2_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_3_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_INTEN_DEFAULT 0x00000000 -#define smnMP1_P2CMSG_INTSTS_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_0_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_1_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_2_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_3_DEFAULT 0x00000000 -#define smnMP1_P2SMSG_INTSTS_DEFAULT 0x00000000 -#define smnMP1_S2PMSG_0_DEFAULT 0x00000000 -#define smnMP1_ACP2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_DC2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_UVD2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_VCE2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_RLC2MP_RESP_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_32_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_33_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_34_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_35_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_36_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_37_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_38_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_39_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_40_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_41_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_42_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_43_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_44_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_45_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_46_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_47_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_48_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_49_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_50_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_51_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_52_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_53_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_54_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_55_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_56_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_57_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_58_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_59_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_60_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_61_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_62_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_63_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_64_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_65_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_66_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_67_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_68_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_69_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_70_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_71_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_72_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_73_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_74_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_75_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_76_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_77_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_78_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_79_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_80_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_81_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_82_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_83_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_84_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_85_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_86_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_87_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_88_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_89_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_90_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_91_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_92_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_93_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_94_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_95_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_96_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_97_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_98_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_99_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_100_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_101_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_102_DEFAULT 0x00000000 -#define smnMP1_C2PMSG_103_DEFAULT 0x00000000 -#define smnMP1_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define smnMP1_IH_CREDIT_DEFAULT 0x00000000 -#define smnMP1_IH_SW_INT_DEFAULT 0x00000000 -#define smnMP1_IH_SW_INT_CTRL_DEFAULT 0x00000000 -#define smnMP1_FPS_CNT_DEFAULT 0x00000000 -#define smnMP1_PUB_CTRL_DEFAULT 0x00000001 -#define smnMP1_EXT_SCRATCH0_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH1_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH2_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH3_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH4_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH5_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH6_DEFAULT 0x00000000 -#define smnMP1_EXT_SCRATCH7_DEFAULT 0x00000000 - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h deleted file mode 100644 index 621e8809c867..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h +++ /dev/null @@ -1,375 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mp_9_0_OFFSET_HEADER -#define _mp_9_0_OFFSET_HEADER - - - -// addressBlock: mp_SmuMp0_SmnDec -// base address: 0x0 -#define mmMP0_SMN_C2PMSG_32 0x0060 -#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_33 0x0061 -#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_34 0x0062 -#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_35 0x0063 -#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_36 0x0064 -#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_37 0x0065 -#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_38 0x0066 -#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_39 0x0067 -#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_40 0x0068 -#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_41 0x0069 -#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_42 0x006a -#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_43 0x006b -#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_44 0x006c -#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_45 0x006d -#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_46 0x006e -#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_47 0x006f -#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_48 0x0070 -#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_49 0x0071 -#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_50 0x0072 -#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_51 0x0073 -#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_52 0x0074 -#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_53 0x0075 -#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_54 0x0076 -#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_55 0x0077 -#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_56 0x0078 -#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_57 0x0079 -#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_58 0x007a -#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_59 0x007b -#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_60 0x007c -#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_61 0x007d -#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_62 0x007e -#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_63 0x007f -#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_64 0x0080 -#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_65 0x0081 -#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_66 0x0082 -#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_67 0x0083 -#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_68 0x0084 -#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_69 0x0085 -#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_70 0x0086 -#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_71 0x0087 -#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_72 0x0088 -#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_73 0x0089 -#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_74 0x008a -#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_75 0x008b -#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_76 0x008c -#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_77 0x008d -#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_78 0x008e -#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_79 0x008f -#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_80 0x0090 -#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_81 0x0091 -#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_82 0x0092 -#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_83 0x0093 -#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_84 0x0094 -#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_85 0x0095 -#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_86 0x0096 -#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_87 0x0097 -#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_88 0x0098 -#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_89 0x0099 -#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_90 0x009a -#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_91 0x009b -#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_92 0x009c -#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_93 0x009d -#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_94 0x009e -#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_95 0x009f -#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_96 0x00a0 -#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_97 0x00a1 -#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_98 0x00a2 -#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_99 0x00a3 -#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_100 0x00a4 -#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_101 0x00a5 -#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_102 0x00a6 -#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 -#define mmMP0_SMN_C2PMSG_103 0x00a7 -#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 -#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 -#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmMP0_SMN_IH_CREDIT 0x00c1 -#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 -#define mmMP0_SMN_IH_SW_INT 0x00c2 -#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 -#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 -#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 - - -// addressBlock: mp_SmuMp1_SmnDec -// base address: 0x0 -#define mmMP1_SMN_ACP2MP_RESP 0x0240 -#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_DC2MP_RESP 0x0241 -#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_UVD2MP_RESP 0x0242 -#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_VCE2MP_RESP 0x0243 -#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_RLC2MP_RESP 0x0244 -#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_32 0x0260 -#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_33 0x0261 -#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_34 0x0262 -#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_35 0x0263 -#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_36 0x0264 -#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_37 0x0265 -#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_38 0x0266 -#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_39 0x0267 -#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_40 0x0268 -#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_41 0x0269 -#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_42 0x026a -#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_43 0x026b -#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_44 0x026c -#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_45 0x026d -#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_46 0x026e -#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_47 0x026f -#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_48 0x0270 -#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_49 0x0271 -#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_50 0x0272 -#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_51 0x0273 -#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_52 0x0274 -#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_53 0x0275 -#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_54 0x0276 -#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_55 0x0277 -#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_56 0x0278 -#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_57 0x0279 -#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_58 0x027a -#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_59 0x027b -#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_60 0x027c -#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_61 0x027d -#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_62 0x027e -#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_63 0x027f -#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_64 0x0280 -#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_65 0x0281 -#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_66 0x0282 -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_67 0x0283 -#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_68 0x0284 -#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_69 0x0285 -#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_70 0x0286 -#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_71 0x0287 -#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_72 0x0288 -#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_73 0x0289 -#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_74 0x028a -#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_75 0x028b -#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_76 0x028c -#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_77 0x028d -#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_78 0x028e -#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_79 0x028f -#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_80 0x0290 -#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_81 0x0291 -#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_82 0x0292 -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_83 0x0293 -#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_84 0x0294 -#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_85 0x0295 -#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_86 0x0296 -#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_87 0x0297 -#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_88 0x0298 -#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_89 0x0299 -#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_90 0x029a -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_91 0x029b -#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_92 0x029c -#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_93 0x029d -#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_94 0x029e -#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_95 0x029f -#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_96 0x02a0 -#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_97 0x02a1 -#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_98 0x02a2 -#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_99 0x02a3 -#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_100 0x02a4 -#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_101 0x02a5 -#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_102 0x02a6 -#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 -#define mmMP1_SMN_C2PMSG_103 0x02a7 -#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 -#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 -#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmMP1_SMN_IH_CREDIT 0x02c1 -#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 -#define mmMP1_SMN_IH_SW_INT 0x02c2 -#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 -#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 -#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 -#define mmMP1_SMN_FPS_CNT 0x02c4 -#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 -#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 -#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 -#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 -#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 -#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 -#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 -#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 -#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 -#define mmMP1_SMN_EXT_SCRATCH8 0x03c8 -#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 - - -// addressBlock: mp_SmuMp1Pub_CruDec -// base address: 0x0 -#define mmMP1_SMN_PUB_CTRL 0x02c5 -#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 - - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h deleted file mode 100644 index ae7b51870322..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h +++ /dev/null @@ -1,1463 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _mp_9_0_SH_MASK_HEADER -#define _mp_9_0_SH_MASK_HEADER - - -// addressBlock: mp_SmuMp0_SmnDec -//MP0_SMN_C2PMSG_32 -#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_33 -#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_34 -#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_35 -#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_36 -#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_37 -#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_38 -#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_39 -#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_40 -#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_41 -#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_42 -#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_43 -#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_44 -#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_45 -#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_46 -#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_47 -#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_48 -#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_49 -#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_50 -#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_51 -#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_52 -#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_53 -#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_54 -#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_55 -#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_56 -#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_57 -#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_58 -#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_59 -#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_60 -#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_61 -#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_62 -#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_63 -#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_64 -#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_65 -#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_66 -#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_67 -#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_68 -#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_69 -#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_70 -#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_71 -#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_72 -#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_73 -#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_74 -#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_75 -#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_76 -#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_77 -#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_78 -#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_79 -#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_80 -#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_81 -#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_82 -#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_83 -#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_84 -#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_85 -#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_86 -#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_87 -#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_88 -#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_89 -#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_90 -#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_91 -#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_92 -#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_93 -#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_94 -#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_95 -#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_96 -#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_97 -#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_98 -#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_99 -#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_100 -#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_101 -#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_102 -#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_C2PMSG_103 -#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP0_SMN_ACTIVE_FCN_ID -#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP0_SMN_IH_CREDIT -#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP0_SMN_IH_SW_INT -#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 -#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 -#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L -#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL -//MP0_SMN_IH_SW_INT_CTRL -#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 -#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 -#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L -#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L - - -// addressBlock: mp_SmuMp1_SmnDec -//MP1_SMN_ACP2MP_RESP -#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_DC2MP_RESP -#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_UVD2MP_RESP -#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_VCE2MP_RESP -#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_RLC2MP_RESP -#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_32 -#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_33 -#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_34 -#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_35 -#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_36 -#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_37 -#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_38 -#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_39 -#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_40 -#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_41 -#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_42 -#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_43 -#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_44 -#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_45 -#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_46 -#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_47 -#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_48 -#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_49 -#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_50 -#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_51 -#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_52 -#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_53 -#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_54 -#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_55 -#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_56 -#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_57 -#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_58 -#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_59 -#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_60 -#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_61 -#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_62 -#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_63 -#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_64 -#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_65 -#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_66 -#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_67 -#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_68 -#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_69 -#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_70 -#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_71 -#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_72 -#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_73 -#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_74 -#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_75 -#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_76 -#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_77 -#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_78 -#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_79 -#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_80 -#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_81 -#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_82 -#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_83 -#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_84 -#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_85 -#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_86 -#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_87 -#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_88 -#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_89 -#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_90 -#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_91 -#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_92 -#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_93 -#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_94 -#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_95 -#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_96 -#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_97 -#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_98 -#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_99 -#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_100 -#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_101 -#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_102 -#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_C2PMSG_103 -#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP1_SMN_ACTIVE_FCN_ID -#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP1_SMN_IH_CREDIT -#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP1_SMN_IH_SW_INT -#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 -#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 -#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L -#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL -//MP1_SMN_IH_SW_INT_CTRL -#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 -#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 -#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L -#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L -//MP1_SMN_FPS_CNT -#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 -#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH0 -#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH1 -#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH2 -#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH3 -#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH4 -#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH5 -#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH6 -#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH7 -#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL -//MP1_SMN_EXT_SCRATCH8 -#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 -#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL - - - - -// addressBlock: mp_SmuMp0Pub_CruDec -//MP0_SOC_INFO -#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 -#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 -#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L -#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL -//MP0_PUB_SCRATCH0 -#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP0_PUB_SCRATCH1 -#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP0_PUB_SCRATCH2 -#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP0_PUB_SCRATCH3 -#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 -#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP0_FW_INTF -#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 -#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L -//MP0_C2PMSG_0 -#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_1 -#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_2 -#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_3 -#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_4 -#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_5 -#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_6 -#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_7 -#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_8 -#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_9 -#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_10 -#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_11 -#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_12 -#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_13 -#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_14 -#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_15 -#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_16 -#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_17 -#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_18 -#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_19 -#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_20 -#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_21 -#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_22 -#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_23 -#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_24 -#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_25 -#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_26 -#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_27 -#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_28 -#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_29 -#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_30 -#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_31 -#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_0 -#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_1 -#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_2 -#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_3 -#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 -#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2CMSG_INTEN -#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 -#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL -//MP0_P2CMSG_INTSTS -#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP0_C2PMSG_ATTR_0 -#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_1 -#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_2 -#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_3 -#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_4 -#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_5 -#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL -//MP0_C2PMSG_ATTR_6 -#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 -#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL -//MP0_P2CMSG_ATTR -#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 -#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL -//MP0_P2SMSG_0 -#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_1 -#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_2 -#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_3 -#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 -#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP0_P2SMSG_ATTR -#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 -#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL -//MP0_S2PMSG_ATTR -#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 -#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L -//MP0_P2SMSG_INTSTS -#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP0_S2PMSG_0 -#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 -#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_32 -#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_33 -#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_34 -#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_35 -#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_36 -#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_37 -#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_38 -#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_39 -#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_40 -#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_41 -#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_42 -#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_43 -#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_44 -#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_45 -#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_46 -#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_47 -#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_48 -#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_49 -#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_50 -#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_51 -#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_52 -#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_53 -#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_54 -#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_55 -#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_56 -#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_57 -#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_58 -#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_59 -#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_60 -#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_61 -#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_62 -#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_63 -#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_64 -#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_65 -#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_66 -#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_67 -#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_68 -#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_69 -#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_70 -#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_71 -#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_72 -#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_73 -#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_74 -#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_75 -#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_76 -#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_77 -#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_78 -#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_79 -#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_80 -#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_81 -#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_82 -#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_83 -#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_84 -#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_85 -#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_86 -#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_87 -#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_88 -#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_89 -#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_90 -#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_91 -#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_92 -#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_93 -#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_94 -#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_95 -#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_96 -#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_97 -#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_98 -#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_99 -#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_100 -#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_101 -#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_102 -#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP0_C2PMSG_103 -#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP0_ACTIVE_FCN_ID -#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP0_IH_CREDIT -#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP0_IH_SW_INT -#define MP0_IH_SW_INT__ID__SHIFT 0x0 -#define MP0_IH_SW_INT__VALID__SHIFT 0x8 -#define MP0_IH_SW_INT__ID_MASK 0x000000FFL -#define MP0_IH_SW_INT__VALID_MASK 0x00000100L -//MP0_IH_SW_INT_CTRL -#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 -#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 -#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L -#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L - - -//CGTT_DRM_CLK_CTRL0 -#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 -#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 -#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f -#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL -#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L -#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L -#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L -#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L -//DRM_LIGHT_SLEEP_CTRL -#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 -#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L - - -// addressBlock: mp_SmuMp1Pub_CruDec -//MP1_SMN_PUB_CTRL -#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 -#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L -//MP1_FIRMWARE_FLAGS -#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 -#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 -#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L -#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL -//MP1_PUB_SCRATCH0 -#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP1_PUB_SCRATCH1 -#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP1_PUB_SCRATCH2 -#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP1_PUB_SCRATCH3 -#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 -#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP1_C2PMSG_0 -#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_1 -#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_2 -#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_3 -#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_4 -#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_5 -#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_6 -#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_7 -#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_8 -#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_9 -#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_10 -#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_11 -#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_12 -#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_13 -#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_14 -#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_15 -#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_16 -#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_17 -#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_18 -#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_19 -#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_20 -#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_21 -#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_22 -#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_23 -#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_24 -#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_25 -#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_26 -#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_27 -#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_28 -#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_29 -#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_30 -#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_31 -#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_0 -#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_1 -#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_2 -#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_3 -#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 -#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2CMSG_INTEN -#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 -#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL -//MP1_P2CMSG_INTSTS -#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP1_P2SMSG_0 -#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_1 -#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_2 -#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_3 -#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 -#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL -//MP1_P2SMSG_INTSTS -#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 -#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 -#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 -#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 -#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L -#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L -#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L -#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L -//MP1_S2PMSG_0 -#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 -#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL -//MP1_ACP2MP_RESP -#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_DC2MP_RESP -#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_UVD2MP_RESP -#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_VCE2MP_RESP -#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_RLC2MP_RESP -#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 -#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_32 -#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_33 -#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_34 -#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_35 -#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_36 -#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_37 -#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_38 -#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_39 -#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_40 -#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_41 -#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_42 -#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_43 -#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_44 -#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_45 -#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_46 -#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_47 -#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_48 -#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_49 -#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_50 -#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_51 -#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_52 -#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_53 -#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_54 -#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_55 -#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_56 -#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_57 -#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_58 -#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_59 -#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_60 -#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_61 -#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_62 -#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_63 -#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_64 -#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_65 -#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_66 -#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_67 -#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_68 -#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_69 -#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_70 -#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_71 -#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_72 -#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_73 -#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_74 -#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_75 -#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_76 -#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_77 -#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_78 -#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_79 -#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_80 -#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_81 -#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_82 -#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_83 -#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_84 -#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_85 -#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_86 -#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_87 -#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_88 -#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_89 -#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_90 -#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_91 -#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_92 -#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_93 -#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_94 -#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_95 -#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_96 -#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_97 -#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_98 -#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_99 -#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_100 -#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_101 -#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_102 -#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL -//MP1_C2PMSG_103 -#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 -#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL -//MP1_ACTIVE_FCN_ID -#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//MP1_IH_CREDIT -#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 -#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 -#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L -#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L -//MP1_IH_SW_INT -#define MP1_IH_SW_INT__ID__SHIFT 0x0 -#define MP1_IH_SW_INT__VALID__SHIFT 0x8 -#define MP1_IH_SW_INT__ID_MASK 0x000000FFL -#define MP1_IH_SW_INT__VALID_MASK 0x00000100L -//MP1_IH_SW_INT_CTRL -#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 -#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 -#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L -#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L -//MP1_FPS_CNT -#define MP1_FPS_CNT__COUNT__SHIFT 0x0 -#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL -//MP1_PUB_CTRL -#define MP1_PUB_CTRL__RESET__SHIFT 0x0 -#define MP1_PUB_CTRL__RESET_MASK 0x00000001L -//MP1_EXT_SCRATCH0 -#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH1 -#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH2 -#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH3 -#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH4 -#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH5 -#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH6 -#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL -//MP1_EXT_SCRATCH7 -#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 -#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL - - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h deleted file mode 100644 index daa7eaef01b8..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h +++ /dev/null @@ -1,1271 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _nbif_6_1_DEFAULT_HEADER -#define _nbif_6_1_DEFAULT_HEADER - - -// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp -// base address: 0x0 -#define cfgVENDOR_ID_DEFAULT 0x00000000 -#define cfgDEVICE_ID_DEFAULT 0x00000000 -#define cfgCOMMAND_DEFAULT 0x00000000 -#define cfgSTATUS_DEFAULT 0x00000000 -#define cfgREVISION_ID_DEFAULT 0x00000000 -#define cfgPROG_INTERFACE_DEFAULT 0x00000000 -#define cfgSUB_CLASS_DEFAULT 0x00000000 -#define cfgBASE_CLASS_DEFAULT 0x00000000 -#define cfgCACHE_LINE_DEFAULT 0x00000000 -#define cfgLATENCY_DEFAULT 0x00000000 -#define cfgHEADER_DEFAULT 0x00000000 -#define cfgBIST_DEFAULT 0x00000000 -#define cfgBASE_ADDR_1_DEFAULT 0x00000000 -#define cfgBASE_ADDR_2_DEFAULT 0x00000000 -#define cfgBASE_ADDR_3_DEFAULT 0x00000000 -#define cfgBASE_ADDR_4_DEFAULT 0x00000000 -#define cfgBASE_ADDR_5_DEFAULT 0x00000000 -#define cfgBASE_ADDR_6_DEFAULT 0x00000000 -#define cfgADAPTER_ID_DEFAULT 0x00000000 -#define cfgROM_BASE_ADDR_DEFAULT 0x00000000 -#define cfgCAP_PTR_DEFAULT 0x00000000 -#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff -#define cfgINTERRUPT_PIN_DEFAULT 0x00000000 -#define cfgMIN_GRANT_DEFAULT 0x00000000 -#define cfgMAX_LATENCY_DEFAULT 0x00000000 -#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 -#define cfgADAPTER_ID_W_DEFAULT 0x00000000 -#define cfgPMI_CAP_LIST_DEFAULT 0x00000000 -#define cfgPMI_CAP_DEFAULT 0x00000000 -#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 -#define cfgPCIE_CAP_DEFAULT 0x00000002 -#define cfgDEVICE_CAP_DEFAULT 0x10000000 -#define cfgDEVICE_CNTL_DEFAULT 0x00002810 -#define cfgDEVICE_STATUS_DEFAULT 0x00000000 -#define cfgLINK_CAP_DEFAULT 0x00011c03 -#define cfgLINK_CNTL_DEFAULT 0x00000000 -#define cfgLINK_STATUS_DEFAULT 0x00000001 -#define cfgDEVICE_CAP2_DEFAULT 0x00000000 -#define cfgDEVICE_CNTL2_DEFAULT 0x00000000 -#define cfgDEVICE_STATUS2_DEFAULT 0x00000000 -#define cfgLINK_CAP2_DEFAULT 0x0000000e -#define cfgLINK_CNTL2_DEFAULT 0x00000003 -#define cfgLINK_STATUS2_DEFAULT 0x00000000 -#define cfgSLOT_CAP2_DEFAULT 0x00000000 -#define cfgSLOT_CNTL2_DEFAULT 0x00000000 -#define cfgSLOT_STATUS2_DEFAULT 0x00000000 -#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 -#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 -#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 -#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 -#define cfgMSI_MSG_DATA_DEFAULT 0x00000000 -#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 -#define cfgMSI_MASK_DEFAULT 0x00000000 -#define cfgMSI_PENDING_DEFAULT 0x00000000 -#define cfgMSI_MASK_64_DEFAULT 0x00000000 -#define cfgMSI_PENDING_64_DEFAULT 0x00000000 -#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 -#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 -#define cfgMSIX_TABLE_DEFAULT 0x00000000 -#define cfgMSIX_PBA_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 -#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 -#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 -#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 -#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 -#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe -#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 -#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 -#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 -#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 -#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 -#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 -#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 -#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 -#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 -#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 -#define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 -#define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 -#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 -#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 -#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 -#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 -#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 -#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 -#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 -#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 -#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 -#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 -#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 -#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 -#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 -#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 -#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 -#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 -#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 -#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 -#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 -#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 -#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 -#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 -#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 -#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 -#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 -#define cfgPCIE_MC_CAP_DEFAULT 0x00000000 -#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 -#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 -#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 -#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 -#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 -#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 -#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 -#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 - - -// addressBlock: bif_cfg_dev0_swds_bifcfgdecp -// base address: 0x0 -#define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 -#define mmIO_BASE_LIMIT_DEFAULT 0x00000000 -#define mmSECONDARY_STATUS_DEFAULT 0x00000000 -#define mmMEM_BASE_LIMIT_DEFAULT 0x00000000 -#define mmPREF_BASE_LIMIT_DEFAULT 0x00000000 -#define mmPREF_BASE_UPPER_DEFAULT 0x00000000 -#define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000 -#define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000 -#define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000 -#define mmSLOT_CAP_DEFAULT 0x00000000 -#define mmSLOT_CNTL_DEFAULT 0x00000000 -#define mmSLOT_STATUS_DEFAULT 0x00000000 -#define mmSSID_CAP_LIST_DEFAULT 0x00000000 -#define mmSSID_CAP_DEFAULT 0x00000000 - - -// addressBlock: rcc_shadow_reg_shadowdec -// base address: 0x0 -#define ixSHADOW_COMMAND_DEFAULT 0x00000000 -#define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 -#define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 -#define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 -#define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 -#define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 -#define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 -#define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 -#define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 -#define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 -#define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 -#define ixSUC_INDEX_DEFAULT 0x00000000 -#define ixSUC_DATA_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_SUMDEC -// base address: 0x0 -#define ixSUM_INDEX_DEFAULT 0x00000000 -#define ixSUM_DATA_DEFAULT 0x00000000 - - -// addressBlock: gdc_GDCDEC -// base address: 0x1400000 -#define mmA2S_CNTL_CL0_DEFAULT 0x00280540 -#define mmA2S_CNTL_CL1_DEFAULT 0x00282540 -#define mmA2S_CNTL_CL2_DEFAULT 0x002825a0 -#define mmA2S_CNTL_CL3_DEFAULT 0x00282550 -#define mmA2S_CNTL_CL4_DEFAULT 0x00282550 -#define mmA2S_CNTL_SW0_DEFAULT 0x08080005 -#define mmA2S_CNTL_SW1_DEFAULT 0x08080205 -#define mmA2S_CNTL_SW2_DEFAULT 0x08080200 -#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080 -#define mmA2S_MISC_CNTL_DEFAULT 0x00000003 -#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f -#define mmNGDC_RESERVED_0_DEFAULT 0x00000000 -#define mmNGDC_RESERVED_1_DEFAULT 0x00000000 -#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 -#define mmS2A_MISC_CNTL_DEFAULT 0x00000000 -#define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006 -#define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006 - - -// addressBlock: nbif_sion_SIONDEC -// base address: 0x1400000 -#define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 -#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 -#define ixSION_CNTL_REG0_DEFAULT 0x00000000 -#define ixSION_CNTL_REG1_DEFAULT 0x00000000 - - -// addressBlock: syshub_mmreg_direct_syshubdirect -// base address: 0x1400000 -#define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 -#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 -#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000 -#define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000 -#define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100 -#define ixSYSHUB_SCRATCH_DEFAULT 0x00000040 -#define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 -#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 -#define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 - - -// addressBlock: gdc_ras_gdc_ras_regblk -// base address: 0x1400000 -#define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000 -#define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000 - - -// addressBlock: gdc_rst_GDCRST_DEC -// base address: 0x1400000 -#define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000 -#define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000 -#define ixSHUB_LINK_RESET_DEFAULT 0x00000000 -#define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 -#define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b -#define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 -#define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_SYSDEC -// base address: 0x0 -#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 -#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 -#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 -#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 -#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 -#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 -#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 -#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 -#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_SYSPFVFDEC -// base address: 0x0 -#define mmMM_INDEX_DEFAULT 0x00000000 -#define mmMM_DATA_DEFAULT 0x00000000 -#define mmMM_INDEX_HI_DEFAULT 0x00000000 -#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 -#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 -#define mmPCIE_INDEX_DEFAULT 0x00000000 -#define mmPCIE_DATA_DEFAULT 0x00000000 -#define mmPCIE_INDEX2_DEFAULT 0x00000000 -#define mmPCIE_DATA2_DEFAULT 0x00000000 - - -// addressBlock: rcc_dwn_BIFDEC1 -// base address: 0x0 -#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 -#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 -#define mmDN_PCIE_CNTL_DEFAULT 0x00000000 -#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 -#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 -#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 -#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 -#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001 -#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 -#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 - - -// addressBlock: rcc_dwnp_BIFDEC1 -// base address: 0x0 -#define mmPCIEP_RESERVED_DEFAULT 0x00000000 -#define mmPCIEP_SCRATCH_DEFAULT 0x00000000 -#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 -#define mmPCIE_RX_CNTL_DEFAULT 0x00000000 -#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 -#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 -#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 -#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 - - -// addressBlock: rcc_ep_BIFDEC1 -// base address: 0x0 -#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 -#define mmEP_PCIE_CNTL_DEFAULT 0x00000100 -#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 -#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 -#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 -#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 -#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 -#define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774 -#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468 -#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 -#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 -#define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000 -#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 -#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 -#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a -#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 -#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 -#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 -#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 -#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 -#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 -#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_BIFDEC1 -// base address: 0x0 -#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 -#define mmBUS_CNTL_DEFAULT 0x00000000 -#define mmBIF_SCRATCH0_DEFAULT 0x00000000 -#define mmBIF_SCRATCH1_DEFAULT 0x00000000 -#define mmBX_RESET_EN_DEFAULT 0x00010003 -#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 -#define mmBX_RESET_CNTL_DEFAULT 0x00000000 -#define mmINTERRUPT_CNTL_DEFAULT 0x00000010 -#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 -#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 -#define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000 -#define mmBIF_CLK_CTRL_DEFAULT 0x00000000 -#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 -#define mmBIF_SLVARB_MODE_DEFAULT 0x00000000 -#define mmBIF_FB_EN_DEFAULT 0x00000000 -#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f -#define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 -#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 -#define mmBACO_CNTL_DEFAULT 0x00000000 -#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 -#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100 -#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 -#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400 -#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100 -#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 -#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 -#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc -#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 -#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc -#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 -#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc -#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 -#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc -#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 -#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc -#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 -#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc -#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 -#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 -#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 -#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc -#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 -#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c -#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c -#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 -#define mmBIF_RB_CNTL_DEFAULT 0x00000000 -#define mmBIF_RB_BASE_DEFAULT 0x00000000 -#define mmBIF_RB_RPTR_DEFAULT 0x00000000 -#define mmBIF_RB_WPTR_DEFAULT 0x00000000 -#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmMAILBOX_INDEX_DEFAULT 0x00000000 -#define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000 -#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 -#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 -#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 -#define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020 -#define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000 -#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 -#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 -#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 -#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 - - -// addressBlock: rcc_pf_0_BIFDEC1 -// base address: 0x0 -#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 -#define mmRCC_RESET_EN_DEFAULT 0x00008000 -#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 -#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 -#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 -#define mmRCC_BUS_CNTL_DEFAULT 0x00000000 -#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 -#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 -#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 -#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 -#define mmRCC_XDMA_LO_DEFAULT 0x00000000 -#define mmRCC_XDMA_HI_DEFAULT 0x00000000 -#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 -#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 -#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 -#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 -#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 -#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 -#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 -#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 -#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 -#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000 -#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 -#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 -#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 - - -// addressBlock: rcc_pf_0_BIFDEC2 -// base address: 0x0 -#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 -#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 -#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 -#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 -#define mmGFXMSIX_PBA_DEFAULT 0x00000000 - - -// addressBlock: rcc_strap_BIFDEC1 -// base address: 0x0 -#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 -#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e -#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 -#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 -#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 -#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 -#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 -#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 -#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 -#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 -#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 -#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 -#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 -#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 -#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 -#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 -#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 -#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 - - -// addressBlock: bif_bx_pf_BIFPFVFDEC1 -// base address: 0x0 -#define mmBIF_BME_STATUS_DEFAULT 0x00000000 -#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 -#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 -#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 -#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 -#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 -#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 -#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 -#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 -#define mmMAILBOX_CONTROL_DEFAULT 0x00000000 -#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 -#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 - - -// addressBlock: rcc_pf_0_BIFPFVFDEC1 -// base address: 0x0 -#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 -#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 -#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 -#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 - - -// addressBlock: syshub_mmreg_ind_syshubdec -// base address: 0x0 -#define mmSYSHUB_INDEX_DEFAULT 0x00000000 -#define mmSYSHUB_DATA_DEFAULT 0x00000000 - - -// addressBlock: rcc_strap_rcc_strap_internal -// base address: 0x10100000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000 -#define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000 - - -// addressBlock: bif_rst_bif_rst_regblk -// base address: 0x10100000 -#define ixHARD_RST_CTRL_DEFAULT 0xb0000055 -#define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 -#define ixSELF_SOFT_RST_DEFAULT 0x00000000 -#define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9 -#define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644 -#define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 -#define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900 -#define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000 -#define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9 -#define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 -#define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000 -#define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff -#define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000 -#define ixBIF_PF_FLR_RST_DEFAULT 0x00000000 -#define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 -#define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b -#define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 - - -// addressBlock: bif_misc_bif_misc_regblk -// base address: 0x10100000 -#define ixMISC_SCRATCH_DEFAULT 0x00000000 -#define ixINTR_LINE_POLARITY_DEFAULT 0x00000000 -#define ixINTR_LINE_ENABLE_DEFAULT 0x00000000 -#define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf -#define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004 -#define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004 -#define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000 -#define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 -#define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 -#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 -#define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080 -#define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 -#define ixSMN_MST_CNTL0_DEFAULT 0x00000001 -#define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000 -#define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 -#define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 -#define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa -#define ixBIFC_THT_CNTL_DEFAULT 0x00000222 -#define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000 -#define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0 -#define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 -#define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf -#define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 -#define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 -#define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 -#define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000 -#define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000 -#define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f -#define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 - - -// addressBlock: bif_ras_bif_ras_regblk -// base address: 0x10100000 -#define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000 -#define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000 -#define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000 -#define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 -#define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 -#define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 - - -// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC -// base address: 0x10134000 -#define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000 -#define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 -#define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 -#define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 - - -// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC -// base address: 0x10134200 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 - - -// addressBlock: pciemsix_amdgfx_MSIXTDEC -// base address: 0x10170000 -#define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 -#define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 - - -// addressBlock: pciemsix_amdgfx_MSIXPDEC -// base address: 0x10171000 -#define ixPCIEMSIX_PBA_DEFAULT 0x00000000 - - -// addressBlock: syshub_mmreg_ind_syshubind -// base address: 0x0 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 -#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 -#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h deleted file mode 100644 index 1fddd0f5aaa2..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _osssys_4_0_DEFAULT_HEADER -#define _osssys_4_0_DEFAULT_HEADER - - -// addressBlock: osssys_osssysdec -#define mmIH_VMID_0_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_1_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_2_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_3_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_4_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_5_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_6_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_7_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_8_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_9_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_10_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_11_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_12_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_13_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_14_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_15_LUT_DEFAULT 0x00000000 -#define mmIH_VMID_0_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_1_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_2_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_3_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_4_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_5_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_6_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_7_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_8_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_9_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_10_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_11_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_12_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_13_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_14_LUT_MM_DEFAULT 0x00000000 -#define mmIH_VMID_15_LUT_MM_DEFAULT 0x00000000 -#define mmIH_COOKIE_0_DEFAULT 0x00000000 -#define mmIH_COOKIE_1_DEFAULT 0x00000000 -#define mmIH_COOKIE_2_DEFAULT 0x00000000 -#define mmIH_COOKIE_3_DEFAULT 0x00000000 -#define mmIH_COOKIE_4_DEFAULT 0x00000000 -#define mmIH_COOKIE_5_DEFAULT 0x00000000 -#define mmIH_COOKIE_6_DEFAULT 0x00000000 -#define mmIH_COOKIE_7_DEFAULT 0x00000000 -#define mmIH_REGISTER_LAST_PART0_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_0_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_1_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_2_DEFAULT 0x00000000 -#define mmSEM_REQ_INPUT_3_DEFAULT 0x00000000 -#define mmSEM_REGISTER_LAST_PART0_DEFAULT 0x00000000 -#define mmIH_RB_CNTL_DEFAULT 0x10610000 -#define mmIH_RB_BASE_DEFAULT 0x00000000 -#define mmIH_RB_BASE_HI_DEFAULT 0x00000000 -#define mmIH_RB_RPTR_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmIH_DOORBELL_RPTR_DEFAULT 0x00000000 -#define mmIH_RB_CNTL_RING1_DEFAULT 0x10410000 -#define mmIH_RB_BASE_RING1_DEFAULT 0x00000000 -#define mmIH_RB_BASE_HI_RING1_DEFAULT 0x00000000 -#define mmIH_RB_RPTR_RING1_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_RING1_DEFAULT 0x00000000 -#define mmIH_DOORBELL_RPTR_RING1_DEFAULT 0x00000000 -#define mmIH_RB_CNTL_RING2_DEFAULT 0x10410000 -#define mmIH_RB_BASE_RING2_DEFAULT 0x00000000 -#define mmIH_RB_BASE_HI_RING2_DEFAULT 0x00000000 -#define mmIH_RB_RPTR_RING2_DEFAULT 0x00000000 -#define mmIH_RB_WPTR_RING2_DEFAULT 0x00000000 -#define mmIH_DOORBELL_RPTR_RING2_DEFAULT 0x00000000 -#define mmIH_VERSION_DEFAULT 0x00000400 -#define mmIH_CNTL_DEFAULT 0x01000000 -#define mmIH_CNTL2_DEFAULT 0x000000ff -#define mmIH_STATUS_DEFAULT 0x00040847 -#define mmIH_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmIH_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmIH_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_VALUE_BIT_31_0_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_VALUE_BIT_63_32_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_VALUE_BIT_95_64_DEFAULT 0x00000000 -#define mmIH_DSM_MATCH_FIELD_CONTROL_DEFAULT 0x0000007f -#define mmIH_DSM_MATCH_DATA_CONTROL_DEFAULT 0x0fffffff -#define mmIH_DSM_MATCH_FCN_ID_DEFAULT 0x00000000 -#define mmIH_LIMIT_INT_RATE_CNTL_DEFAULT 0x00000000 -#define mmIH_VF_RB_STATUS_DEFAULT 0x00000000 -#define mmIH_VF_RB_STATUS2_DEFAULT 0x00000000 -#define mmIH_VF_RB1_STATUS_DEFAULT 0x00000000 -#define mmIH_VF_RB1_STATUS2_DEFAULT 0x00000000 -#define mmIH_VF_RB2_STATUS_DEFAULT 0x00000000 -#define mmIH_VF_RB2_STATUS2_DEFAULT 0x00000000 -#define mmIH_INT_FLOOD_CNTL_DEFAULT 0x00000000 -#define mmIH_RB0_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_RB1_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_RB2_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_INT_FLOOD_STATUS_DEFAULT 0x00000000 -#define mmIH_STORM_CLIENT_LIST_CNTL_DEFAULT 0x00000000 -#define mmIH_CLK_CTRL_DEFAULT 0x00000000 -#define mmIH_INT_FLAGS_DEFAULT 0x00000000 -#define mmIH_LAST_INT_INFO0_DEFAULT 0x00000000 -#define mmIH_LAST_INT_INFO1_DEFAULT 0x00000000 -#define mmIH_LAST_INT_INFO2_DEFAULT 0x00000000 -#define mmIH_SCRATCH_DEFAULT 0x00000000 -#define mmIH_CLIENT_CREDIT_ERROR_DEFAULT 0x00000000 -#define mmIH_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmIH_COOKIE_REC_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmIH_CREDIT_STATUS_DEFAULT 0xfffffffe -#define mmIH_MMHUB_ERROR_DEFAULT 0x00000000 -#define mmIH_REGISTER_LAST_PART2_DEFAULT 0x00000000 -#define mmSEM_CLK_CTRL_DEFAULT 0x00000100 -#define mmSEM_UTC_CREDIT_DEFAULT 0x00000510 -#define mmSEM_UTC_CONFIG_DEFAULT 0x00000020 -#define mmSEM_UTCL2_TRAN_EN_LUT_DEFAULT 0x800000ff -#define mmSEM_MCIF_CONFIG_DEFAULT 0x00001040 -#define mmSEM_PERFMON_CNTL_DEFAULT 0x00000000 -#define mmSEM_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmSEM_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmSEM_STATUS_DEFAULT 0x80f90003 -#define mmSEM_MAILBOX_CLIENTCONFIG_DEFAULT 0x00fac688 -#define mmSEM_MAILBOX_DEFAULT 0x00000000 -#define mmSEM_MAILBOX_CONTROL_DEFAULT 0x00000000 -#define mmSEM_CHICKEN_BITS_DEFAULT 0x00084ad6 -#define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_DEFAULT 0x00000008 -#define mmSEM_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmSEM_OUTSTANDING_THRESHOLD_DEFAULT 0x00000010 -#define mmSEM_REGISTER_LAST_PART2_DEFAULT 0x00000000 -#define mmIH_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmIH_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmIH_CLIENT_CFG_DEFAULT 0x0000001f -#define mmIH_CLIENT_CFG_INDEX_DEFAULT 0x00000000 -#define mmIH_CLIENT_CFG_DATA_DEFAULT 0x00000000 -#define mmIH_CID_REMAP_INDEX_DEFAULT 0x00000000 -#define mmIH_CID_REMAP_DATA_DEFAULT 0x00000000 -#define mmIH_CHICKEN_DEFAULT 0x00000000 -#define mmIH_MMHUB_CNTL_DEFAULT 0x00000001 -#define mmIH_REGISTER_LAST_PART1_DEFAULT 0x00000000 -#define mmSEM_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmSEM_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmSEM_RESP_SDMA0_DEFAULT 0x0004950c -#define mmSEM_RESP_SDMA1_DEFAULT 0x0004958c -#define mmSEM_RESP_UVD_DEFAULT 0x0004860c -#define mmSEM_RESP_VCE_0_DEFAULT 0x0004900c -#define mmSEM_RESP_ACP_DEFAULT 0x0004870c -#define mmSEM_RESP_ISP_DEFAULT 0x00000000 -#define mmSEM_RESP_VCE_1_DEFAULT 0x0004908c -#define mmSEM_RESP_VP8_DEFAULT 0x00000000 -#define mmSEM_RESP_GC_DEFAULT 0x0004858c -#define mmSEM_CID_REMAP_INDEX_DEFAULT 0x00000000 -#define mmSEM_CID_REMAP_DATA_DEFAULT 0x00000000 -#define mmSEM_ATOMIC_OP_LUT_DEFAULT 0x040a102f -#define mmSEM_EDC_CONFIG_DEFAULT 0x00000002 -#define mmSEM_CHICKEN_BITS2_DEFAULT 0x00000000 -#define mmSEM_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmSEM_REGISTER_LAST_PART1_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h deleted file mode 100644 index afd15bd6a41a..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_0_DEFAULT_HEADER -#define _sdma0_4_0_DEFAULT_HEADER - - -// addressBlock: sdma0_sdma0dec -#define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000 -#define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000 -#define mmSDMA0_VM_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000 -#define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000 -#define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000 -#define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f -#define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff -#define mmSDMA0_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff -#define mmSDMA0_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA0_PUB_REG_TYPE0_DEFAULT 0x3c000000 -#define mmSDMA0_PUB_REG_TYPE1_DEFAULT 0x30003882 -#define mmSDMA0_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 -#define mmSDMA0_PUB_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA0_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 -#define mmSDMA0_POWER_CNTL_DEFAULT 0x0003c000 -#define mmSDMA0_CLK_CTRL_DEFAULT 0xff000100 -#define mmSDMA0_CNTL_DEFAULT 0x00000002 -#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x00831f07 -#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00100012 -#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 -#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000 -#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000 -#define mmSDMA0_PROGRAM_DEFAULT 0x00000000 -#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557 -#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff -#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000003 -#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000 -#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000 -#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001 -#define mmSDMA0_FREEZE_DEFAULT 0x00000000 -#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA_POWER_GATING_DEFAULT 0x00000000 -#define mmSDMA_PGFSM_CONFIG_DEFAULT 0x00000000 -#define mmSDMA_PGFSM_WRITE_DEFAULT 0x00000000 -#define mmSDMA_PGFSM_READ_DEFAULT 0x00000000 -#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002 -#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff -#define mmSDMA0_ID_DEFAULT 0x00000001 -#define mmSDMA0_VERSION_DEFAULT 0x00000400 -#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000 -#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 -#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000 -#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200 -#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0003019 -#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbe1fe -#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x201001ff -#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x503001ff -#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000600 -#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000 -#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00010001 -#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x000003e0 -#define mmSDMA0_POWER_CNTL_IDLE_DEFAULT 0x06060200 -#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 -#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00000005 -#define mmSDMA0_STATUS3_REG_DEFAULT 0x00100000 -#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f -#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000 -#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000 -#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000 -#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000 -#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000 -#define mmSDMA0_UNBREAKABLE_DEFAULT 0x00000000 -#define mmSDMA0_PERFMON_CNTL_DEFAULT 0x000ff7fd -#define mmSDMA0_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmSDMA0_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 -#define mmSDMA0_CRD_CNTL_DEFAULT 0x000085c0 -#define mmSDMA0_MMHUB_TRUSTLVL_DEFAULT 0x00000000 -#define mmSDMA0_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmSDMA0_ULV_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 -#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_GFX_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_GFX_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 -#define mmSDMA0_GFX_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_GFX_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_GFX_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_GFX_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_GFX_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_GFX_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_PAGE_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_PAGE_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA0_PAGE_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_RLC0_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_RLC0_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA0_RLC0_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA0_RLC1_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA0_RLC1_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA0_RLC1_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_STATUS_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA0_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h deleted file mode 100644 index b100c4e5f1ca..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_0_OFFSET_HEADER -#define _sdma0_4_0_OFFSET_HEADER - - - -// addressBlock: sdma0_sdma0dec -// base address: 0x4980 -#define mmSDMA0_UCODE_ADDR 0x0000 -#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 -#define mmSDMA0_UCODE_DATA 0x0001 -#define mmSDMA0_UCODE_DATA_BASE_IDX 0 -#define mmSDMA0_VM_CNTL 0x0004 -#define mmSDMA0_VM_CNTL_BASE_IDX 0 -#define mmSDMA0_VM_CTX_LO 0x0005 -#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 -#define mmSDMA0_VM_CTX_HI 0x0006 -#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 -#define mmSDMA0_ACTIVE_FCN_ID 0x0007 -#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmSDMA0_VM_CTX_CNTL 0x0008 -#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 -#define mmSDMA0_VIRT_RESET_REQ 0x0009 -#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 -#define mmSDMA0_VF_ENABLE 0x000a -#define mmSDMA0_VF_ENABLE_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b -#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c -#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d -#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 -#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e -#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE0 0x000f -#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE1 0x0010 -#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE2 0x0011 -#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 -#define mmSDMA0_PUB_REG_TYPE3 0x0012 -#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 -#define mmSDMA0_MMHUB_CNTL 0x0013 -#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 -#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 -#define mmSDMA0_POWER_CNTL 0x001a -#define mmSDMA0_POWER_CNTL_BASE_IDX 0 -#define mmSDMA0_CLK_CTRL 0x001b -#define mmSDMA0_CLK_CTRL_BASE_IDX 0 -#define mmSDMA0_CNTL 0x001c -#define mmSDMA0_CNTL_BASE_IDX 0 -#define mmSDMA0_CHICKEN_BITS 0x001d -#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 -#define mmSDMA0_GB_ADDR_CONFIG 0x001e -#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 -#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f -#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 -#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 -#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define mmSDMA0_RB_RPTR_FETCH 0x0022 -#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 -#define mmSDMA0_IB_OFFSET_FETCH 0x0023 -#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 -#define mmSDMA0_PROGRAM 0x0024 -#define mmSDMA0_PROGRAM_BASE_IDX 0 -#define mmSDMA0_STATUS_REG 0x0025 -#define mmSDMA0_STATUS_REG_BASE_IDX 0 -#define mmSDMA0_STATUS1_REG 0x0026 -#define mmSDMA0_STATUS1_REG_BASE_IDX 0 -#define mmSDMA0_RD_BURST_CNTL 0x0027 -#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 -#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 -#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 -#define mmSDMA0_UCODE_CHECKSUM 0x0029 -#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 -#define mmSDMA0_F32_CNTL 0x002a -#define mmSDMA0_F32_CNTL_BASE_IDX 0 -#define mmSDMA0_FREEZE 0x002b -#define mmSDMA0_FREEZE_BASE_IDX 0 -#define mmSDMA0_PHASE0_QUANTUM 0x002c -#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 -#define mmSDMA0_PHASE1_QUANTUM 0x002d -#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 -#define mmSDMA_POWER_GATING 0x002e -#define mmSDMA_POWER_GATING_BASE_IDX 0 -#define mmSDMA_PGFSM_CONFIG 0x002f -#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 -#define mmSDMA_PGFSM_WRITE 0x0030 -#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 -#define mmSDMA_PGFSM_READ 0x0031 -#define mmSDMA_PGFSM_READ_BASE_IDX 0 -#define mmSDMA0_EDC_CONFIG 0x0032 -#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 -#define mmSDMA0_BA_THRESHOLD 0x0033 -#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 -#define mmSDMA0_ID 0x0034 -#define mmSDMA0_ID_BASE_IDX 0 -#define mmSDMA0_VERSION 0x0035 -#define mmSDMA0_VERSION_BASE_IDX 0 -#define mmSDMA0_EDC_COUNTER 0x0036 -#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 -#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 -#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define mmSDMA0_STATUS2_REG 0x0038 -#define mmSDMA0_STATUS2_REG_BASE_IDX 0 -#define mmSDMA0_ATOMIC_CNTL 0x0039 -#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 -#define mmSDMA0_ATOMIC_PREOP_LO 0x003a -#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 -#define mmSDMA0_ATOMIC_PREOP_HI 0x003b -#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 -#define mmSDMA0_UTCL1_CNTL 0x003c -#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 -#define mmSDMA0_UTCL1_WATERMK 0x003d -#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_STATUS 0x003e -#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_STATUS 0x003f -#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV0 0x0040 -#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV1 0x0041 -#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 -#define mmSDMA0_UTCL1_INV2 0x0042 -#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 -#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 -#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 -#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 -#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 -#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 -#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 -#define mmSDMA0_UTCL1_TIMEOUT 0x0047 -#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 -#define mmSDMA0_UTCL1_PAGE 0x0048 -#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 -#define mmSDMA0_POWER_CNTL_IDLE 0x0049 -#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 -#define mmSDMA0_RELAX_ORDERING_LUT 0x004a -#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 -#define mmSDMA0_CHICKEN_BITS_2 0x004b -#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 -#define mmSDMA0_STATUS3_REG 0x004c -#define mmSDMA0_STATUS3_REG_BASE_IDX 0 -#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d -#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e -#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PHASE2_QUANTUM 0x004f -#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 -#define mmSDMA0_ERROR_LOG 0x0050 -#define mmSDMA0_ERROR_LOG_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG0 0x0051 -#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG1 0x0052 -#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG2 0x0053 -#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 -#define mmSDMA0_PUB_DUMMY_REG3 0x0054 -#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 -#define mmSDMA0_F32_COUNTER 0x0055 -#define mmSDMA0_F32_COUNTER_BASE_IDX 0 -#define mmSDMA0_UNBREAKABLE 0x0056 -#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 -#define mmSDMA0_PERFMON_CNTL 0x0057 -#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 -#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 -#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 -#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 -#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a -#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 -#define mmSDMA0_CRD_CNTL 0x005b -#define mmSDMA0_CRD_CNTL_BASE_IDX 0 -#define mmSDMA0_MMHUB_TRUSTLVL 0x005c -#define mmSDMA0_MMHUB_TRUSTLVL_BASE_IDX 0 -#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d -#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 -#define mmSDMA0_ULV_CNTL 0x005e -#define mmSDMA0_ULV_CNTL_BASE_IDX 0 -#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 -#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 -#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define mmSDMA0_GFX_RB_CNTL 0x0080 -#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_RB_BASE 0x0081 -#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 -#define mmSDMA0_GFX_RB_BASE_HI 0x0082 -#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR 0x0083 -#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 -#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR 0x0085 -#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 -#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 -#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 -#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 -#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_IB_CNTL 0x008a -#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_IB_RPTR 0x008b -#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_GFX_IB_OFFSET 0x008c -#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_GFX_IB_BASE_LO 0x008d -#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_GFX_IB_BASE_HI 0x008e -#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_GFX_IB_SIZE 0x008f -#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_GFX_SKIP_CNTL 0x0090 -#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 -#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL 0x0092 -#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 -#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 -#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_STATUS 0x00a8 -#define mmSDMA0_GFX_STATUS_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 -#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_GFX_WATERMARK 0x00aa -#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 -#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab -#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac -#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad -#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af -#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_GFX_PREEMPT 0x00b0 -#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 -#define mmSDMA0_GFX_DUMMY_REG 0x00b1 -#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 -#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 -#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 -#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 -#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 -#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 -#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 -#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 -#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 -#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 -#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 -#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 -#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_CNTL 0x00e0 -#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_BASE 0x00e1 -#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 -#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR 0x00e3 -#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 -#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR 0x00e5 -#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 -#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 -#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 -#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_CNTL 0x00ea -#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_RPTR 0x00eb -#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_OFFSET 0x00ec -#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed -#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee -#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_SIZE 0x00ef -#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 -#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 -#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL 0x00f2 -#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 -#define mmSDMA0_PAGE_STATUS 0x0108 -#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 -#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_PAGE_WATERMARK 0x010a -#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 -#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b -#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c -#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d -#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f -#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_PAGE_PREEMPT 0x0110 -#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 -#define mmSDMA0_PAGE_DUMMY_REG 0x0111 -#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 -#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 -#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 -#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 -#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 -#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 -#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 -#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 -#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 -#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 -#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 -#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 -#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 -#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_CNTL 0x0140 -#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_BASE 0x0141 -#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_BASE_HI 0x0142 -#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR 0x0143 -#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 -#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR 0x0145 -#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 -#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 -#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 -#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_CNTL 0x014a -#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_RPTR 0x014b -#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_OFFSET 0x014c -#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_BASE_LO 0x014d -#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_BASE_HI 0x014e -#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_SIZE 0x014f -#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC0_SKIP_CNTL 0x0150 -#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 -#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL 0x0152 -#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC0_STATUS 0x0168 -#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 -#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC0_WATERMARK 0x016a -#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b -#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c -#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d -#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f -#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC0_PREEMPT 0x0170 -#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC0_DUMMY_REG 0x0171 -#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 -#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 -#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 -#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 -#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 -#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 -#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 -#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 -#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 -#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 -#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 -#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 -#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 -#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_CNTL 0x01a0 -#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_BASE 0x01a1 -#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 -#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR 0x01a3 -#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 -#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR 0x01a5 -#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 -#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 -#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 -#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_CNTL 0x01aa -#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_RPTR 0x01ab -#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_OFFSET 0x01ac -#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad -#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae -#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_SIZE 0x01af -#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 -#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 -#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 -#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL 0x01b2 -#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 -#define mmSDMA0_RLC1_STATUS 0x01c8 -#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 -#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA0_RLC1_WATERMARK 0x01ca -#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 -#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb -#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc -#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd -#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf -#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA0_RLC1_PREEMPT 0x01d0 -#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 -#define mmSDMA0_RLC1_DUMMY_REG 0x01d1 -#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 -#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 -#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 -#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 -#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 -#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 -#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 -#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 -#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 -#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 -#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 -#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 -#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 -#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h deleted file mode 100644 index 412ae457f7e0..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h +++ /dev/null @@ -1,1852 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma0_4_0_SH_MASK_HEADER -#define _sdma0_4_0_SH_MASK_HEADER - - -// addressBlock: sdma0_sdma0dec -//SDMA0_UCODE_ADDR -#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL -//SDMA0_UCODE_DATA -#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 -#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_VM_CNTL -#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 -#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL -//SDMA0_VM_CTX_LO -#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 -#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_VM_CTX_HI -#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 -#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_ACTIVE_FCN_ID -#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//SDMA0_VM_CTX_CNTL -#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 -#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 -#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L -//SDMA0_VIRT_RESET_REQ -#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L -//SDMA0_VF_ENABLE -#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 -#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -//SDMA0_CONTEXT_REG_TYPE0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L -//SDMA0_CONTEXT_REG_TYPE1 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L -//SDMA0_CONTEXT_REG_TYPE2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L -//SDMA0_CONTEXT_REG_TYPE3 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_PUB_REG_TYPE0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e -#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L -#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L -#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L -//SDMA0_PUB_REG_TYPE3 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 -#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL -//SDMA0_MMHUB_CNTL -#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 -#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL -//SDMA0_CONTEXT_GROUP_BOUNDARY -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 -#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL -//SDMA0_POWER_CNTL -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc -#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L -#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L -//SDMA0_CLK_CTRL -#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//SDMA0_CNTL -#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 -#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 -#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 -#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c -#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e -#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L -//SDMA0_CHICKEN_BITS -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e -#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L -#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L -#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L -//SDMA0_GB_ADDR_CONFIG -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_GB_ADDR_CONFIG_READ -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA0_RB_RPTR_FETCH_HI -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 -#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL -//SDMA0_RB_RPTR_FETCH -#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL -//SDMA0_IB_OFFSET_FETCH -#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 -#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL -//SDMA0_PROGRAM -#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 -#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL -//SDMA0_STATUS_REG -#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 -#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 -#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 -#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 -#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 -#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 -#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 -#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 -#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 -#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 -#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb -#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc -#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd -#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe -#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 -#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 -#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 -#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 -#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a -#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b -#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c -#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e -#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f -#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L -//SDMA0_STATUS1_REG -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 -#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 -#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 -#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 -#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 -#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa -#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd -#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe -#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf -#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 -#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 -#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L -//SDMA0_RD_BURST_CNTL -#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 -#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L -//SDMA0_HBM_PAGE_CONFIG -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 -#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L -//SDMA0_UCODE_CHECKSUM -#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 -#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL -//SDMA0_F32_CNTL -#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 -#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 -#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L -//SDMA0_FREEZE -#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 -#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 -#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 -#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 -#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L -//SDMA0_PHASE0_QUANTUM -#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L -//SDMA0_PHASE1_QUANTUM -#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L -//SDMA_POWER_GATING -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 -#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L -#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L -#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L -#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L -//SDMA_PGFSM_CONFIG -#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 -#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 -#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 -#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa -#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb -#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc -#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b -#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c -#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL -#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L -#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L -#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L -#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L -#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L -#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L -#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L -#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L -//SDMA_PGFSM_WRITE -#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL -//SDMA_PGFSM_READ -#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 -#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL -//SDMA0_EDC_CONFIG -#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 -#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L -//SDMA0_BA_THRESHOLD -#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 -#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 -#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL -#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L -//SDMA0_ID -#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 -#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL -//SDMA0_VERSION -#define SDMA0_VERSION__MINVER__SHIFT 0x0 -#define SDMA0_VERSION__MAJVER__SHIFT 0x8 -#define SDMA0_VERSION__REV__SHIFT 0x10 -#define SDMA0_VERSION__MINVER_MASK 0x0000007FL -#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L -#define SDMA0_VERSION__REV_MASK 0x003F0000L -//SDMA0_EDC_COUNTER -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L -//SDMA0_EDC_COUNTER_CLEAR -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 -#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L -//SDMA0_STATUS2_REG -#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 -#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 -#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 -#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL -#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L -//SDMA0_ATOMIC_CNTL -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f -#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL -#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L -//SDMA0_ATOMIC_PREOP_LO -#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL -//SDMA0_ATOMIC_PREOP_HI -#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 -#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_CNTL -#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 -#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 -#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb -#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d -#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL -#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L -#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L -#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L -//SDMA0_UTCL1_WATERMK -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a -#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL -#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L -#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L -#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L -//SDMA0_UTCL1_RD_STATUS -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L -#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L -#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L -//SDMA0_UTCL1_WR_STATUS -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L -#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L -//SDMA0_UTCL1_INV0 -#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 -#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 -#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 -#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 -#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb -#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc -#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c -#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L -#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L -//SDMA0_UTCL1_INV1 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_INV2 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 -#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_RD_XNACK1 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_WR_XNACK0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA0_UTCL1_WR_XNACK1 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA0_UTCL1_TIMEOUT -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 -#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL -#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L -//SDMA0_UTCL1_PAGE -#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 -#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 -#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 -#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL -#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L -#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L -//SDMA0_POWER_CNTL_IDLE -#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 -#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 -#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 -#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL -#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L -#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L -//SDMA0_RELAX_ORDERING_LUT -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 -#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 -#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 -#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd -#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f -#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L -#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L -#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L -//SDMA0_CHICKEN_BITS_2 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 -#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL -//SDMA0_STATUS3_REG -#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 -#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 -#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL -#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L -#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L -//SDMA0_PHYSICAL_ADDR_LO -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 -#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc -#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L -//SDMA0_PHYSICAL_ADDR_HI -#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL -//SDMA0_PHASE2_QUANTUM -#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L -//SDMA0_ERROR_LOG -#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 -#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 -#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL -#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L -//SDMA0_PUB_DUMMY_REG0 -#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG1 -#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG2 -#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL -//SDMA0_PUB_DUMMY_REG3 -#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 -#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL -//SDMA0_F32_COUNTER -#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 -#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL -//SDMA0_UNBREAKABLE -#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 -#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L -//SDMA0_PERFMON_CNTL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 -#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb -#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc -#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL -#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L -//SDMA0_PERFCOUNTER0_RESULT -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER1_RESULT -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L -#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L -//SDMA0_CRD_CNTL -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd -#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L -#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L -//SDMA0_MMHUB_TRUSTLVL -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L -#define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L -//SDMA0_GPU_IOV_VIOLATION_LOG -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//SDMA0_ULV_CNTL -#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 -#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d -#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e -#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f -#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL -#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L -#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L -#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L -//SDMA0_EA_DBIT_ADDR_DATA -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA0_EA_DBIT_ADDR_INDEX -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 -#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L -//SDMA0_GFX_RB_CNTL -#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_GFX_RB_BASE -#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_BASE_HI -#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_GFX_RB_RPTR -#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_HI -#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR -#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_HI -#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_CNTL -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_GFX_RB_RPTR_ADDR_HI -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_RPTR_ADDR_LO -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_IB_CNTL -#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_GFX_IB_RPTR -#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_OFFSET -#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_GFX_IB_BASE_LO -#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_GFX_IB_BASE_HI -#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SIZE -#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_GFX_SKIP_CNTL -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_GFX_CONTEXT_STATUS -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_GFX_DOORBELL -#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_GFX_CONTEXT_CNTL -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 -#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -//SDMA0_GFX_STATUS -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_GFX_DOORBELL_LOG -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_GFX_WATERMARK -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_GFX_DOORBELL_OFFSET -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_GFX_CSA_ADDR_LO -#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_CSA_ADDR_HI -#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_IB_SUB_REMAIN -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_GFX_PREEMPT -#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_GFX_DUMMY_REG -#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_GFX_RB_AQL_CNTL -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_GFX_MINOR_PTR_UPDATE -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_GFX_MIDCMD_DATA0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA1 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA2 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA3 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA4 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA5 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA6 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA7 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_DATA8 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_GFX_MIDCMD_CNTL -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_PAGE_RB_CNTL -#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_PAGE_RB_BASE -#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_BASE_HI -#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_PAGE_RB_RPTR -#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_RPTR_HI -#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR -#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_HI -#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_POLL_CNTL -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_PAGE_RB_RPTR_ADDR_HI -#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_RPTR_ADDR_LO -#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_PAGE_IB_CNTL -#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_PAGE_IB_RPTR -#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_PAGE_IB_OFFSET -#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_PAGE_IB_BASE_LO -#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_PAGE_IB_BASE_HI -#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_IB_SIZE -#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_PAGE_SKIP_CNTL -#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_PAGE_CONTEXT_STATUS -#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_PAGE_DOORBELL -#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_PAGE_STATUS -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_PAGE_DOORBELL_LOG -#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_PAGE_WATERMARK -#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_PAGE_DOORBELL_OFFSET -#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_PAGE_CSA_ADDR_LO -#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_PAGE_CSA_ADDR_HI -#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_IB_SUB_REMAIN -#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_PAGE_PREEMPT -#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_PAGE_DUMMY_REG -#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_PAGE_RB_AQL_CNTL -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_PAGE_MINOR_PTR_UPDATE -#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_PAGE_MIDCMD_DATA0 -#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA1 -#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA2 -#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA3 -#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA4 -#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA5 -#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA6 -#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA7 -#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_DATA8 -#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_PAGE_MIDCMD_CNTL -#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC0_RB_CNTL -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC0_RB_BASE -#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_BASE_HI -#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC0_RB_RPTR -#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_HI -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR -#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_HI -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_CNTL -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC0_RB_RPTR_ADDR_HI -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_RPTR_ADDR_LO -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_IB_CNTL -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC0_IB_RPTR -#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_OFFSET -#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC0_IB_BASE_LO -#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC0_IB_BASE_HI -#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SIZE -#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC0_SKIP_CNTL -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC0_CONTEXT_STATUS -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC0_DOORBELL -#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC0_STATUS -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC0_DOORBELL_LOG -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC0_WATERMARK -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC0_DOORBELL_OFFSET -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC0_CSA_ADDR_LO -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_CSA_ADDR_HI -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_IB_SUB_REMAIN -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC0_PREEMPT -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC0_DUMMY_REG -#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC0_RB_AQL_CNTL -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC0_MINOR_PTR_UPDATE -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC0_MIDCMD_DATA0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA1 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA2 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA3 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA4 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA5 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA6 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA7 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_DATA8 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC0_MIDCMD_CNTL -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA0_RLC1_RB_CNTL -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA0_RLC1_RB_BASE -#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_BASE_HI -#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA0_RLC1_RB_RPTR -#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_HI -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR -#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_HI -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_CNTL -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA0_RLC1_RB_RPTR_ADDR_HI -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_RPTR_ADDR_LO -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_IB_CNTL -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA0_RLC1_IB_RPTR -#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_OFFSET -#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA0_RLC1_IB_BASE_LO -#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA0_RLC1_IB_BASE_HI -#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SIZE -#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA0_RLC1_SKIP_CNTL -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA0_RLC1_CONTEXT_STATUS -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA0_RLC1_DOORBELL -#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA0_RLC1_STATUS -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA0_RLC1_DOORBELL_LOG -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA0_RLC1_WATERMARK -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA0_RLC1_DOORBELL_OFFSET -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA0_RLC1_CSA_ADDR_LO -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_CSA_ADDR_HI -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_IB_SUB_REMAIN -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA0_RLC1_PREEMPT -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA0_RLC1_DUMMY_REG -#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA0_RLC1_RB_AQL_CNTL -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA0_RLC1_MINOR_PTR_UPDATE -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA0_RLC1_MIDCMD_DATA0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA1 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA2 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA3 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA4 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA5 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA6 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA7 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_DATA8 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA0_RLC1_MIDCMD_CNTL -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h deleted file mode 100644 index 85c5c5e3ce7d..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma1_4_0_DEFAULT_HEADER -#define _sdma1_4_0_DEFAULT_HEADER - - -// addressBlock: sdma1_sdma1dec -#define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000 -#define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000 -#define mmSDMA1_VM_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000 -#define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000 -#define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000 -#define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000 -#define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000 -#define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f -#define mmSDMA1_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff -#define mmSDMA1_CONTEXT_REG_TYPE2_DEFAULT 0x000003ff -#define mmSDMA1_CONTEXT_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA1_PUB_REG_TYPE0_DEFAULT 0x3c000000 -#define mmSDMA1_PUB_REG_TYPE1_DEFAULT 0x30003882 -#define mmSDMA1_PUB_REG_TYPE2_DEFAULT 0x0fc6e880 -#define mmSDMA1_PUB_REG_TYPE3_DEFAULT 0x00000000 -#define mmSDMA1_MMHUB_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_DEFAULT 0x00000000 -#define mmSDMA1_POWER_CNTL_DEFAULT 0x0003c000 -#define mmSDMA1_CLK_CTRL_DEFAULT 0xff000100 -#define mmSDMA1_CNTL_DEFAULT 0x00000002 -#define mmSDMA1_CHICKEN_BITS_DEFAULT 0x00831f07 -#define mmSDMA1_GB_ADDR_CONFIG_DEFAULT 0x00100012 -#define mmSDMA1_GB_ADDR_CONFIG_READ_DEFAULT 0x00100012 -#define mmSDMA1_RB_RPTR_FETCH_HI_DEFAULT 0x00000000 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RB_RPTR_FETCH_DEFAULT 0x00000000 -#define mmSDMA1_IB_OFFSET_FETCH_DEFAULT 0x00000000 -#define mmSDMA1_PROGRAM_DEFAULT 0x00000000 -#define mmSDMA1_STATUS_REG_DEFAULT 0x46dee557 -#define mmSDMA1_STATUS1_REG_DEFAULT 0x000003ff -#define mmSDMA1_RD_BURST_CNTL_DEFAULT 0x00000003 -#define mmSDMA1_HBM_PAGE_CONFIG_DEFAULT 0x00000000 -#define mmSDMA1_UCODE_CHECKSUM_DEFAULT 0x00000000 -#define mmSDMA1_F32_CNTL_DEFAULT 0x00000001 -#define mmSDMA1_FREEZE_DEFAULT 0x00000000 -#define mmSDMA1_PHASE0_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA1_PHASE1_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA1_EDC_CONFIG_DEFAULT 0x00000002 -#define mmSDMA1_BA_THRESHOLD_DEFAULT 0x03ff03ff -#define mmSDMA1_ID_DEFAULT 0x00000001 -#define mmSDMA1_VERSION_DEFAULT 0x00000400 -#define mmSDMA1_EDC_COUNTER_DEFAULT 0x00000000 -#define mmSDMA1_EDC_COUNTER_CLEAR_DEFAULT 0x00000000 -#define mmSDMA1_STATUS2_REG_DEFAULT 0x00000001 -#define mmSDMA1_ATOMIC_CNTL_DEFAULT 0x00000200 -#define mmSDMA1_ATOMIC_PREOP_LO_DEFAULT 0x00000000 -#define mmSDMA1_ATOMIC_PREOP_HI_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_CNTL_DEFAULT 0xd0003019 -#define mmSDMA1_UTCL1_WATERMK_DEFAULT 0xfffbe1fe -#define mmSDMA1_UTCL1_RD_STATUS_DEFAULT 0x201001ff -#define mmSDMA1_UTCL1_WR_STATUS_DEFAULT 0x503001ff -#define mmSDMA1_UTCL1_INV0_DEFAULT 0x00000600 -#define mmSDMA1_UTCL1_INV1_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_INV2_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_RD_XNACK0_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_RD_XNACK1_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_WR_XNACK0_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_WR_XNACK1_DEFAULT 0x00000000 -#define mmSDMA1_UTCL1_TIMEOUT_DEFAULT 0x00010001 -#define mmSDMA1_UTCL1_PAGE_DEFAULT 0x000003e0 -#define mmSDMA1_POWER_CNTL_IDLE_DEFAULT 0x06060200 -#define mmSDMA1_RELAX_ORDERING_LUT_DEFAULT 0xc0000006 -#define mmSDMA1_CHICKEN_BITS_2_DEFAULT 0x00000005 -#define mmSDMA1_STATUS3_REG_DEFAULT 0x00100000 -#define mmSDMA1_PHYSICAL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PHYSICAL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PHASE2_QUANTUM_DEFAULT 0x00010002 -#define mmSDMA1_ERROR_LOG_DEFAULT 0x0000000f -#define mmSDMA1_PUB_DUMMY_REG0_DEFAULT 0x00000000 -#define mmSDMA1_PUB_DUMMY_REG1_DEFAULT 0x00000000 -#define mmSDMA1_PUB_DUMMY_REG2_DEFAULT 0x00000000 -#define mmSDMA1_PUB_DUMMY_REG3_DEFAULT 0x00000000 -#define mmSDMA1_F32_COUNTER_DEFAULT 0x00000000 -#define mmSDMA1_UNBREAKABLE_DEFAULT 0x00000000 -#define mmSDMA1_PERFMON_CNTL_DEFAULT 0x000ff7fd -#define mmSDMA1_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 -#define mmSDMA1_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_DEFAULT 0x00640000 -#define mmSDMA1_CRD_CNTL_DEFAULT 0x000085c0 -#define mmSDMA1_MMHUB_TRUSTLVL_DEFAULT 0x00000000 -#define mmSDMA1_GPU_IOV_VIOLATION_LOG_DEFAULT 0x00000000 -#define mmSDMA1_ULV_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000 -#define mmSDMA1_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_GFX_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_GFX_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_GFX_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CONTEXT_STATUS_DEFAULT 0x00000005 -#define mmSDMA1_GFX_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CONTEXT_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_GFX_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_GFX_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_GFX_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_GFX_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_GFX_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_GFX_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_GFX_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_GFX_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_PAGE_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_PAGE_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA1_PAGE_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_PAGE_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_RLC0_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_RLC0_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA1_RLC0_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_RLC0_MIDCMD_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_CNTL_DEFAULT 0x00040000 -#define mmSDMA1_RLC1_RB_BASE_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_RPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_DEFAULT 0x00401000 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_CNTL_DEFAULT 0x00000100 -#define mmSDMA1_RLC1_IB_RPTR_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_BASE_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_BASE_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_SIZE_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_SKIP_CNTL_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_CONTEXT_STATUS_DEFAULT 0x00000004 -#define mmSDMA1_RLC1_DOORBELL_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_STATUS_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_DOORBELL_LOG_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_WATERMARK_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_DOORBELL_OFFSET_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_CSA_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_CSA_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_IB_SUB_REMAIN_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_PREEMPT_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_DUMMY_REG_DEFAULT 0x0000000f -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_RB_AQL_CNTL_DEFAULT 0x00004000 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA0_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA1_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA2_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA3_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA4_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA5_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA6_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA7_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_DATA8_DEFAULT 0x00000000 -#define mmSDMA1_RLC1_MIDCMD_CNTL_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h deleted file mode 100644 index 92150d6b65b8..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h +++ /dev/null @@ -1,539 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma1_4_0_OFFSET_HEADER -#define _sdma1_4_0_OFFSET_HEADER - - - -// addressBlock: sdma1_sdma1dec -// base address: 0x5180 -#define mmSDMA1_UCODE_ADDR 0x0000 -#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 -#define mmSDMA1_UCODE_DATA 0x0001 -#define mmSDMA1_UCODE_DATA_BASE_IDX 0 -#define mmSDMA1_VM_CNTL 0x0004 -#define mmSDMA1_VM_CNTL_BASE_IDX 0 -#define mmSDMA1_VM_CTX_LO 0x0005 -#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 -#define mmSDMA1_VM_CTX_HI 0x0006 -#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 -#define mmSDMA1_ACTIVE_FCN_ID 0x0007 -#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 -#define mmSDMA1_VM_CTX_CNTL 0x0008 -#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 -#define mmSDMA1_VIRT_RESET_REQ 0x0009 -#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 -#define mmSDMA1_VF_ENABLE 0x000a -#define mmSDMA1_VF_ENABLE_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b -#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c -#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d -#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 -#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e -#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE0 0x000f -#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE1 0x0010 -#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE2 0x0011 -#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 -#define mmSDMA1_PUB_REG_TYPE3 0x0012 -#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 -#define mmSDMA1_MMHUB_CNTL 0x0013 -#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 -#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 -#define mmSDMA1_POWER_CNTL 0x001a -#define mmSDMA1_POWER_CNTL_BASE_IDX 0 -#define mmSDMA1_CLK_CTRL 0x001b -#define mmSDMA1_CLK_CTRL_BASE_IDX 0 -#define mmSDMA1_CNTL 0x001c -#define mmSDMA1_CNTL_BASE_IDX 0 -#define mmSDMA1_CHICKEN_BITS 0x001d -#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 -#define mmSDMA1_GB_ADDR_CONFIG 0x001e -#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 -#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f -#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 -#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 -#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 -#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 -#define mmSDMA1_RB_RPTR_FETCH 0x0022 -#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 -#define mmSDMA1_IB_OFFSET_FETCH 0x0023 -#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 -#define mmSDMA1_PROGRAM 0x0024 -#define mmSDMA1_PROGRAM_BASE_IDX 0 -#define mmSDMA1_STATUS_REG 0x0025 -#define mmSDMA1_STATUS_REG_BASE_IDX 0 -#define mmSDMA1_STATUS1_REG 0x0026 -#define mmSDMA1_STATUS1_REG_BASE_IDX 0 -#define mmSDMA1_RD_BURST_CNTL 0x0027 -#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 -#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 -#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 -#define mmSDMA1_UCODE_CHECKSUM 0x0029 -#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 -#define mmSDMA1_F32_CNTL 0x002a -#define mmSDMA1_F32_CNTL_BASE_IDX 0 -#define mmSDMA1_FREEZE 0x002b -#define mmSDMA1_FREEZE_BASE_IDX 0 -#define mmSDMA1_PHASE0_QUANTUM 0x002c -#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 -#define mmSDMA1_PHASE1_QUANTUM 0x002d -#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 -#define mmSDMA1_EDC_CONFIG 0x0032 -#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 -#define mmSDMA1_BA_THRESHOLD 0x0033 -#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 -#define mmSDMA1_ID 0x0034 -#define mmSDMA1_ID_BASE_IDX 0 -#define mmSDMA1_VERSION 0x0035 -#define mmSDMA1_VERSION_BASE_IDX 0 -#define mmSDMA1_EDC_COUNTER 0x0036 -#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 -#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 -#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 -#define mmSDMA1_STATUS2_REG 0x0038 -#define mmSDMA1_STATUS2_REG_BASE_IDX 0 -#define mmSDMA1_ATOMIC_CNTL 0x0039 -#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 -#define mmSDMA1_ATOMIC_PREOP_LO 0x003a -#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 -#define mmSDMA1_ATOMIC_PREOP_HI 0x003b -#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 -#define mmSDMA1_UTCL1_CNTL 0x003c -#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 -#define mmSDMA1_UTCL1_WATERMK 0x003d -#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_STATUS 0x003e -#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_STATUS 0x003f -#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV0 0x0040 -#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV1 0x0041 -#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 -#define mmSDMA1_UTCL1_INV2 0x0042 -#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 -#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 -#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 -#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 -#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 -#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 -#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 -#define mmSDMA1_UTCL1_TIMEOUT 0x0047 -#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 -#define mmSDMA1_UTCL1_PAGE 0x0048 -#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 -#define mmSDMA1_POWER_CNTL_IDLE 0x0049 -#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 -#define mmSDMA1_RELAX_ORDERING_LUT 0x004a -#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 -#define mmSDMA1_CHICKEN_BITS_2 0x004b -#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 -#define mmSDMA1_STATUS3_REG 0x004c -#define mmSDMA1_STATUS3_REG_BASE_IDX 0 -#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d -#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e -#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PHASE2_QUANTUM 0x004f -#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 -#define mmSDMA1_ERROR_LOG 0x0050 -#define mmSDMA1_ERROR_LOG_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG0 0x0051 -#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG1 0x0052 -#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG2 0x0053 -#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 -#define mmSDMA1_PUB_DUMMY_REG3 0x0054 -#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 -#define mmSDMA1_F32_COUNTER 0x0055 -#define mmSDMA1_F32_COUNTER_BASE_IDX 0 -#define mmSDMA1_UNBREAKABLE 0x0056 -#define mmSDMA1_UNBREAKABLE_BASE_IDX 0 -#define mmSDMA1_PERFMON_CNTL 0x0057 -#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 -#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 -#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 -#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 -#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a -#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 -#define mmSDMA1_CRD_CNTL 0x005b -#define mmSDMA1_CRD_CNTL_BASE_IDX 0 -#define mmSDMA1_MMHUB_TRUSTLVL 0x005c -#define mmSDMA1_MMHUB_TRUSTLVL_BASE_IDX 0 -#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d -#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 -#define mmSDMA1_ULV_CNTL 0x005e -#define mmSDMA1_ULV_CNTL_BASE_IDX 0 -#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 -#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 -#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 -#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 -#define mmSDMA1_GFX_RB_CNTL 0x0080 -#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_RB_BASE 0x0081 -#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 -#define mmSDMA1_GFX_RB_BASE_HI 0x0082 -#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR 0x0083 -#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 -#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR 0x0085 -#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 -#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 -#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 -#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 -#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_IB_CNTL 0x008a -#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_IB_RPTR 0x008b -#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_GFX_IB_OFFSET 0x008c -#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_GFX_IB_BASE_LO 0x008d -#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_GFX_IB_BASE_HI 0x008e -#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_GFX_IB_SIZE 0x008f -#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_GFX_SKIP_CNTL 0x0090 -#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 -#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL 0x0092 -#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 -#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 -#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_STATUS 0x00a8 -#define mmSDMA1_GFX_STATUS_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 -#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_GFX_WATERMARK 0x00aa -#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 -#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab -#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac -#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad -#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af -#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_GFX_PREEMPT 0x00b0 -#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 -#define mmSDMA1_GFX_DUMMY_REG 0x00b1 -#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 -#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 -#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 -#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 -#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 -#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 -#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 -#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 -#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 -#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 -#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 -#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 -#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 -#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_CNTL 0x00e0 -#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_BASE 0x00e1 -#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 -#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR 0x00e3 -#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 -#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR 0x00e5 -#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 -#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 -#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 -#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_CNTL 0x00ea -#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_RPTR 0x00eb -#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_OFFSET 0x00ec -#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed -#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee -#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_SIZE 0x00ef -#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 -#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 -#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL 0x00f2 -#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 -#define mmSDMA1_PAGE_STATUS 0x0108 -#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 -#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_PAGE_WATERMARK 0x010a -#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 -#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b -#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c -#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d -#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f -#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_PAGE_PREEMPT 0x0110 -#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 -#define mmSDMA1_PAGE_DUMMY_REG 0x0111 -#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 -#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 -#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 -#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 -#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 -#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 -#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 -#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 -#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 -#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 -#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 -#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 -#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 -#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_CNTL 0x0140 -#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_BASE 0x0141 -#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_BASE_HI 0x0142 -#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR 0x0143 -#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 -#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR 0x0145 -#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 -#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 -#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 -#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_CNTL 0x014a -#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_RPTR 0x014b -#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_OFFSET 0x014c -#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_BASE_LO 0x014d -#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_BASE_HI 0x014e -#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_SIZE 0x014f -#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC0_SKIP_CNTL 0x0150 -#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 -#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL 0x0152 -#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC0_STATUS 0x0168 -#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 -#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC0_WATERMARK 0x016a -#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b -#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c -#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d -#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f -#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC0_PREEMPT 0x0170 -#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC0_DUMMY_REG 0x0171 -#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 -#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 -#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 -#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 -#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 -#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 -#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 -#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 -#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 -#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 -#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 -#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 -#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 -#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_CNTL 0x01a0 -#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_BASE 0x01a1 -#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 -#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR 0x01a3 -#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 -#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR 0x01a5 -#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 -#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 -#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 -#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_CNTL 0x01aa -#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_RPTR 0x01ab -#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_OFFSET 0x01ac -#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad -#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae -#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_SIZE 0x01af -#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 -#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 -#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 -#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL 0x01b2 -#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 -#define mmSDMA1_RLC1_STATUS 0x01c8 -#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 -#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 -#define mmSDMA1_RLC1_WATERMARK 0x01ca -#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 -#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb -#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 -#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc -#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd -#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf -#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 -#define mmSDMA1_RLC1_PREEMPT 0x01d0 -#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 -#define mmSDMA1_RLC1_DUMMY_REG 0x01d1 -#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 -#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 -#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 -#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 -#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 -#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 -#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 -#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 -#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 -#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 -#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 -#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 -#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 -#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 -#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 -#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h deleted file mode 100644 index 25decdf96d16..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h +++ /dev/null @@ -1,1810 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _sdma1_4_0_SH_MASK_HEADER -#define _sdma1_4_0_SH_MASK_HEADER - - -// addressBlock: sdma1_sdma1dec -//SDMA1_UCODE_ADDR -#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 -#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL -//SDMA1_UCODE_DATA -#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 -#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA1_VM_CNTL -#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 -#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL -//SDMA1_VM_CTX_LO -#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 -#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_VM_CTX_HI -#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 -#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_ACTIVE_FCN_ID -#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 -#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 -#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f -#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL -#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L -#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L -//SDMA1_VM_CTX_CNTL -#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 -#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 -#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L -#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L -//SDMA1_VIRT_RESET_REQ -#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 -#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f -#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL -#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L -//SDMA1_VF_ENABLE -#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 -#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L -//SDMA1_CONTEXT_REG_TYPE0 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L -//SDMA1_CONTEXT_REG_TYPE1 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L -#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L -#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L -#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L -//SDMA1_CONTEXT_REG_TYPE2 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L -#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L -#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L -//SDMA1_CONTEXT_REG_TYPE3 -#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 -#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL -//SDMA1_PUB_REG_TYPE0 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 -#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 -#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 -#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 -#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 -#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L -//SDMA1_PUB_REG_TYPE1 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 -#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 -#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 -#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 -#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 -#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 -#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa -#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd -#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 -#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 -#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L -//SDMA1_PUB_REG_TYPE2 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 -#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 -#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa -#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb -#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf -#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 -#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 -#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a -#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b -#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c -#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d -#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e -#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L -#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L -#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L -#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L -#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L -#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L -#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L -//SDMA1_PUB_REG_TYPE3 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 -#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L -#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L -#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL -//SDMA1_MMHUB_CNTL -#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 -#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL -//SDMA1_CONTEXT_GROUP_BOUNDARY -#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 -#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL -//SDMA1_POWER_CNTL -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc -#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L -#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L -#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L -#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L -#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L -//SDMA1_CLK_CTRL -#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 -#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f -#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL -#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L -#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L -#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L -//SDMA1_CNTL -#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 -#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 -#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 -#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c -#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e -#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L -#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L -#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L -#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L -#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L -#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L -#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L -#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L -#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L -#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L -//SDMA1_CHICKEN_BITS -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 -#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 -#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 -#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 -#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e -#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L -#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L -#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L -#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L -#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L -#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L -#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L -#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L -#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L -#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L -#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L -#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L -#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L -//SDMA1_GB_ADDR_CONFIG -#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 -#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc -#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L -#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L -#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA1_GB_ADDR_CONFIG_READ -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 -#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 -#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L -#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L -#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L -#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L -//SDMA1_RB_RPTR_FETCH_HI -#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 -#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL -//SDMA1_RB_RPTR_FETCH -#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 -#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL -//SDMA1_IB_OFFSET_FETCH -#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 -#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL -//SDMA1_PROGRAM -#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 -#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL -//SDMA1_STATUS_REG -#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 -#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 -#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 -#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 -#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 -#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 -#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 -#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 -#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 -#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 -#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb -#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc -#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd -#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe -#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 -#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 -#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 -#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 -#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a -#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b -#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c -#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e -#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f -#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L -#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L -#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L -#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L -#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L -#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L -#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L -#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L -#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L -#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L -#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L -#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L -#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L -#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L -#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L -#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L -#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L -#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L -#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L -#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L -#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L -#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L -#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L -#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L -#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L -#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L -#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L -#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L -#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L -//SDMA1_STATUS1_REG -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 -#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 -#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 -#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 -#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 -#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa -#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd -#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe -#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf -#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 -#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 -#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L -#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L -#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L -#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L -#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L -#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L -#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L -#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L -#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L -#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L -#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L -#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L -#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L -#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L -//SDMA1_RD_BURST_CNTL -#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 -#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L -//SDMA1_HBM_PAGE_CONFIG -#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 -#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L -//SDMA1_UCODE_CHECKSUM -#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 -#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL -//SDMA1_F32_CNTL -#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 -#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 -#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L -#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L -//SDMA1_FREEZE -#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 -#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 -#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 -#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 -#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L -#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L -#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L -#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L -//SDMA1_PHASE0_QUANTUM -#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L -//SDMA1_PHASE1_QUANTUM -#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L -//SDMA1_EDC_CONFIG -#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 -#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L -#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L -//SDMA1_BA_THRESHOLD -#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 -#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 -#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL -#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L -//SDMA1_ID -#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 -#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL -//SDMA1_VERSION -#define SDMA1_VERSION__MINVER__SHIFT 0x0 -#define SDMA1_VERSION__MAJVER__SHIFT 0x8 -#define SDMA1_VERSION__REV__SHIFT 0x10 -#define SDMA1_VERSION__MINVER_MASK 0x0000007FL -#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L -#define SDMA1_VERSION__REV_MASK 0x003F0000L -//SDMA1_EDC_COUNTER -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 -#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 -#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 -#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe -#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf -#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L -#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L -#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L -#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L -#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L -#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L -#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L -#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L -#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L -//SDMA1_EDC_COUNTER_CLEAR -#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 -#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L -//SDMA1_STATUS2_REG -#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 -#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 -#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 -#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L -#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL -#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L -//SDMA1_ATOMIC_CNTL -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f -#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL -#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L -//SDMA1_ATOMIC_PREOP_LO -#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 -#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL -//SDMA1_ATOMIC_PREOP_HI -#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 -#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_CNTL -#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 -#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 -#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb -#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe -#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 -#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d -#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L -#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL -#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L -#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L -#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L -#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L -//SDMA1_UTCL1_WATERMK -#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 -#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa -#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 -#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a -#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL -#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L -#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L -#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L -//SDMA1_UTCL1_RD_STATUS -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 -#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 -#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a -#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d -#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e -#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L -#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L -#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L -#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L -#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L -#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L -//SDMA1_UTCL1_WR_STATUS -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 -#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 -#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 -#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 -#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 -#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 -#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L -#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L -#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L -#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L -#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L -#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L -#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L -#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L -#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L -#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L -#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L -#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L -#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L -#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L -//SDMA1_UTCL1_INV0 -#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 -#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 -#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 -#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 -#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 -#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 -#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 -#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 -#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 -#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 -#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa -#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb -#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc -#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c -#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L -#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L -#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L -#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L -#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L -#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L -#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L -#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L -#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L -#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L -#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L -#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L -#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L -#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L -//SDMA1_UTCL1_INV1 -#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 -#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_INV2 -#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 -#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_RD_XNACK0 -#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_RD_XNACK1 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA1_UTCL1_WR_XNACK0 -#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 -#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL -//SDMA1_UTCL1_WR_XNACK1 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 -#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a -#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L -#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L -#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L -//SDMA1_UTCL1_TIMEOUT -#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 -#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 -#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL -#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L -//SDMA1_UTCL1_PAGE -#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 -#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 -#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 -#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 -#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L -#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL -#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L -#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L -//SDMA1_POWER_CNTL_IDLE -#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 -#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 -#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 -#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL -#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L -#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L -//SDMA1_RELAX_ORDERING_LUT -#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 -#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 -#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 -#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 -#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 -#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 -#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 -#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa -#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb -#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc -#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd -#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe -#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b -#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c -#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d -#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e -#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f -#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L -#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L -#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L -#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L -#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L -#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L -#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L -#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L -#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L -#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L -#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L -#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L -#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L -#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L -#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L -#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L -//SDMA1_CHICKEN_BITS_2 -#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 -#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL -//SDMA1_STATUS3_REG -#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 -#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 -#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 -#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL -#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L -#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L -//SDMA1_PHYSICAL_ADDR_LO -#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 -#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 -#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 -#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc -#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L -#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L -#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L -#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L -//SDMA1_PHYSICAL_ADDR_HI -#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL -//SDMA1_PHASE2_QUANTUM -#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 -#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 -#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e -#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL -#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L -#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L -//SDMA1_ERROR_LOG -#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 -#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 -#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL -#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L -//SDMA1_PUB_DUMMY_REG0 -#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL -//SDMA1_PUB_DUMMY_REG1 -#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL -//SDMA1_PUB_DUMMY_REG2 -#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL -//SDMA1_PUB_DUMMY_REG3 -#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 -#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL -//SDMA1_F32_COUNTER -#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 -#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL -//SDMA1_UNBREAKABLE -#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 -#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L -//SDMA1_PERFMON_CNTL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 -#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb -#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc -#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L -#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL -#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L -#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L -#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L -//SDMA1_PERFCOUNTER0_RESULT -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA1_PERFCOUNTER1_RESULT -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 -#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL -//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L -#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L -//SDMA1_CRD_CNTL -#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 -#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd -#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L -#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L -//SDMA1_MMHUB_TRUSTLVL -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L -#define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L -//SDMA1_GPU_IOV_VIOLATION_LOG -#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 -#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 -#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 -#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 -#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 -#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L -#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L -#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL -#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L -#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L -//SDMA1_ULV_CNTL -#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 -#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d -#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e -#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f -#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL -#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L -#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L -#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L -//SDMA1_EA_DBIT_ADDR_DATA -#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 -#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL -//SDMA1_EA_DBIT_ADDR_INDEX -#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 -#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L -//SDMA1_GFX_RB_CNTL -#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_GFX_RB_BASE -#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_BASE_HI -#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_GFX_RB_RPTR -#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_RPTR_HI -#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR -#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_HI -#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_POLL_CNTL -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_GFX_RB_RPTR_ADDR_HI -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_RPTR_ADDR_LO -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_GFX_IB_CNTL -#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_GFX_IB_RPTR -#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_GFX_IB_OFFSET -#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_GFX_IB_BASE_LO -#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_GFX_IB_BASE_HI -#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_IB_SIZE -#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_GFX_SKIP_CNTL -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_GFX_CONTEXT_STATUS -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_GFX_DOORBELL -#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_GFX_CONTEXT_CNTL -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 -#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L -//SDMA1_GFX_STATUS -#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_GFX_DOORBELL_LOG -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_GFX_WATERMARK -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_GFX_DOORBELL_OFFSET -#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_GFX_CSA_ADDR_LO -#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_GFX_CSA_ADDR_HI -#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_IB_SUB_REMAIN -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_GFX_PREEMPT -#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_GFX_DUMMY_REG -#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_GFX_RB_AQL_CNTL -#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_GFX_MINOR_PTR_UPDATE -#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_GFX_MIDCMD_DATA0 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA1 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA2 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA3 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA4 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA5 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA6 -#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA7 -#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_DATA8 -#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_GFX_MIDCMD_CNTL -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA1_PAGE_RB_CNTL -#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_PAGE_RB_BASE -#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_BASE_HI -#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_PAGE_RB_RPTR -#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_RPTR_HI -#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR -#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_HI -#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_POLL_CNTL -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_PAGE_RB_RPTR_ADDR_HI -#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_RPTR_ADDR_LO -#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_PAGE_IB_CNTL -#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_PAGE_IB_RPTR -#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_PAGE_IB_OFFSET -#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_PAGE_IB_BASE_LO -#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_PAGE_IB_BASE_HI -#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_IB_SIZE -#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_PAGE_SKIP_CNTL -#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_PAGE_CONTEXT_STATUS -#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_PAGE_DOORBELL -#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_PAGE_STATUS -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_PAGE_DOORBELL_LOG -#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_PAGE_WATERMARK -#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_PAGE_DOORBELL_OFFSET -#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_PAGE_CSA_ADDR_LO -#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_PAGE_CSA_ADDR_HI -#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_IB_SUB_REMAIN -#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_PAGE_PREEMPT -#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_PAGE_DUMMY_REG -#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_PAGE_RB_AQL_CNTL -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_PAGE_MINOR_PTR_UPDATE -#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_PAGE_MIDCMD_DATA0 -#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA1 -#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA2 -#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA3 -#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA4 -#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA5 -#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA6 -#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA7 -#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_DATA8 -#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_PAGE_MIDCMD_CNTL -#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA1_RLC0_RB_CNTL -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_RLC0_RB_BASE -#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_BASE_HI -#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_RLC0_RB_RPTR -#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_RPTR_HI -#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR -#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_HI -#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_POLL_CNTL -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_RLC0_RB_RPTR_ADDR_HI -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_RPTR_ADDR_LO -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC0_IB_CNTL -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_RLC0_IB_RPTR -#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC0_IB_OFFSET -#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC0_IB_BASE_LO -#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_RLC0_IB_BASE_HI -#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_IB_SIZE -#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_RLC0_SKIP_CNTL -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_RLC0_CONTEXT_STATUS -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_RLC0_DOORBELL -#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_RLC0_STATUS -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_RLC0_DOORBELL_LOG -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_RLC0_WATERMARK -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_RLC0_DOORBELL_OFFSET -#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_RLC0_CSA_ADDR_LO -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC0_CSA_ADDR_HI -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_IB_SUB_REMAIN -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_RLC0_PREEMPT -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_RLC0_DUMMY_REG -#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC0_RB_AQL_CNTL -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_RLC0_MINOR_PTR_UPDATE -#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_RLC0_MIDCMD_DATA0 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA1 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA2 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA3 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA4 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA5 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA6 -#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA7 -#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_DATA8 -#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_RLC0_MIDCMD_CNTL -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L -//SDMA1_RLC1_RB_CNTL -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 -#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 -#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 -#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL -#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L -#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L -#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L -#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L -//SDMA1_RLC1_RB_BASE -#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_BASE_HI -#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL -//SDMA1_RLC1_RB_RPTR -#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_RPTR_HI -#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR -#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_HI -#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_POLL_CNTL -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L -#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L -//SDMA1_RLC1_RB_RPTR_ADDR_HI -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_RPTR_ADDR_LO -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC1_IB_CNTL -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 -#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 -#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L -#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L -#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L -//SDMA1_RLC1_IB_RPTR -#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 -#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC1_IB_OFFSET -#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL -//SDMA1_RLC1_IB_BASE_LO -#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 -#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L -//SDMA1_RLC1_IB_BASE_HI -#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_IB_SIZE -#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 -#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL -//SDMA1_RLC1_SKIP_CNTL -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 -#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL -//SDMA1_RLC1_CONTEXT_STATUS -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa -#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L -#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L -#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L -#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L -#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L -#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L -//SDMA1_RLC1_DOORBELL -#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c -#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e -#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L -#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L -//SDMA1_RLC1_STATUS -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL -#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L -//SDMA1_RLC1_DOORBELL_LOG -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 -#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 -#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L -#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL -//SDMA1_RLC1_WATERMARK -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 -#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL -#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L -//SDMA1_RLC1_DOORBELL_OFFSET -#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 -#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL -//SDMA1_RLC1_CSA_ADDR_LO -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC1_CSA_ADDR_HI -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_IB_SUB_REMAIN -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 -#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL -//SDMA1_RLC1_PREEMPT -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 -#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L -//SDMA1_RLC1_DUMMY_REG -#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 -#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL -//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 -#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL -//SDMA1_RLC1_RB_AQL_CNTL -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 -#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L -#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL -#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L -//SDMA1_RLC1_MINOR_PTR_UPDATE -#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 -#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L -//SDMA1_RLC1_MIDCMD_DATA0 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA1 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA2 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA3 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA4 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA5 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA6 -#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA7 -#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_DATA8 -#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL -//SDMA1_RLC1_MIDCMD_CNTL -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 -#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L -#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L -#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L -#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h deleted file mode 100644 index 5c186c2e8739..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _smuio_9_0_DEFAULT_HEADER -#define _smuio_9_0_DEFAULT_HEADER - - -// addressBlock: smuio_smuio_SmuSmuioDec -#define mmROM_CNTL_DEFAULT 0x00000000 -#define mmROM_STATUS_DEFAULT 0x00000000 -#define mmCGTT_ROM_CLK_CTRL0_DEFAULT 0xc0000100 -#define mmROM_INDEX_DEFAULT 0x00000000 -#define mmROM_DATA_DEFAULT 0x00000000 -#define mmROM_START_DEFAULT 0x00000000 -#define mmROM_SW_CNTL_DEFAULT 0x00000000 -#define mmROM_SW_STATUS_DEFAULT 0x00000000 -#define mmROM_SW_COMMAND_DEFAULT 0x00000000 -#define mmROM_SW_DATA_1_DEFAULT 0x00000000 -#define mmROM_SW_DATA_2_DEFAULT 0x00000000 -#define mmROM_SW_DATA_3_DEFAULT 0x00000000 -#define mmROM_SW_DATA_4_DEFAULT 0x00000000 -#define mmROM_SW_DATA_5_DEFAULT 0x00000000 -#define mmROM_SW_DATA_6_DEFAULT 0x00000000 -#define mmROM_SW_DATA_7_DEFAULT 0x00000000 -#define mmROM_SW_DATA_8_DEFAULT 0x00000000 -#define mmROM_SW_DATA_9_DEFAULT 0x00000000 -#define mmROM_SW_DATA_10_DEFAULT 0x00000000 -#define mmROM_SW_DATA_11_DEFAULT 0x00000000 -#define mmROM_SW_DATA_12_DEFAULT 0x00000000 -#define mmROM_SW_DATA_13_DEFAULT 0x00000000 -#define mmROM_SW_DATA_14_DEFAULT 0x00000000 -#define mmROM_SW_DATA_15_DEFAULT 0x00000000 -#define mmROM_SW_DATA_16_DEFAULT 0x00000000 -#define mmROM_SW_DATA_17_DEFAULT 0x00000000 -#define mmROM_SW_DATA_18_DEFAULT 0x00000000 -#define mmROM_SW_DATA_19_DEFAULT 0x00000000 -#define mmROM_SW_DATA_20_DEFAULT 0x00000000 -#define mmROM_SW_DATA_21_DEFAULT 0x00000000 -#define mmROM_SW_DATA_22_DEFAULT 0x00000000 -#define mmROM_SW_DATA_23_DEFAULT 0x00000000 -#define mmROM_SW_DATA_24_DEFAULT 0x00000000 -#define mmROM_SW_DATA_25_DEFAULT 0x00000000 -#define mmROM_SW_DATA_26_DEFAULT 0x00000000 -#define mmROM_SW_DATA_27_DEFAULT 0x00000000 -#define mmROM_SW_DATA_28_DEFAULT 0x00000000 -#define mmROM_SW_DATA_29_DEFAULT 0x00000000 -#define mmROM_SW_DATA_30_DEFAULT 0x00000000 -#define mmROM_SW_DATA_31_DEFAULT 0x00000000 -#define mmROM_SW_DATA_32_DEFAULT 0x00000000 -#define mmROM_SW_DATA_33_DEFAULT 0x00000000 -#define mmROM_SW_DATA_34_DEFAULT 0x00000000 -#define mmROM_SW_DATA_35_DEFAULT 0x00000000 -#define mmROM_SW_DATA_36_DEFAULT 0x00000000 -#define mmROM_SW_DATA_37_DEFAULT 0x00000000 -#define mmROM_SW_DATA_38_DEFAULT 0x00000000 -#define mmROM_SW_DATA_39_DEFAULT 0x00000000 -#define mmROM_SW_DATA_40_DEFAULT 0x00000000 -#define mmROM_SW_DATA_41_DEFAULT 0x00000000 -#define mmROM_SW_DATA_42_DEFAULT 0x00000000 -#define mmROM_SW_DATA_43_DEFAULT 0x00000000 -#define mmROM_SW_DATA_44_DEFAULT 0x00000000 -#define mmROM_SW_DATA_45_DEFAULT 0x00000000 -#define mmROM_SW_DATA_46_DEFAULT 0x00000000 -#define mmROM_SW_DATA_47_DEFAULT 0x00000000 -#define mmROM_SW_DATA_48_DEFAULT 0x00000000 -#define mmROM_SW_DATA_49_DEFAULT 0x00000000 -#define mmROM_SW_DATA_50_DEFAULT 0x00000000 -#define mmROM_SW_DATA_51_DEFAULT 0x00000000 -#define mmROM_SW_DATA_52_DEFAULT 0x00000000 -#define mmROM_SW_DATA_53_DEFAULT 0x00000000 -#define mmROM_SW_DATA_54_DEFAULT 0x00000000 -#define mmROM_SW_DATA_55_DEFAULT 0x00000000 -#define mmROM_SW_DATA_56_DEFAULT 0x00000000 -#define mmROM_SW_DATA_57_DEFAULT 0x00000000 -#define mmROM_SW_DATA_58_DEFAULT 0x00000000 -#define mmROM_SW_DATA_59_DEFAULT 0x00000000 -#define mmROM_SW_DATA_60_DEFAULT 0x00000000 -#define mmROM_SW_DATA_61_DEFAULT 0x00000000 -#define mmROM_SW_DATA_62_DEFAULT 0x00000000 -#define mmROM_SW_DATA_63_DEFAULT 0x00000000 -#define mmROM_SW_DATA_64_DEFAULT 0x00000000 - -#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h deleted file mode 100644 index 48963caac534..000000000000 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (C) 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN - * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef _uvd_7_0_DEFAULT_HEADER -#define _uvd_7_0_DEFAULT_HEADER - - -// addressBlock: uvd0_uvd_pg_dec -#define mmUVD_POWER_STATUS_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_CNTL_DEFAULT 0x01000101 -#define mmUVD_DPG_RBC_RB_BASE_LOW_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_BASE_HIGH_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_DPG_RBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_DPG_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 - - -// addressBlock: uvd0_uvdnpdec -#define mmUVD_JPEG_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_GPCOM_VCPU_CMD_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA0_DEFAULT 0x00000000 -#define mmUVD_GPCOM_VCPU_DATA1_DEFAULT 0x00000000 -#define mmUVD_UDEC_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DB_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_UDEC_DBW_ADDR_CONFIG_DEFAULT 0x22010010 -#define mmUVD_SUVD_CGC_GATE_DEFAULT 0x00000000 -#define mmUVD_SUVD_CGC_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_POWER_STATUS_U_DEFAULT 0x00000000 -#define mmUVD_NO_OP_DEFAULT 0x00000000 -#define mmUVD_GP_SCRATCH8_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI2_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE2_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR2_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 - - -// addressBlock: uvd0_uvddec -#define mmUVD_SEMA_CNTL_DEFAULT 0x00000003 -#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_DEFAULT 0x00000000 -#define mmUVD_JRBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RB_RPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_WPTR3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_LO3_DEFAULT 0x00000000 -#define mmUVD_RB_BASE_HI3_DEFAULT 0x00000000 -#define mmUVD_RB_SIZE3_DEFAULT 0x00000000 -#define mmJPEG_CGC_GATE_DEFAULT 0x00300000 -#define mmUVD_CTX_INDEX_DEFAULT 0x00000000 -#define mmUVD_CTX_DATA_DEFAULT 0x00000000 -#define mmUVD_CGC_GATE_DEFAULT 0x000fffff -#define mmUVD_CGC_CTRL_DEFAULT 0x1fff018d -#define mmUVD_GP_SCRATCH4_DEFAULT 0x00000000 -#define mmUVD_LMI_CTRL2_DEFAULT 0x003e0000 -#define mmUVD_MASTINT_EN_DEFAULT 0x00000000 -#define mmJPEG_CGC_CTRL_DEFAULT 0x0000018d -#define mmUVD_LMI_CTRL_DEFAULT 0x00104340 -#define mmUVD_LMI_VM_CTRL_DEFAULT 0x00000000 -#define mmUVD_LMI_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_MP_SWAP_CNTL_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXA0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXA1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUXB0_DEFAULT 0x00002040 -#define mmUVD_MPC_SET_MUXB1_DEFAULT 0x00000000 -#define mmUVD_MPC_SET_MUX_DEFAULT 0x00000088 -#define mmUVD_MPC_SET_ALU_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE0_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE1_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CACHE_SIZE2_DEFAULT 0x00000000 -#define mmUVD_VCPU_CNTL_DEFAULT 0x0ff20000 -#define mmUVD_SOFT_RESET_DEFAULT 0x00000008 -#define mmUVD_LMI_RBC_IB_VMID_DEFAULT 0x00000000 -#define mmUVD_RBC_IB_SIZE_DEFAULT 0x00000000 -#define mmUVD_LMI_RBC_RB_VMID_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_RPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_WPTR_CNTL_DEFAULT 0x00000000 -#define mmUVD_RBC_RB_CNTL_DEFAULT 0x01000101 -#define mmUVD_RBC_RB_RPTR_ADDR_DEFAULT 0x00000000 -#define mmUVD_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_TIMEOUT_STATUS_DEFAULT 0x00000000 -#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_DEFAULT 0x02000000 -#define mmUVD_CONTEXT_ID_DEFAULT 0x00000000 -#define mmUVD_CONTEXT_ID2_DEFAULT 0x00000000 - - -#endif diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h index 7343aed4d019..721473199921 100644 --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h @@ -25,6 +25,145 @@ #define PP_MAX_CLOCK_LEVELS 8 +enum amd_pp_display_config_type{ + AMD_PP_DisplayConfigType_None = 0, + AMD_PP_DisplayConfigType_DP54 , + AMD_PP_DisplayConfigType_DP432 , + AMD_PP_DisplayConfigType_DP324 , + AMD_PP_DisplayConfigType_DP27, + AMD_PP_DisplayConfigType_DP243, + AMD_PP_DisplayConfigType_DP216, + AMD_PP_DisplayConfigType_DP162, + AMD_PP_DisplayConfigType_HDMI6G , + AMD_PP_DisplayConfigType_HDMI297 , + AMD_PP_DisplayConfigType_HDMI162, + AMD_PP_DisplayConfigType_LVDS, + AMD_PP_DisplayConfigType_DVI, + AMD_PP_DisplayConfigType_WIRELESS, + AMD_PP_DisplayConfigType_VGA +}; + +struct single_display_configuration +{ + uint32_t controller_index; + uint32_t controller_id; + uint32_t signal_type; + uint32_t display_state; + /* phy id for the primary internal transmitter */ + uint8_t primary_transmitter_phyi_d; + /* bitmap with the active lanes */ + uint8_t primary_transmitter_active_lanemap; + /* phy id for the secondary internal transmitter (for dual-link dvi) */ + uint8_t secondary_transmitter_phy_id; + /* bitmap with the active lanes */ + uint8_t secondary_transmitter_active_lanemap; + /* misc phy settings for SMU. */ + uint32_t config_flags; + uint32_t display_type; + uint32_t view_resolution_cx; + uint32_t view_resolution_cy; + enum amd_pp_display_config_type displayconfigtype; + uint32_t vertical_refresh; /* for active display */ +}; + +#define MAX_NUM_DISPLAY 32 + +struct amd_pp_display_configuration { + bool nb_pstate_switch_disable;/* controls NB PState switch */ + bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ + bool cpu_pstate_disable; + uint32_t cpu_pstate_separation_time; + + uint32_t num_display; /* total number of display*/ + uint32_t num_path_including_non_display; + uint32_t crossfire_display_index; + uint32_t min_mem_set_clock; + uint32_t min_core_set_clock; + /* unit 10KHz x bit*/ + uint32_t min_bus_bandwidth; + /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ + uint32_t min_core_set_clock_in_sr; + + struct single_display_configuration displays[MAX_NUM_DISPLAY]; + + uint32_t vrefresh; /* for active display*/ + + uint32_t min_vblank_time; /* for active display*/ + bool multi_monitor_in_sync; + /* Controller Index of primary display - used in MCLK SMC switching hang + * SW Workaround*/ + uint32_t crtc_index; + /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ + uint32_t line_time_in_us; + bool invalid_vblank_time; + + uint32_t display_clk; + /* + * for given display configuration if multimonitormnsync == false then + * Memory clock DPMS with this latency or below is allowed, DPMS with + * higher latency not allowed. + */ + uint32_t dce_tolerable_mclk_in_active_latency; + uint32_t min_dcef_set_clk; + uint32_t min_dcef_deep_sleep_set_clk; +}; + +struct amd_pp_simple_clock_info { + uint32_t engine_max_clock; + uint32_t memory_max_clock; + uint32_t level; +}; + +enum PP_DAL_POWERLEVEL { + PP_DAL_POWERLEVEL_INVALID = 0, + PP_DAL_POWERLEVEL_ULTRALOW, + PP_DAL_POWERLEVEL_LOW, + PP_DAL_POWERLEVEL_NOMINAL, + PP_DAL_POWERLEVEL_PERFORMANCE, + + PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, + PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, + PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, + PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, + PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, + PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, + PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, + PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, +}; + +struct amd_pp_clock_info { + uint32_t min_engine_clock; + uint32_t max_engine_clock; + uint32_t min_memory_clock; + uint32_t max_memory_clock; + uint32_t min_bus_bandwidth; + uint32_t max_bus_bandwidth; + uint32_t max_engine_clock_in_sr; + uint32_t min_engine_clock_in_sr; + enum PP_DAL_POWERLEVEL max_clocks_state; +}; + +enum amd_pp_clock_type { + amd_pp_disp_clock = 1, + amd_pp_sys_clock, + amd_pp_mem_clock, + amd_pp_dcef_clock, + amd_pp_soc_clock, + amd_pp_pixel_clock, + amd_pp_phy_clock, + amd_pp_dcf_clock, + amd_pp_dpp_clock, + amd_pp_f_clock = amd_pp_dcef_clock, +}; + +#define MAX_NUM_CLOCKS 16 + +struct amd_pp_clocks { + uint32_t count; + uint32_t clock[MAX_NUM_CLOCKS]; + uint32_t latency[MAX_NUM_CLOCKS]; +}; + struct pp_clock_with_latency { uint32_t clocks_in_khz; uint32_t latency_in_us; @@ -45,6 +184,11 @@ struct pp_clock_levels_with_voltage { struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS]; }; +struct pp_display_clock_request { + enum amd_pp_clock_type clock_type; + uint32_t clock_freq_in_khz; +}; + #define PP_MAX_WM_SETS 4 enum pp_wm_set_id { diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h new file mode 100644 index 000000000000..ed27626dff14 --- /dev/null +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -0,0 +1,294 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __KGD_PP_INTERFACE_H__ +#define __KGD_PP_INTERFACE_H__ + +extern const struct amd_ip_funcs pp_ip_funcs; +extern const struct amd_pm_funcs pp_dpm_funcs; + +struct amd_vce_state { + /* vce clocks */ + u32 evclk; + u32 ecclk; + /* gpu clocks */ + u32 sclk; + u32 mclk; + u8 clk_idx; + u8 pstate; +}; + + +enum amd_dpm_forced_level { + AMD_DPM_FORCED_LEVEL_AUTO = 0x1, + AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, + AMD_DPM_FORCED_LEVEL_LOW = 0x4, + AMD_DPM_FORCED_LEVEL_HIGH = 0x8, + AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, + AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, + AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, + AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, +}; + +enum amd_pm_state_type { + /* not used for dpm */ + POWER_STATE_TYPE_DEFAULT, + POWER_STATE_TYPE_POWERSAVE, + /* user selectable states */ + POWER_STATE_TYPE_BATTERY, + POWER_STATE_TYPE_BALANCED, + POWER_STATE_TYPE_PERFORMANCE, + /* internal states */ + POWER_STATE_TYPE_INTERNAL_UVD, + POWER_STATE_TYPE_INTERNAL_UVD_SD, + POWER_STATE_TYPE_INTERNAL_UVD_HD, + POWER_STATE_TYPE_INTERNAL_UVD_HD2, + POWER_STATE_TYPE_INTERNAL_UVD_MVC, + POWER_STATE_TYPE_INTERNAL_BOOT, + POWER_STATE_TYPE_INTERNAL_THERMAL, + POWER_STATE_TYPE_INTERNAL_ACPI, + POWER_STATE_TYPE_INTERNAL_ULV, + POWER_STATE_TYPE_INTERNAL_3DPERF, +}; + +#define AMD_MAX_VCE_LEVELS 6 + +enum amd_vce_level { + AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ + AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ + AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ + AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ + AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ + AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ +}; + +enum amd_pp_profile_type { + AMD_PP_GFX_PROFILE, + AMD_PP_COMPUTE_PROFILE, +}; + +struct amd_pp_profile { + enum amd_pp_profile_type type; + uint32_t min_sclk; + uint32_t min_mclk; + uint16_t activity_threshold; + uint8_t up_hyst; + uint8_t down_hyst; +}; + +enum amd_fan_ctrl_mode { + AMD_FAN_CTRL_NONE = 0, + AMD_FAN_CTRL_MANUAL = 1, + AMD_FAN_CTRL_AUTO = 2, +}; + +enum pp_clock_type { + PP_SCLK, + PP_MCLK, + PP_PCIE, +}; + +enum amd_pp_sensors { + AMDGPU_PP_SENSOR_GFX_SCLK = 0, + AMDGPU_PP_SENSOR_VDDNB, + AMDGPU_PP_SENSOR_VDDGFX, + AMDGPU_PP_SENSOR_UVD_VCLK, + AMDGPU_PP_SENSOR_UVD_DCLK, + AMDGPU_PP_SENSOR_VCE_ECCLK, + AMDGPU_PP_SENSOR_GPU_LOAD, + AMDGPU_PP_SENSOR_GFX_MCLK, + AMDGPU_PP_SENSOR_GPU_TEMP, + AMDGPU_PP_SENSOR_VCE_POWER, + AMDGPU_PP_SENSOR_UVD_POWER, + AMDGPU_PP_SENSOR_GPU_POWER, +}; + +enum amd_pp_task { + AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, + AMD_PP_TASK_ENABLE_USER_STATE, + AMD_PP_TASK_READJUST_POWER_STATE, + AMD_PP_TASK_COMPLETE_INIT, + AMD_PP_TASK_MAX +}; + +struct amd_pp_init { + struct cgs_device *device; + uint32_t chip_family; + uint32_t chip_id; + bool pm_en; + uint32_t feature_mask; +}; + + + +enum { + PP_GROUP_UNKNOWN = 0, + PP_GROUP_GFX = 1, + PP_GROUP_SYS, + PP_GROUP_MAX +}; + +struct pp_states_info { + uint32_t nums; + uint32_t states[16]; +}; + +struct pp_gpu_power { + uint32_t vddc_power; + uint32_t vddci_power; + uint32_t max_gpu_power; + uint32_t average_gpu_power; +}; + +#define PP_GROUP_MASK 0xF0000000 +#define PP_GROUP_SHIFT 28 + +#define PP_BLOCK_MASK 0x0FFFFF00 +#define PP_BLOCK_SHIFT 8 + +#define PP_BLOCK_GFX_CG 0x01 +#define PP_BLOCK_GFX_MG 0x02 +#define PP_BLOCK_GFX_3D 0x04 +#define PP_BLOCK_GFX_RLC 0x08 +#define PP_BLOCK_GFX_CP 0x10 +#define PP_BLOCK_SYS_BIF 0x01 +#define PP_BLOCK_SYS_MC 0x02 +#define PP_BLOCK_SYS_ROM 0x04 +#define PP_BLOCK_SYS_DRM 0x08 +#define PP_BLOCK_SYS_HDP 0x10 +#define PP_BLOCK_SYS_SDMA 0x20 + +#define PP_STATE_MASK 0x0000000F +#define PP_STATE_SHIFT 0 +#define PP_STATE_SUPPORT_MASK 0x000000F0 +#define PP_STATE_SUPPORT_SHIFT 0 + +#define PP_STATE_CG 0x01 +#define PP_STATE_LS 0x02 +#define PP_STATE_DS 0x04 +#define PP_STATE_SD 0x08 +#define PP_STATE_SUPPORT_CG 0x10 +#define PP_STATE_SUPPORT_LS 0x20 +#define PP_STATE_SUPPORT_DS 0x40 +#define PP_STATE_SUPPORT_SD 0x80 + +#define PP_CG_MSG_ID(group, block, support, state) \ + ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ + (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) + +struct seq_file; +enum amd_pp_clock_type; +struct amd_pp_simple_clock_info; +struct amd_pp_display_configuration; +struct amd_pp_clock_info; +struct pp_display_clock_request; +struct pp_wm_sets_with_clock_ranges_soc15; +struct pp_clock_levels_with_voltage; +struct pp_clock_levels_with_latency; +struct amd_pp_clocks; + +struct amd_pm_funcs { +/* export for dpm on ci and si */ + int (*pre_set_power_state)(void *handle); + int (*set_power_state)(void *handle); + void (*post_set_power_state)(void *handle); + void (*display_configuration_changed)(void *handle); + void (*print_power_state)(void *handle, void *ps); + bool (*vblank_too_short)(void *handle); + void (*enable_bapm)(void *handle, bool enable); + int (*check_state_equal)(void *handle, + void *cps, + void *rps, + bool *equal); +/* export for sysfs */ + int (*get_temperature)(void *handle); + void (*set_fan_control_mode)(void *handle, u32 mode); + u32 (*get_fan_control_mode)(void *handle); + int (*set_fan_speed_percent)(void *handle, u32 speed); + int (*get_fan_speed_percent)(void *handle, u32 *speed); + int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); + int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); + int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); + int (*get_sclk_od)(void *handle); + int (*set_sclk_od)(void *handle, uint32_t value); + int (*get_mclk_od)(void *handle); + int (*set_mclk_od)(void *handle, uint32_t value); + int (*read_sensor)(void *handle, int idx, void *value, int *size); + enum amd_dpm_forced_level (*get_performance_level)(void *handle); + enum amd_pm_state_type (*get_current_power_state)(void *handle); + int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); + int (*get_pp_num_states)(void *handle, struct pp_states_info *data); + int (*get_pp_table)(void *handle, char **table); + int (*set_pp_table)(void *handle, const char *buf, size_t size); + void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); + + int (*reset_power_profile_state)(void *handle, + struct amd_pp_profile *request); + int (*get_power_profile_state)(void *handle, + struct amd_pp_profile *query); + int (*set_power_profile_state)(void *handle, + struct amd_pp_profile *request); + int (*switch_power_profile)(void *handle, + enum amd_pp_profile_type type); +/* export to amdgpu */ + void (*powergate_uvd)(void *handle, bool gate); + void (*powergate_vce)(void *handle, bool gate); + struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); + int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, + void *input, void *output); + int (*load_firmware)(void *handle); + int (*wait_for_fw_loading_complete)(void *handle); + int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); + int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low, + uint32_t virtual_addr_hi, + uint32_t mc_addr_low, + uint32_t mc_addr_hi, + uint32_t size); +/* export to DC */ + u32 (*get_sclk)(void *handle, bool low); + u32 (*get_mclk)(void *handle, bool low); + int (*display_configuration_change)(void *handle, + const struct amd_pp_display_configuration *input); + int (*get_display_power_level)(void *handle, + struct amd_pp_simple_clock_info *output); + int (*get_current_clocks)(void *handle, + struct amd_pp_clock_info *clocks); + int (*get_clock_by_type)(void *handle, + enum amd_pp_clock_type type, + struct amd_pp_clocks *clocks); + int (*get_clock_by_type_with_latency)(void *handle, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_latency *clocks); + int (*get_clock_by_type_with_voltage)(void *handle, + enum amd_pp_clock_type type, + struct pp_clock_levels_with_voltage *clocks); + int (*set_watermarks_for_clocks_ranges)(void *handle, + struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); + int (*display_clock_voltage_request)(void *handle, + struct pp_display_clock_request *clock); + int (*get_display_mode_validation_clocks)(void *handle, + struct amd_pp_simple_clock_info *clocks); +}; + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h b/drivers/gpu/drm/amd/include/soc15ip.h index 1767db69df7a..1767db69df7a 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h +++ b/drivers/gpu/drm/amd/include/soc15ip.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h b/drivers/gpu/drm/amd/include/vega10_enum.h index c14ba65a2415..c14ba65a2415 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h +++ b/drivers/gpu/drm/amd/include/vega10_enum.h diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index c7e34128cbde..9d3bdada79d5 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -122,7 +122,7 @@ static int pp_sw_init(void *handle) ret = hwmgr->smumgr_funcs->smu_init(hwmgr); - pr_info("amdgpu: powerplay sw initialized\n"); + pr_debug("amdgpu: powerplay sw initialized\n"); } return ret; } @@ -788,6 +788,26 @@ static int pp_dpm_get_pp_table(void *handle, char **table) return size; } +static int amd_powerplay_reset(void *handle) +{ + struct pp_instance *instance = (struct pp_instance *)handle; + int ret; + + ret = pp_check(instance); + if (ret) + return ret; + + ret = pp_hw_fini(instance); + if (ret) + return ret; + + ret = hwmgr_hw_init(instance); + if (ret) + return ret; + + return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); +} + static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) { struct pp_hwmgr *hwmgr; @@ -1146,64 +1166,41 @@ static int pp_dpm_switch_power_profile(void *handle, return 0; } -const struct amd_pm_funcs pp_dpm_funcs = { - .get_temperature = pp_dpm_get_temperature, - .load_firmware = pp_dpm_load_fw, - .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, - .force_performance_level = pp_dpm_force_performance_level, - .get_performance_level = pp_dpm_get_performance_level, - .get_current_power_state = pp_dpm_get_current_power_state, - .get_sclk = pp_dpm_get_sclk, - .get_mclk = pp_dpm_get_mclk, - .powergate_vce = pp_dpm_powergate_vce, - .powergate_uvd = pp_dpm_powergate_uvd, - .dispatch_tasks = pp_dpm_dispatch_tasks, - .set_fan_control_mode = pp_dpm_set_fan_control_mode, - .get_fan_control_mode = pp_dpm_get_fan_control_mode, - .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, - .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, - .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, - .get_pp_num_states = pp_dpm_get_pp_num_states, - .get_pp_table = pp_dpm_get_pp_table, - .set_pp_table = pp_dpm_set_pp_table, - .force_clock_level = pp_dpm_force_clock_level, - .print_clock_levels = pp_dpm_print_clock_levels, - .get_sclk_od = pp_dpm_get_sclk_od, - .set_sclk_od = pp_dpm_set_sclk_od, - .get_mclk_od = pp_dpm_get_mclk_od, - .set_mclk_od = pp_dpm_set_mclk_od, - .read_sensor = pp_dpm_read_sensor, - .get_vce_clock_state = pp_dpm_get_vce_clock_state, - .reset_power_profile_state = pp_dpm_reset_power_profile_state, - .get_power_profile_state = pp_dpm_get_power_profile_state, - .set_power_profile_state = pp_dpm_set_power_profile_state, - .switch_power_profile = pp_dpm_switch_power_profile, - .set_clockgating_by_smu = pp_set_clockgating_by_smu, -}; - -int amd_powerplay_reset(void *handle) +static int pp_dpm_notify_smu_memory_info(void *handle, + uint32_t virtual_addr_low, + uint32_t virtual_addr_hi, + uint32_t mc_addr_low, + uint32_t mc_addr_hi, + uint32_t size) { - struct pp_instance *instance = (struct pp_instance *)handle; - int ret; + struct pp_hwmgr *hwmgr; + struct pp_instance *pp_handle = (struct pp_instance *)handle; + int ret = 0; - ret = pp_check(instance); - if (ret) - return ret; + ret = pp_check(pp_handle); - ret = pp_hw_fini(instance); if (ret) return ret; - ret = hwmgr_hw_init(instance); - if (ret) - return ret; + hwmgr = pp_handle->hwmgr; - return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL); -} + if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) { + pr_info("%s was not implemented.\n", __func__); + return -EINVAL; + } + + mutex_lock(&pp_handle->pp_lock); + + ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low, + virtual_addr_hi, mc_addr_low, mc_addr_hi, + size); -/* export this function to DAL */ + mutex_unlock(&pp_handle->pp_lock); + + return ret; +} -int amd_powerplay_display_configuration_change(void *handle, +static int pp_display_configuration_change(void *handle, const struct amd_pp_display_configuration *display_config) { struct pp_hwmgr *hwmgr; @@ -1222,7 +1219,7 @@ int amd_powerplay_display_configuration_change(void *handle, return 0; } -int amd_powerplay_get_display_power_level(void *handle, +static int pp_get_display_power_level(void *handle, struct amd_pp_simple_clock_info *output) { struct pp_hwmgr *hwmgr; @@ -1245,7 +1242,7 @@ int amd_powerplay_get_display_power_level(void *handle, return ret; } -int amd_powerplay_get_current_clocks(void *handle, +static int pp_get_current_clocks(void *handle, struct amd_pp_clock_info *clocks) { struct amd_pp_simple_clock_info simple_clocks; @@ -1299,7 +1296,7 @@ int amd_powerplay_get_current_clocks(void *handle, return 0; } -int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) +static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) { struct pp_hwmgr *hwmgr; struct pp_instance *pp_handle = (struct pp_instance *)handle; @@ -1321,7 +1318,7 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s return ret; } -int amd_powerplay_get_clock_by_type_with_latency(void *handle, +static int pp_get_clock_by_type_with_latency(void *handle, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) { @@ -1343,7 +1340,7 @@ int amd_powerplay_get_clock_by_type_with_latency(void *handle, return ret; } -int amd_powerplay_get_clock_by_type_with_voltage(void *handle, +static int pp_get_clock_by_type_with_voltage(void *handle, enum amd_pp_clock_type type, struct pp_clock_levels_with_voltage *clocks) { @@ -1368,7 +1365,7 @@ int amd_powerplay_get_clock_by_type_with_voltage(void *handle, return ret; } -int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, +static int pp_set_watermarks_for_clocks_ranges(void *handle, struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) { struct pp_hwmgr *hwmgr; @@ -1392,7 +1389,7 @@ int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, return ret; } -int amd_powerplay_display_clock_voltage_request(void *handle, +static int pp_display_clock_voltage_request(void *handle, struct pp_display_clock_request *clock) { struct pp_hwmgr *hwmgr; @@ -1415,7 +1412,7 @@ int amd_powerplay_display_clock_voltage_request(void *handle, return ret; } -int amd_powerplay_get_display_mode_validation_clocks(void *handle, +static int pp_get_display_mode_validation_clocks(void *handle, struct amd_pp_simple_clock_info *clocks) { struct pp_hwmgr *hwmgr; @@ -1441,3 +1438,48 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle, return ret; } +const struct amd_pm_funcs pp_dpm_funcs = { + .get_temperature = pp_dpm_get_temperature, + .load_firmware = pp_dpm_load_fw, + .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, + .force_performance_level = pp_dpm_force_performance_level, + .get_performance_level = pp_dpm_get_performance_level, + .get_current_power_state = pp_dpm_get_current_power_state, + .powergate_vce = pp_dpm_powergate_vce, + .powergate_uvd = pp_dpm_powergate_uvd, + .dispatch_tasks = pp_dpm_dispatch_tasks, + .set_fan_control_mode = pp_dpm_set_fan_control_mode, + .get_fan_control_mode = pp_dpm_get_fan_control_mode, + .set_fan_speed_percent = pp_dpm_set_fan_speed_percent, + .get_fan_speed_percent = pp_dpm_get_fan_speed_percent, + .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, + .get_pp_num_states = pp_dpm_get_pp_num_states, + .get_pp_table = pp_dpm_get_pp_table, + .set_pp_table = pp_dpm_set_pp_table, + .force_clock_level = pp_dpm_force_clock_level, + .print_clock_levels = pp_dpm_print_clock_levels, + .get_sclk_od = pp_dpm_get_sclk_od, + .set_sclk_od = pp_dpm_set_sclk_od, + .get_mclk_od = pp_dpm_get_mclk_od, + .set_mclk_od = pp_dpm_set_mclk_od, + .read_sensor = pp_dpm_read_sensor, + .get_vce_clock_state = pp_dpm_get_vce_clock_state, + .reset_power_profile_state = pp_dpm_reset_power_profile_state, + .get_power_profile_state = pp_dpm_get_power_profile_state, + .set_power_profile_state = pp_dpm_set_power_profile_state, + .switch_power_profile = pp_dpm_switch_power_profile, + .set_clockgating_by_smu = pp_set_clockgating_by_smu, + .notify_smu_memory_info = pp_dpm_notify_smu_memory_info, +/* export to DC */ + .get_sclk = pp_dpm_get_sclk, + .get_mclk = pp_dpm_get_mclk, + .display_configuration_change = pp_display_configuration_change, + .get_display_power_level = pp_get_display_power_level, + .get_current_clocks = pp_get_current_clocks, + .get_clock_by_type = pp_get_clock_by_type, + .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency, + .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage, + .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges, + .display_clock_voltage_request = pp_display_clock_voltage_request, + .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks, +}; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h index c6ba0d64cfb7..4112a9398163 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_overdriver.h @@ -43,4 +43,4 @@ struct phm_fuses_default { extern int pp_override_get_default_fuse_value(uint64_t key, struct phm_fuses_default *result); -#endif
\ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c index c062844b15f3..560c1c159fcc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c @@ -542,4 +542,4 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, boot_values->ulDCEFClk = frequency; return 0; -}
\ No newline at end of file +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c index a651ebcf44fd..b49d65c3e984 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c @@ -523,8 +523,7 @@ static int get_pcie_table( if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; else - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ - Disregarding the excess entries... \n"); + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); pcie_table->count = pcie_count; for (i = 0; i < pcie_count; i++) { @@ -563,8 +562,7 @@ static int get_pcie_table( if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count) pcie_count = (uint32_t)atom_pcie_table->ucNumEntries; else - pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \ - Disregarding the excess entries... \n"); + pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n"); pcie_table->count = pcie_count; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index afae32ee2b0d..c3e7e34535e8 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -394,8 +394,8 @@ static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, dep_table->entries[i].clk = ((unsigned long)table->entries[i].ucClockHigh << 16) | le16_to_cpu(table->entries[i].usClockLow); - dep_table->entries[i].v = - (unsigned long)le16_to_cpu(table->entries[i].usVoltage); + dep_table->entries[i].v = + (unsigned long)le16_to_cpu(table->entries[i].usVoltage); } *ptable = dep_table; @@ -1042,7 +1042,7 @@ static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr, static int init_overdrive_limits(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) { - int result; + int result = 0; uint8_t frev, crev; uint16_t size; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h index 9a0149370d26..ae59a3fdea8a 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h @@ -25,17 +25,17 @@ #define RAVEN_INC_H -#include "asic_reg/raven1/MP/mp_10_0_default.h" -#include "asic_reg/raven1/MP/mp_10_0_offset.h" -#include "asic_reg/raven1/MP/mp_10_0_sh_mask.h" +#include "asic_reg/mp/mp_10_0_default.h" +#include "asic_reg/mp/mp_10_0_offset.h" +#include "asic_reg/mp/mp_10_0_sh_mask.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_default.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_offset.h" -#include "asic_reg/raven1/NBIO/nbio_7_0_sh_mask.h" +#include "asic_reg/nbio/nbio_7_0_default.h" +#include "asic_reg/nbio/nbio_7_0_offset.h" +#include "asic_reg/nbio/nbio_7_0_sh_mask.h" -#include "asic_reg/raven1/THM/thm_10_0_default.h" -#include "asic_reg/raven1/THM/thm_10_0_offset.h" -#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h" +#include "asic_reg/thm/thm_10_0_default.h" +#include "asic_reg/thm/thm_10_0_offset.h" +#include "asic_reg/thm/thm_10_0_sh_mask.h" #define ixDDI_PHY_GEN_STATUS 0x3FCE8 diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index e33ec7fc5d09..8edb0c4c3876 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -4339,9 +4339,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, for (i = 0; i < pcie_table->count; i++) size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : - (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : - (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", (i == now) ? "*" : ""); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index f8d838c2c8ee..07d256d136ad 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -546,8 +546,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, } if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) - pr_info("Voltage value looks like a Leakage ID \ - but it's not patched\n"); + pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); } /** @@ -701,18 +700,14 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) table_info->vdd_dep_on_mclk; PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, - "VDD dependency on SCLK table is missing. \ - This table is mandatory", return -EINVAL); + "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, - "VDD dependency on SCLK table is empty. \ - This table is mandatory", return -EINVAL); + "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, - "VDD dependency on MCLK table is missing. \ - This table is mandatory", return -EINVAL); + "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, - "VDD dependency on MCLK table is empty. \ - This table is mandatory", return -EINVAL); + "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); table_info->max_clock_voltage_on_ac.sclk = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; @@ -3416,8 +3411,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( DPMTABLE_OD_UPDATE_SCLK)) { result = vega10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate SCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", return result); } @@ -3426,8 +3420,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( DPMTABLE_OD_UPDATE_MCLK)){ result = vega10_populate_all_memory_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate MCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", return result); } } else { @@ -3544,8 +3537,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( data->apply_optimized_settings) { result = vega10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate SCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", return result); } @@ -3553,8 +3545,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { result = vega10_populate_all_memory_levels(hwmgr); PP_ASSERT_WITH_CODE(!result, - "Failed to populate MCLK during \ - PopulateNewDPMClocksStates Function!", + "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", return result); } } @@ -4654,9 +4645,9 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, for (i = 0; i < pcie_table->count; i++) size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GB, x1" : - (pcie_table->pcie_gen[i] == 1) ? "5.0GB, x16" : - (pcie_table->pcie_gen[i] == 2) ? "8.0GB, x16" : "", + (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" : + (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" : + (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "", (i == now) ? "*" : ""); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h index 8c55eaa3c32b..faf7ac044348 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h @@ -24,21 +24,20 @@ #ifndef VEGA10_INC_H #define VEGA10_INC_H -#include "asic_reg/vega10/THM/thm_9_0_default.h" -#include "asic_reg/vega10/THM/thm_9_0_offset.h" -#include "asic_reg/vega10/THM/thm_9_0_sh_mask.h" +#include "asic_reg/thm/thm_9_0_default.h" +#include "asic_reg/thm/thm_9_0_offset.h" +#include "asic_reg/thm/thm_9_0_sh_mask.h" -#include "asic_reg/vega10/MP/mp_9_0_default.h" -#include "asic_reg/vega10/MP/mp_9_0_offset.h" -#include "asic_reg/vega10/MP/mp_9_0_sh_mask.h" +#include "asic_reg/mp/mp_9_0_offset.h" +#include "asic_reg/mp/mp_9_0_sh_mask.h" -#include "asic_reg/vega10/GC/gc_9_0_default.h" -#include "asic_reg/vega10/GC/gc_9_0_offset.h" -#include "asic_reg/vega10/GC/gc_9_0_sh_mask.h" +#include "asic_reg/gc/gc_9_0_default.h" +#include "asic_reg/gc/gc_9_0_offset.h" +#include "asic_reg/gc/gc_9_0_sh_mask.h" -#include "asic_reg/vega10/NBIO/nbio_6_1_default.h" -#include "asic_reg/vega10/NBIO/nbio_6_1_offset.h" -#include "asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h" +#include "asic_reg/nbio/nbio_6_1_default.h" +#include "asic_reg/nbio/nbio_6_1_offset.h" +#include "asic_reg/nbio/nbio_6_1_sh_mask.h" #endif diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 95932cc88460..152e70db4a81 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,280 +29,7 @@ #include "amd_shared.h" #include "cgs_common.h" #include "dm_pp_interface.h" - -extern const struct amd_ip_funcs pp_ip_funcs; -extern const struct amd_pm_funcs pp_dpm_funcs; - -enum amd_pp_sensors { - AMDGPU_PP_SENSOR_GFX_SCLK = 0, - AMDGPU_PP_SENSOR_VDDNB, - AMDGPU_PP_SENSOR_VDDGFX, - AMDGPU_PP_SENSOR_UVD_VCLK, - AMDGPU_PP_SENSOR_UVD_DCLK, - AMDGPU_PP_SENSOR_VCE_ECCLK, - AMDGPU_PP_SENSOR_GPU_LOAD, - AMDGPU_PP_SENSOR_GFX_MCLK, - AMDGPU_PP_SENSOR_GPU_TEMP, - AMDGPU_PP_SENSOR_VCE_POWER, - AMDGPU_PP_SENSOR_UVD_POWER, - AMDGPU_PP_SENSOR_GPU_POWER, -}; - -enum amd_pp_task { - AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, - AMD_PP_TASK_ENABLE_USER_STATE, - AMD_PP_TASK_READJUST_POWER_STATE, - AMD_PP_TASK_COMPLETE_INIT, - AMD_PP_TASK_MAX -}; - -struct amd_pp_init { - struct cgs_device *device; - uint32_t chip_family; - uint32_t chip_id; - bool pm_en; - uint32_t feature_mask; -}; - -enum amd_pp_display_config_type{ - AMD_PP_DisplayConfigType_None = 0, - AMD_PP_DisplayConfigType_DP54 , - AMD_PP_DisplayConfigType_DP432 , - AMD_PP_DisplayConfigType_DP324 , - AMD_PP_DisplayConfigType_DP27, - AMD_PP_DisplayConfigType_DP243, - AMD_PP_DisplayConfigType_DP216, - AMD_PP_DisplayConfigType_DP162, - AMD_PP_DisplayConfigType_HDMI6G , - AMD_PP_DisplayConfigType_HDMI297 , - AMD_PP_DisplayConfigType_HDMI162, - AMD_PP_DisplayConfigType_LVDS, - AMD_PP_DisplayConfigType_DVI, - AMD_PP_DisplayConfigType_WIRELESS, - AMD_PP_DisplayConfigType_VGA -}; - -struct single_display_configuration -{ - uint32_t controller_index; - uint32_t controller_id; - uint32_t signal_type; - uint32_t display_state; - /* phy id for the primary internal transmitter */ - uint8_t primary_transmitter_phyi_d; - /* bitmap with the active lanes */ - uint8_t primary_transmitter_active_lanemap; - /* phy id for the secondary internal transmitter (for dual-link dvi) */ - uint8_t secondary_transmitter_phy_id; - /* bitmap with the active lanes */ - uint8_t secondary_transmitter_active_lanemap; - /* misc phy settings for SMU. */ - uint32_t config_flags; - uint32_t display_type; - uint32_t view_resolution_cx; - uint32_t view_resolution_cy; - enum amd_pp_display_config_type displayconfigtype; - uint32_t vertical_refresh; /* for active display */ -}; - -#define MAX_NUM_DISPLAY 32 - -struct amd_pp_display_configuration { - bool nb_pstate_switch_disable;/* controls NB PState switch */ - bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ - bool cpu_pstate_disable; - uint32_t cpu_pstate_separation_time; - - uint32_t num_display; /* total number of display*/ - uint32_t num_path_including_non_display; - uint32_t crossfire_display_index; - uint32_t min_mem_set_clock; - uint32_t min_core_set_clock; - /* unit 10KHz x bit*/ - uint32_t min_bus_bandwidth; - /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ - uint32_t min_core_set_clock_in_sr; - - struct single_display_configuration displays[MAX_NUM_DISPLAY]; - - uint32_t vrefresh; /* for active display*/ - - uint32_t min_vblank_time; /* for active display*/ - bool multi_monitor_in_sync; - /* Controller Index of primary display - used in MCLK SMC switching hang - * SW Workaround*/ - uint32_t crtc_index; - /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ - uint32_t line_time_in_us; - bool invalid_vblank_time; - - uint32_t display_clk; - /* - * for given display configuration if multimonitormnsync == false then - * Memory clock DPMS with this latency or below is allowed, DPMS with - * higher latency not allowed. - */ - uint32_t dce_tolerable_mclk_in_active_latency; - uint32_t min_dcef_set_clk; - uint32_t min_dcef_deep_sleep_set_clk; -}; - -struct amd_pp_simple_clock_info { - uint32_t engine_max_clock; - uint32_t memory_max_clock; - uint32_t level; -}; - -enum PP_DAL_POWERLEVEL { - PP_DAL_POWERLEVEL_INVALID = 0, - PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_PERFORMANCE, - - PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, - PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, - PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, - PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, - PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, -}; - -struct amd_pp_clock_info { - uint32_t min_engine_clock; - uint32_t max_engine_clock; - uint32_t min_memory_clock; - uint32_t max_memory_clock; - uint32_t min_bus_bandwidth; - uint32_t max_bus_bandwidth; - uint32_t max_engine_clock_in_sr; - uint32_t min_engine_clock_in_sr; - enum PP_DAL_POWERLEVEL max_clocks_state; -}; - -enum amd_pp_clock_type { - amd_pp_disp_clock = 1, - amd_pp_sys_clock, - amd_pp_mem_clock, - amd_pp_dcef_clock, - amd_pp_soc_clock, - amd_pp_pixel_clock, - amd_pp_phy_clock, - amd_pp_dcf_clock, - amd_pp_dpp_clock, - amd_pp_f_clock = amd_pp_dcef_clock, -}; - -#define MAX_NUM_CLOCKS 16 - -struct amd_pp_clocks { - uint32_t count; - uint32_t clock[MAX_NUM_CLOCKS]; - uint32_t latency[MAX_NUM_CLOCKS]; -}; - - -enum { - PP_GROUP_UNKNOWN = 0, - PP_GROUP_GFX = 1, - PP_GROUP_SYS, - PP_GROUP_MAX -}; - -struct pp_states_info { - uint32_t nums; - uint32_t states[16]; -}; - -struct pp_gpu_power { - uint32_t vddc_power; - uint32_t vddci_power; - uint32_t max_gpu_power; - uint32_t average_gpu_power; -}; - -struct pp_display_clock_request { - enum amd_pp_clock_type clock_type; - uint32_t clock_freq_in_khz; -}; - -#define PP_GROUP_MASK 0xF0000000 -#define PP_GROUP_SHIFT 28 - -#define PP_BLOCK_MASK 0x0FFFFF00 -#define PP_BLOCK_SHIFT 8 - -#define PP_BLOCK_GFX_CG 0x01 -#define PP_BLOCK_GFX_MG 0x02 -#define PP_BLOCK_GFX_3D 0x04 -#define PP_BLOCK_GFX_RLC 0x08 -#define PP_BLOCK_GFX_CP 0x10 -#define PP_BLOCK_SYS_BIF 0x01 -#define PP_BLOCK_SYS_MC 0x02 -#define PP_BLOCK_SYS_ROM 0x04 -#define PP_BLOCK_SYS_DRM 0x08 -#define PP_BLOCK_SYS_HDP 0x10 -#define PP_BLOCK_SYS_SDMA 0x20 - -#define PP_STATE_MASK 0x0000000F -#define PP_STATE_SHIFT 0 -#define PP_STATE_SUPPORT_MASK 0x000000F0 -#define PP_STATE_SUPPORT_SHIFT 0 - -#define PP_STATE_CG 0x01 -#define PP_STATE_LS 0x02 -#define PP_STATE_DS 0x04 -#define PP_STATE_SD 0x08 -#define PP_STATE_SUPPORT_CG 0x10 -#define PP_STATE_SUPPORT_LS 0x20 -#define PP_STATE_SUPPORT_DS 0x40 -#define PP_STATE_SUPPORT_SD 0x80 - -#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\ - block << PP_BLOCK_SHIFT |\ - support << PP_STATE_SUPPORT_SHIFT |\ - state << PP_STATE_SHIFT) - -struct amd_powerplay { - struct cgs_device *cgs_device; - void *pp_handle; - const struct amd_ip_funcs *ip_funcs; - const struct amd_pm_funcs *pp_funcs; -}; - -int amd_powerplay_reset(void *handle); - -int amd_powerplay_display_configuration_change(void *handle, - const struct amd_pp_display_configuration *input); - -int amd_powerplay_get_display_power_level(void *handle, - struct amd_pp_simple_clock_info *output); - -int amd_powerplay_get_current_clocks(void *handle, - struct amd_pp_clock_info *output); - -int amd_powerplay_get_clock_by_type(void *handle, - enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks); - -int amd_powerplay_get_clock_by_type_with_latency(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks); - -int amd_powerplay_get_clock_by_type_with_voltage(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks); - -int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - -int amd_powerplay_display_clock_voltage_request(void *handle, - struct pp_display_clock_request *clock); - -int amd_powerplay_get_display_mode_validation_clocks(void *handle, - struct amd_pp_simple_clock_info *output); +#include "kgd_pp_interface.h" #endif /* _AMD_POWERPLAY_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h index a511611ec7e0..b7ab69e4c254 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h @@ -23,7 +23,7 @@ #ifndef PP_SOC15_H #define PP_SOC15_H -#include "vega10/soc15ip.h" +#include "soc15ip.h" inline static uint32_t soc15_get_register_offset( uint32_t hw_id, diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c index 4d672cd15785..c36f00ef46f3 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c @@ -1732,8 +1732,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.GraphicsBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Graphics DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); result = 0; } @@ -1743,8 +1742,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.MemoryBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Memory DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); result = 0; } @@ -2602,9 +2600,9 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), "Invalid VramInfo table.", return -EINVAL); - temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -2617,10 +2615,10 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); - if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) { + if (!data->is_memory_gddr5) { + PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { @@ -2628,8 +2626,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; } j++; - PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); } break; @@ -2644,8 +2640,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c index 34128822b8fb..d62078681cae 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c @@ -911,8 +911,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, &graphic_level->MinVddc); PP_ASSERT_WITH_CODE((0 == result), - "can not find VDDC voltage value for VDDC \ - engine clock dependency table", return result); + "can not find VDDC voltage value for VDDC engine clock dependency table", return result); /* SCLK frequency in units of 10KHz*/ graphic_level->SclkFrequency = engine_clock; @@ -1678,8 +1677,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.GraphicsBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Graphics DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n"); result = 0; } @@ -1689,8 +1687,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr, if (0 != result) { smu_data->smc_state_table.MemoryBootLevel = 0; - pr_err("VBIOS did not find boot engine clock value \ - in dependency table. Using Memory DPM level 0!"); + pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n"); result = 0; } @@ -2552,9 +2549,9 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), "Invalid VramInfo table.", return -EINVAL); - temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -2568,10 +2565,10 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, } } j++; - PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); - if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) { + if (!data->is_memory_gddr5) { + PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) { @@ -2579,8 +2576,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; } j++; - PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); } break; @@ -2595,8 +2590,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index 0a8e48bff219..81b8790c0d22 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -3106,9 +3106,9 @@ static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); } j++; + PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), "Invalid VramInfo table.", return -EINVAL); - temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; @@ -3121,18 +3121,16 @@ static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, table->mc_reg_table_entry[k].mc_data[j] |= 0x100; } j++; - PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); if (!data->is_memory_gddr5) { + PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), + "Invalid VramInfo table.", return -EINVAL); table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; for (k = 0; k < table->num_entries; k++) table->mc_reg_table_entry[k].mc_data[j] = (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; j++; - PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); } break; @@ -3147,8 +3145,6 @@ static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); } j++; - PP_ASSERT_WITH_CODE((j <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), - "Invalid VramInfo table.", return -EINVAL); break; default: diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c index 2f979fb86824..f6f39d01d227 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c @@ -381,10 +381,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) (rev_id == 0xc1) || (rev_id == 0xc3)))) { if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) { - pr_err("Your firmware(0x%x) doesn't match \ - SMU9_DRIVER_IF_VERSION(0x%x). \ - Please update your firmware!\n", - smc_driver_if_version, SMU9_DRIVER_IF_VERSION); + pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n", + smc_driver_if_version, SMU9_DRIVER_IF_VERSION); return -EINVAL; } } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h index 283a0dc25e84..eebe323c7159 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h @@ -13,8 +13,8 @@ #define TRACE_INCLUDE_FILE gpu_sched_trace TRACE_EVENT(amd_sched_job, - TP_PROTO(struct amd_sched_job *sched_job), - TP_ARGS(sched_job), + TP_PROTO(struct amd_sched_job *sched_job, struct amd_sched_entity *entity), + TP_ARGS(sched_job, entity), TP_STRUCT__entry( __field(struct amd_sched_entity *, entity) __field(struct dma_fence *, fence) @@ -25,12 +25,11 @@ TRACE_EVENT(amd_sched_job, ), TP_fast_assign( - __entry->entity = sched_job->s_entity; + __entry->entity = entity; __entry->id = sched_job->id; __entry->fence = &sched_job->s_fence->finished; __entry->name = sched_job->sched->name; - __entry->job_count = kfifo_len( - &sched_job->s_entity->job_queue) / sizeof(sched_job); + __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->hw_rq_count); ), diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 92ec663fdada..dcb987e6d94a 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -28,9 +28,14 @@ #include <drm/drmP.h> #include "gpu_scheduler.h" +#include "spsc_queue.h" + #define CREATE_TRACE_POINTS #include "gpu_sched_trace.h" +#define to_amd_sched_job(sched_job) \ + container_of((sched_job), struct amd_sched_job, queue_node) + static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity); static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); static void amd_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb); @@ -121,10 +126,8 @@ amd_sched_rq_select_entity(struct amd_sched_rq *rq) int amd_sched_entity_init(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity, struct amd_sched_rq *rq, - uint32_t jobs) + uint32_t jobs, atomic_t *guilty) { - int r; - if (!(sched && entity && rq)) return -EINVAL; @@ -132,12 +135,11 @@ int amd_sched_entity_init(struct amd_gpu_scheduler *sched, INIT_LIST_HEAD(&entity->list); entity->rq = rq; entity->sched = sched; + entity->guilty = guilty; spin_lock_init(&entity->rq_lock); spin_lock_init(&entity->queue_lock); - r = kfifo_alloc(&entity->job_queue, jobs * sizeof(void *), GFP_KERNEL); - if (r) - return r; + spsc_queue_init(&entity->job_queue); atomic_set(&entity->fence_seq, 0); entity->fence_context = dma_fence_context_alloc(2); @@ -170,7 +172,7 @@ static bool amd_sched_entity_is_initialized(struct amd_gpu_scheduler *sched, static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity) { rmb(); - if (kfifo_is_empty(&entity->job_queue)) + if (spsc_queue_peek(&entity->job_queue) == NULL) return true; return false; @@ -185,7 +187,7 @@ static bool amd_sched_entity_is_idle(struct amd_sched_entity *entity) */ static bool amd_sched_entity_is_ready(struct amd_sched_entity *entity) { - if (kfifo_is_empty(&entity->job_queue)) + if (spsc_queue_peek(&entity->job_queue) == NULL) return false; if (READ_ONCE(entity->dependency)) @@ -227,17 +229,23 @@ void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, */ kthread_park(sched->thread); kthread_unpark(sched->thread); - while (kfifo_out(&entity->job_queue, &job, sizeof(job))) { + if (entity->dependency) { + dma_fence_remove_callback(entity->dependency, + &entity->cb); + dma_fence_put(entity->dependency); + entity->dependency = NULL; + } + + while ((job = to_amd_sched_job(spsc_queue_pop(&entity->job_queue)))) { struct amd_sched_fence *s_fence = job->s_fence; amd_sched_fence_scheduled(s_fence); dma_fence_set_error(&s_fence->finished, -ESRCH); amd_sched_fence_finished(s_fence); + WARN_ON(s_fence->parent); dma_fence_put(&s_fence->finished); sched->ops->free_job(job); } - } - kfifo_free(&entity->job_queue); } static void amd_sched_entity_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) @@ -332,40 +340,44 @@ static bool amd_sched_entity_add_dependency_cb(struct amd_sched_entity *entity) } static struct amd_sched_job * -amd_sched_entity_peek_job(struct amd_sched_entity *entity) +amd_sched_entity_pop_job(struct amd_sched_entity *entity) { struct amd_gpu_scheduler *sched = entity->sched; - struct amd_sched_job *sched_job; + struct amd_sched_job *sched_job = to_amd_sched_job( + spsc_queue_peek(&entity->job_queue)); - if (!kfifo_out_peek(&entity->job_queue, &sched_job, sizeof(sched_job))) + if (!sched_job) return NULL; - while ((entity->dependency = sched->ops->dependency(sched_job))) + while ((entity->dependency = sched->ops->dependency(sched_job, entity))) if (amd_sched_entity_add_dependency_cb(entity)) return NULL; + /* skip jobs from entity that marked guilty */ + if (entity->guilty && atomic_read(entity->guilty)) + dma_fence_set_error(&sched_job->s_fence->finished, -ECANCELED); + + spsc_queue_pop(&entity->job_queue); return sched_job; } /** - * Helper to submit a job to the job queue + * Submit a job to the job queue * * @sched_job The pointer to job required to submit * - * Returns true if we could submit the job. + * Returns 0 for success, negative error code otherwise. */ -static bool amd_sched_entity_in(struct amd_sched_job *sched_job) +void amd_sched_entity_push_job(struct amd_sched_job *sched_job, + struct amd_sched_entity *entity) { struct amd_gpu_scheduler *sched = sched_job->sched; - struct amd_sched_entity *entity = sched_job->s_entity; - bool added, first = false; + bool first = false; - spin_lock(&entity->queue_lock); - added = kfifo_in(&entity->job_queue, &sched_job, - sizeof(sched_job)) == sizeof(sched_job); + trace_amd_sched_job(sched_job, entity); - if (added && kfifo_len(&entity->job_queue) == sizeof(sched_job)) - first = true; + spin_lock(&entity->queue_lock); + first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node); spin_unlock(&entity->queue_lock); @@ -377,7 +389,6 @@ static bool amd_sched_entity_in(struct amd_sched_job *sched_job) spin_unlock(&entity->rq_lock); amd_sched_wakeup(sched); } - return added; } /* job_finish is called after hw fence signaled @@ -442,9 +453,11 @@ static void amd_sched_job_timedout(struct work_struct *work) job->sched->ops->timedout_job(job); } -void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched) +void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *bad) { struct amd_sched_job *s_job; + struct amd_sched_entity *entity, *tmp; + int i;; spin_lock(&sched->job_list_lock); list_for_each_entry_reverse(s_job, &sched->ring_mirror_list, node) { @@ -457,6 +470,30 @@ void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched) } } spin_unlock(&sched->job_list_lock); + + if (bad && bad->s_priority != AMD_SCHED_PRIORITY_KERNEL) { + atomic_inc(&bad->karma); + /* don't increase @bad's karma if it's from KERNEL RQ, + * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs) + * corrupt but keep in mind that kernel jobs always considered good. + */ + for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_KERNEL; i++ ) { + struct amd_sched_rq *rq = &sched->sched_rq[i]; + + spin_lock(&rq->lock); + list_for_each_entry_safe(entity, tmp, &rq->entities, list) { + if (bad->s_fence->scheduled.context == entity->fence_context) { + if (atomic_read(&bad->karma) > bad->sched->hang_limit) + if (entity->guilty) + atomic_set(entity->guilty, 1); + break; + } + } + spin_unlock(&rq->lock); + if (&entity->list != &rq->entities) + break; + } + } } void amd_sched_job_kickout(struct amd_sched_job *s_job) @@ -471,6 +508,7 @@ void amd_sched_job_kickout(struct amd_sched_job *s_job) void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) { struct amd_sched_job *s_job, *tmp; + bool found_guilty = false; int r; spin_lock(&sched->job_list_lock); @@ -482,6 +520,15 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { struct amd_sched_fence *s_fence = s_job->s_fence; struct dma_fence *fence; + uint64_t guilty_context; + + if (!found_guilty && atomic_read(&s_job->karma) > sched->hang_limit) { + found_guilty = true; + guilty_context = s_job->s_fence->scheduled.context; + } + + if (found_guilty && s_job->s_fence->scheduled.context == guilty_context) + dma_fence_set_error(&s_fence->finished, -ECANCELED); spin_unlock(&sched->job_list_lock); fence = sched->ops->run_job(s_job); @@ -497,7 +544,6 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) r); dma_fence_put(fence); } else { - DRM_ERROR("Failed to run job!\n"); amd_sched_process_job(NULL, &s_fence->cb); } spin_lock(&sched->job_list_lock); @@ -505,22 +551,6 @@ void amd_sched_job_recovery(struct amd_gpu_scheduler *sched) spin_unlock(&sched->job_list_lock); } -/** - * Submit a job to the job queue - * - * @sched_job The pointer to job required to submit - * - * Returns 0 for success, negative error code otherwise. - */ -void amd_sched_entity_push_job(struct amd_sched_job *sched_job) -{ - struct amd_sched_entity *entity = sched_job->s_entity; - - trace_amd_sched_job(sched_job); - wait_event(entity->sched->job_scheduled, - amd_sched_entity_in(sched_job)); -} - /* init a sched_job with basic field */ int amd_sched_job_init(struct amd_sched_job *job, struct amd_gpu_scheduler *sched, @@ -528,7 +558,7 @@ int amd_sched_job_init(struct amd_sched_job *job, void *owner) { job->sched = sched; - job->s_entity = entity; + job->s_priority = entity->rq - sched->sched_rq; job->s_fence = amd_sched_fence_create(entity, owner); if (!job->s_fence) return -ENOMEM; @@ -610,7 +640,7 @@ static int amd_sched_main(void *param) { struct sched_param sparam = {.sched_priority = 1}; struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param; - int r, count; + int r; sched_setscheduler(current, SCHED_FIFO, &sparam); @@ -628,7 +658,7 @@ static int amd_sched_main(void *param) if (!entity) continue; - sched_job = amd_sched_entity_peek_job(entity); + sched_job = amd_sched_entity_pop_job(entity); if (!sched_job) continue; @@ -651,13 +681,9 @@ static int amd_sched_main(void *param) r); dma_fence_put(fence); } else { - DRM_ERROR("Failed to run job!\n"); amd_sched_process_job(NULL, &s_fence->cb); } - count = kfifo_out(&entity->job_queue, &sched_job, - sizeof(sched_job)); - WARN_ON(count != sizeof(sched_job)); wake_up(&sched->job_scheduled); } return 0; @@ -675,13 +701,17 @@ static int amd_sched_main(void *param) */ int amd_sched_init(struct amd_gpu_scheduler *sched, const struct amd_sched_backend_ops *ops, - unsigned hw_submission, long timeout, const char *name) + unsigned hw_submission, + unsigned hang_limit, + long timeout, + const char *name) { int i; sched->ops = ops; sched->hw_submission_limit = hw_submission; sched->name = name; sched->timeout = timeout; + sched->hang_limit = hang_limit; for (i = AMD_SCHED_PRIORITY_MIN; i < AMD_SCHED_PRIORITY_MAX; i++) amd_sched_rq_init(&sched->sched_rq[i]); diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 52c8e5447624..b590fcc2786a 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -26,10 +26,24 @@ #include <linux/kfifo.h> #include <linux/dma-fence.h> +#include "spsc_queue.h" struct amd_gpu_scheduler; struct amd_sched_rq; +enum amd_sched_priority { + AMD_SCHED_PRIORITY_MIN, + AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN, + AMD_SCHED_PRIORITY_NORMAL, + AMD_SCHED_PRIORITY_HIGH_SW, + AMD_SCHED_PRIORITY_HIGH_HW, + AMD_SCHED_PRIORITY_KERNEL, + AMD_SCHED_PRIORITY_MAX, + AMD_SCHED_PRIORITY_INVALID = -1, + AMD_SCHED_PRIORITY_UNSET = -2 +}; + + /** * A scheduler entity is a wrapper around a job queue or a group * of other entities. Entities take turns emitting jobs from their @@ -43,13 +57,14 @@ struct amd_sched_entity { struct amd_gpu_scheduler *sched; spinlock_t queue_lock; - struct kfifo job_queue; + struct spsc_queue job_queue; atomic_t fence_seq; uint64_t fence_context; struct dma_fence *dependency; struct dma_fence_cb cb; + atomic_t *guilty; /* points to ctx's guilty */ }; /** @@ -74,8 +89,8 @@ struct amd_sched_fence { }; struct amd_sched_job { + struct spsc_node queue_node; struct amd_gpu_scheduler *sched; - struct amd_sched_entity *s_entity; struct amd_sched_fence *s_fence; struct dma_fence_cb finish_cb; struct work_struct finish_work; @@ -83,6 +98,7 @@ struct amd_sched_job { struct delayed_work work_tdr; uint64_t id; atomic_t karma; + enum amd_sched_priority s_priority; }; extern const struct dma_fence_ops amd_sched_fence_ops_scheduled; @@ -108,24 +124,13 @@ static inline bool amd_sched_invalidate_job(struct amd_sched_job *s_job, int thr * these functions should be implemented in driver side */ struct amd_sched_backend_ops { - struct dma_fence *(*dependency)(struct amd_sched_job *sched_job); + struct dma_fence *(*dependency)(struct amd_sched_job *sched_job, + struct amd_sched_entity *s_entity); struct dma_fence *(*run_job)(struct amd_sched_job *sched_job); void (*timedout_job)(struct amd_sched_job *sched_job); void (*free_job)(struct amd_sched_job *sched_job); }; -enum amd_sched_priority { - AMD_SCHED_PRIORITY_MIN, - AMD_SCHED_PRIORITY_LOW = AMD_SCHED_PRIORITY_MIN, - AMD_SCHED_PRIORITY_NORMAL, - AMD_SCHED_PRIORITY_HIGH_SW, - AMD_SCHED_PRIORITY_HIGH_HW, - AMD_SCHED_PRIORITY_KERNEL, - AMD_SCHED_PRIORITY_MAX, - AMD_SCHED_PRIORITY_INVALID = -1, - AMD_SCHED_PRIORITY_UNSET = -2 -}; - /** * One scheduler is implemented for each hardware ring */ @@ -142,20 +147,22 @@ struct amd_gpu_scheduler { struct task_struct *thread; struct list_head ring_mirror_list; spinlock_t job_list_lock; + int hang_limit; }; int amd_sched_init(struct amd_gpu_scheduler *sched, const struct amd_sched_backend_ops *ops, - uint32_t hw_submission, long timeout, const char *name); + uint32_t hw_submission, unsigned hang_limit, long timeout, const char *name); void amd_sched_fini(struct amd_gpu_scheduler *sched); int amd_sched_entity_init(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity, struct amd_sched_rq *rq, - uint32_t jobs); + uint32_t jobs, atomic_t* guilty); void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity); -void amd_sched_entity_push_job(struct amd_sched_job *sched_job); +void amd_sched_entity_push_job(struct amd_sched_job *sched_job, + struct amd_sched_entity *entity); void amd_sched_entity_set_rq(struct amd_sched_entity *entity, struct amd_sched_rq *rq); @@ -170,16 +177,10 @@ int amd_sched_job_init(struct amd_sched_job *job, struct amd_gpu_scheduler *sched, struct amd_sched_entity *entity, void *owner); -void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched); +void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched, struct amd_sched_job *job); void amd_sched_job_recovery(struct amd_gpu_scheduler *sched); bool amd_sched_dependency_optimized(struct dma_fence* fence, struct amd_sched_entity *entity); void amd_sched_job_kickout(struct amd_sched_job *s_job); -static inline enum amd_sched_priority -amd_sched_get_job_priority(struct amd_sched_job *job) -{ - return (job->s_entity->rq - job->sched->sched_rq); -} - #endif diff --git a/drivers/gpu/drm/amd/scheduler/spsc_queue.h b/drivers/gpu/drm/amd/scheduler/spsc_queue.h new file mode 100644 index 000000000000..5902f35ce759 --- /dev/null +++ b/drivers/gpu/drm/amd/scheduler/spsc_queue.h @@ -0,0 +1,121 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef AMD_SCHEDULER_SPSC_QUEUE_H_ +#define AMD_SCHEDULER_SPSC_QUEUE_H_ + +#include <linux/atomic.h> + +/** SPSC lockless queue */ + +struct spsc_node { + + /* Stores spsc_node* */ + struct spsc_node *next; +}; + +struct spsc_queue { + + struct spsc_node *head; + + /* atomic pointer to struct spsc_node* */ + atomic_long_t tail; + + atomic_t job_count; +}; + +static inline void spsc_queue_init(struct spsc_queue *queue) +{ + queue->head = NULL; + atomic_long_set(&queue->tail, (long)&queue->head); + atomic_set(&queue->job_count, 0); +} + +static inline struct spsc_node *spsc_queue_peek(struct spsc_queue *queue) +{ + return queue->head; +} + +static inline int spsc_queue_count(struct spsc_queue *queue) +{ + return atomic_read(&queue->job_count); +} + +static inline bool spsc_queue_push(struct spsc_queue *queue, struct spsc_node *node) +{ + struct spsc_node **tail; + + node->next = NULL; + + preempt_disable(); + + tail = (struct spsc_node **)atomic_long_xchg(&queue->tail, (long)&node->next); + WRITE_ONCE(*tail, node); + atomic_inc(&queue->job_count); + + /* + * In case of first element verify new node will be visible to the consumer + * thread when we ping the kernel thread that there is new work to do. + */ + smp_wmb(); + + preempt_enable(); + + return tail == &queue->head; +} + + +static inline struct spsc_node *spsc_queue_pop(struct spsc_queue *queue) +{ + struct spsc_node *next, *node; + + /* Verify reading from memory and not the cache */ + smp_rmb(); + + node = READ_ONCE(queue->head); + + if (!node) + return NULL; + + next = READ_ONCE(node->next); + WRITE_ONCE(queue->head, next); + + if (unlikely(!next)) { + /* slowpath for the last element in the queue */ + + if (atomic_long_cmpxchg(&queue->tail, + (long)&node->next, (long) &queue->head) != (long)&node->next) { + /* Updating tail failed wait for new next to appear */ + do { + smp_rmb(); + } while (unlikely(!(queue->head = READ_ONCE(node->next)))); + } + } + + atomic_dec(&queue->job_count); + return node; +} + + + +#endif /* AMD_SCHEDULER_SPSC_QUEUE_H_ */ diff --git a/drivers/gpu/drm/ast/ast_ttm.c b/drivers/gpu/drm/ast/ast_ttm.c index 696a15dc2f3f..28da7c2b7ed9 100644 --- a/drivers/gpu/drm/ast/ast_ttm.c +++ b/drivers/gpu/drm/ast/ast_ttm.c @@ -354,6 +354,7 @@ static inline u64 ast_bo_gpu_offset(struct ast_bo *bo) int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -365,7 +366,7 @@ int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) ast_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -377,6 +378,7 @@ int ast_bo_pin(struct ast_bo *bo, u32 pl_flag, u64 *gpu_addr) int ast_bo_unpin(struct ast_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -388,11 +390,12 @@ int ast_bo_unpin(struct ast_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - return ttm_bo_validate(&bo->bo, &bo->placement, false, false); + return ttm_bo_validate(&bo->bo, &bo->placement, &ctx); } int ast_bo_push_sysram(struct ast_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -409,7 +412,7 @@ int ast_bo_push_sysram(struct ast_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; diff --git a/drivers/gpu/drm/bochs/bochs_mm.c b/drivers/gpu/drm/bochs/bochs_mm.c index c4cadb638460..8250b5e612d2 100644 --- a/drivers/gpu/drm/bochs/bochs_mm.c +++ b/drivers/gpu/drm/bochs/bochs_mm.c @@ -283,6 +283,7 @@ static inline u64 bochs_bo_gpu_offset(struct bochs_bo *bo) int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -295,7 +296,7 @@ int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) bochs_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -307,6 +308,7 @@ int bochs_bo_pin(struct bochs_bo *bo, u32 pl_flag, u64 *gpu_addr) int bochs_bo_unpin(struct bochs_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { @@ -320,7 +322,7 @@ int bochs_bo_unpin(struct bochs_bo *bo) for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; diff --git a/drivers/gpu/drm/cirrus/cirrus_ttm.c b/drivers/gpu/drm/cirrus/cirrus_ttm.c index 1ff1838c0d44..2a5b54d3a03a 100644 --- a/drivers/gpu/drm/cirrus/cirrus_ttm.c +++ b/drivers/gpu/drm/cirrus/cirrus_ttm.c @@ -358,6 +358,7 @@ static inline u64 cirrus_bo_gpu_offset(struct cirrus_bo *bo) int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -369,7 +370,7 @@ int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) cirrus_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -381,6 +382,7 @@ int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr) int cirrus_bo_push_sysram(struct cirrus_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -397,7 +399,7 @@ int cirrus_bo_push_sysram(struct cirrus_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c index 3518167a7dc4..ab4ee5953615 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c @@ -344,6 +344,7 @@ int hibmc_bo_create(struct drm_device *dev, int size, int align, int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -356,7 +357,7 @@ int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr) hibmc_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -368,6 +369,7 @@ int hibmc_bo_pin(struct hibmc_bo *bo, u32 pl_flag, u64 *gpu_addr) int hibmc_bo_unpin(struct hibmc_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { @@ -380,7 +382,7 @@ int hibmc_bo_unpin(struct hibmc_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("validate failed for unpin: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/mgag200/mgag200_ttm.c b/drivers/gpu/drm/mgag200/mgag200_ttm.c index 3e7e1cd31395..f03da63abc7b 100644 --- a/drivers/gpu/drm/mgag200/mgag200_ttm.c +++ b/drivers/gpu/drm/mgag200/mgag200_ttm.c @@ -354,6 +354,7 @@ static inline u64 mgag200_bo_gpu_offset(struct mgag200_bo *bo) int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (bo->pin_count) { @@ -366,7 +367,7 @@ int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) mgag200_ttm_placement(bo, pl_flag); for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) return ret; @@ -378,6 +379,7 @@ int mgag200_bo_pin(struct mgag200_bo *bo, u32 pl_flag, u64 *gpu_addr) int mgag200_bo_unpin(struct mgag200_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -389,11 +391,12 @@ int mgag200_bo_unpin(struct mgag200_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - return ttm_bo_validate(&bo->bo, &bo->placement, false, false); + return ttm_bo_validate(&bo->bo, &bo->placement, &ctx); } int mgag200_bo_push_sysram(struct mgag200_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int i, ret; if (!bo->pin_count) { DRM_ERROR("unpin bad %p\n", bo); @@ -410,7 +413,7 @@ int mgag200_bo_push_sysram(struct mgag200_bo *bo) for (i = 0; i < bo->placement.num_placement ; i++) bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; - ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false); + ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx); if (ret) { DRM_ERROR("pushing to VRAM failed\n"); return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 2615912430cc..949bf6b3feab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -548,10 +548,10 @@ int nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, bool no_wait_gpu) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; int ret; - ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, - interruptible, no_wait_gpu); + ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); if (ret) return ret; @@ -1199,6 +1199,7 @@ static int nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, bool no_wait_gpu, struct ttm_mem_reg *new_reg) { + struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; struct ttm_place placement_memtype = { .fpfn = 0, .lpfn = 0, @@ -1213,7 +1214,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, tmp_reg = *new_reg; tmp_reg.mm_node = NULL; - ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); + ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); if (ret) return ret; @@ -1235,6 +1236,7 @@ static int nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, bool no_wait_gpu, struct ttm_mem_reg *new_reg) { + struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; struct ttm_place placement_memtype = { .fpfn = 0, .lpfn = 0, @@ -1249,7 +1251,7 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, tmp_reg = *new_reg; tmp_reg.mm_node = NULL; - ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); + ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); if (ret) return ret; @@ -1326,8 +1328,9 @@ nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, } static int -nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, - bool no_wait_gpu, struct ttm_mem_reg *new_reg) +nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, + struct ttm_mem_reg *new_reg) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); @@ -1335,7 +1338,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, struct nouveau_drm_tile *new_tile = NULL; int ret = 0; - ret = ttm_bo_wait(bo, intr, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; @@ -1359,22 +1362,26 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, /* Hardware assisted copy. */ if (drm->ttm.move) { if (new_reg->mem_type == TTM_PL_SYSTEM) - ret = nouveau_bo_move_flipd(bo, evict, intr, - no_wait_gpu, new_reg); + ret = nouveau_bo_move_flipd(bo, evict, + ctx->interruptible, + ctx->no_wait_gpu, new_reg); else if (old_reg->mem_type == TTM_PL_SYSTEM) - ret = nouveau_bo_move_flips(bo, evict, intr, - no_wait_gpu, new_reg); + ret = nouveau_bo_move_flips(bo, evict, + ctx->interruptible, + ctx->no_wait_gpu, new_reg); else - ret = nouveau_bo_move_m2mf(bo, evict, intr, - no_wait_gpu, new_reg); + ret = nouveau_bo_move_m2mf(bo, evict, + ctx->interruptible, + ctx->no_wait_gpu, new_reg); if (!ret) goto out; } /* Fallback to software copy. */ - ret = ttm_bo_wait(bo, intr, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret == 0) - ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg); + ret = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, new_reg); out: if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index efc89aaef66a..e72a7e37eb0a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -354,7 +354,7 @@ validate_fini_no_ticket(struct validate_op *op, struct nouveau_fence *fence, list_del(&nvbo->entry); nvbo->reserved_by = NULL; - ttm_bo_unreserve_ticket(&nvbo->bo, &op->ticket); + ttm_bo_unreserve(&nvbo->bo); drm_gem_object_unreference_unlocked(&nvbo->gem); } } diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index 31effed4a3c8..e8c0b1037230 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -309,6 +309,7 @@ static int qxl_update_area_ioctl(struct drm_device *dev, void *data, int ret; struct drm_gem_object *gobj = NULL; struct qxl_bo *qobj = NULL; + struct ttm_operation_ctx ctx = { true, false }; if (update_area->left >= update_area->right || update_area->top >= update_area->bottom) @@ -326,8 +327,7 @@ static int qxl_update_area_ioctl(struct drm_device *dev, void *data, if (!qobj->pin_count) { qxl_ttm_placement_from_domain(qobj, qobj->type, false); - ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, - true, false); + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); if (unlikely(ret)) goto out; } diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c index 0a67ddf19c3d..f6b80fe47d1f 100644 --- a/drivers/gpu/drm/qxl/qxl_object.c +++ b/drivers/gpu/drm/qxl/qxl_object.c @@ -223,6 +223,7 @@ struct qxl_bo *qxl_bo_ref(struct qxl_bo *bo) static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; struct drm_device *ddev = bo->gem_base.dev; int r; @@ -233,7 +234,7 @@ static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) return 0; } qxl_ttm_placement_from_domain(bo, domain, true); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (likely(r == 0)) { bo->pin_count = 1; if (gpu_addr != NULL) @@ -246,6 +247,7 @@ static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) static int __qxl_bo_unpin(struct qxl_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; struct drm_device *ddev = bo->gem_base.dev; int r, i; @@ -258,7 +260,7 @@ static int __qxl_bo_unpin(struct qxl_bo *bo) return 0; for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (unlikely(r != 0)) dev_err(ddev->dev, "%p validate failed for unpin\n", bo); return r; diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index a6da6fa6ad58..b223c8d0a491 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -230,12 +230,12 @@ int qxl_release_list_add(struct qxl_release *release, struct qxl_bo *bo) static int qxl_release_validate_bo(struct qxl_bo *bo) { + struct ttm_operation_ctx ctx = { true, false }; int ret; if (!bo->pin_count) { qxl_ttm_placement_from_domain(bo, bo->type, false); - ret = ttm_bo_validate(&bo->tbo, &bo->placement, - true, false); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (ret) return ret; } @@ -468,7 +468,7 @@ void qxl_release_fence_buffer_objects(struct qxl_release *release) reservation_object_add_shared_fence(bo->resv, &release->base); ttm_bo_add_to_lru(bo); - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } spin_unlock(&glob->lru_lock); ww_acquire_fini(&release->ticket); diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 586ecd6e0e45..d866f329e7d8 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -341,15 +341,14 @@ static void qxl_move_null(struct ttm_buffer_object *bo, new_mem->mm_node = NULL; } -static int qxl_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int qxl_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { struct ttm_mem_reg *old_mem = &bo->mem; int ret; - ret = ttm_bo_wait(bo, interruptible, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; @@ -358,7 +357,7 @@ static int qxl_bo_move(struct ttm_buffer_object *bo, qxl_move_null(bo, new_mem); return 0; } - return ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, + return ttm_bo_move_memcpy(bo, ctx->interruptible, ctx->no_wait_gpu, new_mem); } diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index ddfe91efa61e..dfda5e0ed166 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -32,6 +32,7 @@ #include <linux/pm_runtime.h> #include <drm/drm_crtc_helper.h> +#include <drm/drm_fb_helper.h> #include <drm/drm_plane_helper.h> #include <drm/drm_edid.h> @@ -1362,15 +1363,9 @@ radeon_user_framebuffer_create(struct drm_device *dev, return &radeon_fb->base; } -static void radeon_output_poll_changed(struct drm_device *dev) -{ - struct radeon_device *rdev = dev->dev_private; - radeon_fb_output_poll_changed(rdev); -} - static const struct drm_mode_config_funcs radeon_mode_funcs = { .fb_create = radeon_user_framebuffer_create, - .output_poll_changed = radeon_output_poll_changed + .output_poll_changed = drm_fb_helper_output_poll_changed, }; static const struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 33b821d6d018..57c5404a1654 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -306,12 +306,6 @@ out: return ret; } -void radeon_fb_output_poll_changed(struct radeon_device *rdev) -{ - if (rdev->mode_info.rfbdev) - drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper); -} - static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev) { struct radeon_framebuffer *rfb = &rfbdev->rfb; @@ -422,19 +416,3 @@ void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector if (rdev->mode_info.rfbdev) drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector); } - -void radeon_fbdev_restore_mode(struct radeon_device *rdev) -{ - struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev; - struct drm_fb_helper *fb_helper; - int ret; - - if (!rfbdev) - return; - - fb_helper = &rfbdev->helper; - - ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); - if (ret) - DRM_DEBUG("failed to restore crtc mode\n"); -} diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index cf3deb283da5..a9962ffba720 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -285,6 +285,7 @@ int radeon_gem_create_ioctl(struct drm_device *dev, void *data, int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct ttm_operation_ctx ctx = { true, false }; struct radeon_device *rdev = dev->dev_private; struct drm_radeon_gem_userptr *args = data; struct drm_gem_object *gobj; @@ -343,7 +344,7 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, } radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); radeon_bo_unreserve(bo); up_read(¤t->mm->mmap_sem); if (r) diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index cde037f213d7..dec1e081f529 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -26,6 +26,7 @@ * Jerome Glisse */ #include <drm/drmP.h> +#include <drm/drm_fb_helper.h> #include "radeon.h" #include <drm/radeon_drm.h> #include "radeon_asic.h" @@ -629,9 +630,7 @@ static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file */ void radeon_driver_lastclose_kms(struct drm_device *dev) { - struct radeon_device *rdev = dev->dev_private; - - radeon_fbdev_restore_mode(rdev); + drm_fb_helper_lastclose(dev); vga_switcheroo_process_delayed_switch(); } diff --git a/drivers/gpu/drm/radeon/radeon_mn.c b/drivers/gpu/drm/radeon/radeon_mn.c index 1d62288b7ee3..abd24975c9b1 100644 --- a/drivers/gpu/drm/radeon/radeon_mn.c +++ b/drivers/gpu/drm/radeon/radeon_mn.c @@ -124,6 +124,7 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn, unsigned long end) { struct radeon_mn *rmn = container_of(mn, struct radeon_mn, mn); + struct ttm_operation_ctx ctx = { false, false }; struct interval_tree_node *it; /* notification is exclusive, but interval is inclusive */ @@ -157,7 +158,7 @@ static void radeon_mn_invalidate_range_start(struct mmu_notifier *mn, DRM_ERROR("(%ld) failed to wait for user bo\n", r); radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) DRM_ERROR("(%ld) failed to validate user bo\n", r); diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index ca0a7ed28c9b..3243e5e01432 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -984,9 +984,6 @@ int radeon_fbdev_init(struct radeon_device *rdev); void radeon_fbdev_fini(struct radeon_device *rdev); void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); -void radeon_fbdev_restore_mode(struct radeon_device *rdev); - -void radeon_fb_output_poll_changed(struct radeon_device *rdev); void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id); diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 093594976126..15404af9d740 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -329,6 +329,7 @@ void radeon_bo_unref(struct radeon_bo **bo) int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, u64 *gpu_addr) { + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) @@ -371,7 +372,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (likely(r == 0)) { bo->pin_count = 1; if (gpu_addr != NULL) @@ -393,6 +394,7 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) int radeon_bo_unpin(struct radeon_bo *bo) { + struct ttm_operation_ctx ctx = { false, false }; int r, i; if (!bo->pin_count) { @@ -406,7 +408,7 @@ int radeon_bo_unpin(struct radeon_bo *bo) bo->placements[i].lpfn = 0; bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; } - r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (likely(r == 0)) { if (bo->tbo.mem.mem_type == TTM_PL_VRAM) bo->rdev->vram_pin_size -= radeon_bo_size(bo); @@ -531,6 +533,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, struct ww_acquire_ctx *ticket, struct list_head *head, int ring) { + struct ttm_operation_ctx ctx = { true, false }; struct radeon_bo_list *lobj; struct list_head duplicates; int r; @@ -572,7 +575,7 @@ int radeon_bo_list_validate(struct radeon_device *rdev, radeon_uvd_force_into_uvd_segment(bo, allowed); initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); bytes_moved += atomic64_read(&rdev->num_bytes_moved) - initial_bytes_moved; @@ -792,6 +795,7 @@ void radeon_bo_move_notify(struct ttm_buffer_object *bo, int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) { + struct ttm_operation_ctx ctx = { false, false }; struct radeon_device *rdev; struct radeon_bo *rbo; unsigned long offset, size, lpfn; @@ -823,10 +827,10 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) rbo->placements[i].lpfn = lpfn; } - r = ttm_bo_validate(bo, &rbo->placement, false, false); + r = ttm_bo_validate(bo, &rbo->placement, &ctx); if (unlikely(r == -ENOMEM)) { radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); - return ttm_bo_validate(bo, &rbo->placement, false, false); + return ttm_bo_validate(bo, &rbo->placement, &ctx); } else if (unlikely(r != 0)) { return r; } diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 6ada64db00e9..98e30d71d9e0 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -311,6 +311,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -328,8 +329,7 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); if (unlikely(r)) { return r; } @@ -358,6 +358,7 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, bool no_wait_gpu, struct ttm_mem_reg *new_mem) { + struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; struct radeon_device *rdev; struct ttm_mem_reg *old_mem = &bo->mem; struct ttm_mem_reg tmp_mem; @@ -375,8 +376,7 @@ static int radeon_move_ram_vram(struct ttm_buffer_object *bo, placements.fpfn = 0; placements.lpfn = 0; placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - r = ttm_bo_mem_space(bo, &placement, &tmp_mem, - interruptible, no_wait_gpu); + r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); if (unlikely(r)) { return r; } @@ -393,17 +393,16 @@ out_cleanup: return r; } -static int radeon_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, - struct ttm_mem_reg *new_mem) +static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, + struct ttm_mem_reg *new_mem) { struct radeon_device *rdev; struct radeon_bo *rbo; struct ttm_mem_reg *old_mem = &bo->mem; int r; - r = ttm_bo_wait(bo, interruptible, no_wait_gpu); + r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (r) return r; @@ -433,19 +432,21 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, if (old_mem->mem_type == TTM_PL_VRAM && new_mem->mem_type == TTM_PL_SYSTEM) { - r = radeon_move_vram_ram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = radeon_move_vram_ram(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, new_mem); } else if (old_mem->mem_type == TTM_PL_SYSTEM && new_mem->mem_type == TTM_PL_VRAM) { - r = radeon_move_ram_vram(bo, evict, interruptible, - no_wait_gpu, new_mem); + r = radeon_move_ram_vram(bo, evict, ctx->interruptible, + ctx->no_wait_gpu, new_mem); } else { - r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); + r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, + new_mem, old_mem); } if (r) { memcpy: - r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem); + r = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, new_mem); if (r) { return r; } diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index e5c0e635e371..7f1a9c787bd1 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c @@ -387,6 +387,7 @@ static void radeon_vm_set_pages(struct radeon_device *rdev, static int radeon_vm_clear_bo(struct radeon_device *rdev, struct radeon_bo *bo) { + struct ttm_operation_ctx ctx = { true, false }; struct radeon_ib ib; unsigned entries; uint64_t addr; @@ -396,7 +397,7 @@ static int radeon_vm_clear_bo(struct radeon_device *rdev, if (r) return r; - r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) goto error_unreserve; diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index c088703777e2..97c3da6d5f17 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -269,9 +269,8 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) } static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, - struct ttm_mem_reg *mem, - bool evict, bool interruptible, - bool no_wait_gpu) + struct ttm_mem_reg *mem, bool evict, + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; bool old_is_pci = ttm_mem_reg_is_pci(bdev, &bo->mem); @@ -325,12 +324,13 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) && !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED)) - ret = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, mem); + ret = ttm_bo_move_ttm(bo, ctx->interruptible, + ctx->no_wait_gpu, mem); else if (bdev->driver->move) - ret = bdev->driver->move(bo, evict, interruptible, - no_wait_gpu, mem); + ret = bdev->driver->move(bo, evict, ctx, mem); else - ret = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, mem); + ret = ttm_bo_move_memcpy(bo, ctx->interruptible, + ctx->no_wait_gpu, mem); if (ret) { if (bdev->driver->move_notify) { @@ -355,13 +355,13 @@ moved: bo->evicted = false; } - if (bo->mem.mm_node) { + if (bo->mem.mm_node) bo->offset = (bo->mem.start << PAGE_SHIFT) + bdev->man[bo->mem.mem_type].gpu_offset; - bo->cur_placement = bo->mem.placement; - } else + else bo->offset = 0; + ctx->bytes_moved += bo->num_pages << PAGE_SHIFT; return 0; out_err: @@ -390,8 +390,6 @@ static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo) ttm_tt_destroy(bo->ttm); bo->ttm = NULL; ttm_bo_mem_put(bo, &bo->mem); - - ww_mutex_unlock (&bo->resv->lock); } static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) @@ -448,7 +446,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) } spin_lock(&glob->lru_lock); - ret = __ttm_bo_reserve(bo, false, true, NULL); + ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; if (!ret) { if (reservation_object_test_signaled_rcu(&bo->ttm_resv, true)) { ttm_bo_del_from_lru(bo); @@ -457,6 +455,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) reservation_object_unlock(&bo->ttm_resv); ttm_bo_cleanup_memtype_use(bo); + reservation_object_unlock(bo->resv); return; } @@ -472,7 +471,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo) ttm_bo_add_to_lru(bo); } - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } if (bo->resv != &bo->ttm_resv) reservation_object_unlock(&bo->ttm_resv); @@ -487,20 +486,21 @@ error: } /** - * function ttm_bo_cleanup_refs_and_unlock + * function ttm_bo_cleanup_refs * If bo idle, remove from delayed- and lru lists, and unref. * If not idle, do nothing. * * Must be called with lru_lock and reservation held, this function - * will drop both before returning. + * will drop the lru lock and optionally the reservation lock before returning. * * @interruptible Any sleeps should occur interruptibly. * @no_wait_gpu Never wait for gpu. Return -EBUSY instead. + * @unlock_resv Unlock the reservation lock as well. */ -static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, - bool interruptible, - bool no_wait_gpu) +static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, + bool interruptible, bool no_wait_gpu, + bool unlock_resv) { struct ttm_bo_global *glob = bo->glob; struct reservation_object *resv; @@ -518,7 +518,9 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, if (ret && !no_wait_gpu) { long lret; - ww_mutex_unlock(&bo->resv->lock); + + if (unlock_resv) + reservation_object_unlock(bo->resv); spin_unlock(&glob->lru_lock); lret = reservation_object_wait_timeout_rcu(resv, true, @@ -531,24 +533,24 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, return -EBUSY; spin_lock(&glob->lru_lock); - ret = __ttm_bo_reserve(bo, false, true, NULL); - - /* - * We raced, and lost, someone else holds the reservation now, - * and is probably busy in ttm_bo_cleanup_memtype_use. - * - * Even if it's not the case, because we finished waiting any - * delayed destruction would succeed, so just return success - * here. - */ - if (ret) { + if (unlock_resv && !reservation_object_trylock(bo->resv)) { + /* + * We raced, and lost, someone else holds the reservation now, + * and is probably busy in ttm_bo_cleanup_memtype_use. + * + * Even if it's not the case, because we finished waiting any + * delayed destruction would succeed, so just return success + * here. + */ spin_unlock(&glob->lru_lock); return 0; } + ret = 0; } if (ret || unlikely(list_empty(&bo->ddestroy))) { - __ttm_bo_unreserve(bo); + if (unlock_resv) + reservation_object_unlock(bo->resv); spin_unlock(&glob->lru_lock); return ret; } @@ -560,6 +562,9 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, spin_unlock(&glob->lru_lock); ttm_bo_cleanup_memtype_use(bo); + if (unlock_resv) + reservation_object_unlock(bo->resv); + return 0; } @@ -567,60 +572,37 @@ static int ttm_bo_cleanup_refs_and_unlock(struct ttm_buffer_object *bo, * Traverse the delayed list, and call ttm_bo_cleanup_refs on all * encountered buffers. */ - -static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) +static bool ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all) { struct ttm_bo_global *glob = bdev->glob; - struct ttm_buffer_object *entry = NULL; - int ret = 0; - - spin_lock(&glob->lru_lock); - if (list_empty(&bdev->ddestroy)) - goto out_unlock; - - entry = list_first_entry(&bdev->ddestroy, - struct ttm_buffer_object, ddestroy); - kref_get(&entry->list_kref); + struct list_head removed; + bool empty; - for (;;) { - struct ttm_buffer_object *nentry = NULL; - - if (entry->ddestroy.next != &bdev->ddestroy) { - nentry = list_first_entry(&entry->ddestroy, - struct ttm_buffer_object, ddestroy); - kref_get(&nentry->list_kref); - } + INIT_LIST_HEAD(&removed); - ret = __ttm_bo_reserve(entry, false, true, NULL); - if (remove_all && ret) { - spin_unlock(&glob->lru_lock); - ret = __ttm_bo_reserve(entry, false, false, NULL); - spin_lock(&glob->lru_lock); - } + spin_lock(&glob->lru_lock); + while (!list_empty(&bdev->ddestroy)) { + struct ttm_buffer_object *bo; - if (!ret) - ret = ttm_bo_cleanup_refs_and_unlock(entry, false, - !remove_all); - else - spin_unlock(&glob->lru_lock); + bo = list_first_entry(&bdev->ddestroy, struct ttm_buffer_object, + ddestroy); + kref_get(&bo->list_kref); + list_move_tail(&bo->ddestroy, &removed); + spin_unlock(&glob->lru_lock); - kref_put(&entry->list_kref, ttm_bo_release_list); - entry = nentry; + reservation_object_lock(bo->resv, NULL); - if (ret || !entry) - goto out; + spin_lock(&glob->lru_lock); + ttm_bo_cleanup_refs(bo, false, !remove_all, true); + kref_put(&bo->list_kref, ttm_bo_release_list); spin_lock(&glob->lru_lock); - if (list_empty(&entry->ddestroy)) - break; } - -out_unlock: + list_splice_tail(&removed, &bdev->ddestroy); + empty = list_empty(&bdev->ddestroy); spin_unlock(&glob->lru_lock); -out: - if (entry) - kref_put(&entry->list_kref, ttm_bo_release_list); - return ret; + + return empty; } static void ttm_bo_delayed_workqueue(struct work_struct *work) @@ -628,7 +610,7 @@ static void ttm_bo_delayed_workqueue(struct work_struct *work) struct ttm_bo_device *bdev = container_of(work, struct ttm_bo_device, wq.work); - if (ttm_bo_delayed_delete(bdev, false)) { + if (!ttm_bo_delayed_delete(bdev, false)) { schedule_delayed_work(&bdev->wq, ((HZ / 100) < 1) ? 1 : HZ / 100); } @@ -672,8 +654,8 @@ void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, int resched) } EXPORT_SYMBOL(ttm_bo_unlock_delayed_workqueue); -static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, - bool no_wait_gpu) +static int ttm_bo_evict(struct ttm_buffer_object *bo, + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_reg evict_mem; @@ -690,8 +672,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, placement.num_placement = 0; placement.num_busy_placement = 0; bdev->driver->evict_flags(bo, &placement); - ret = ttm_bo_mem_space(bo, &placement, &evict_mem, interruptible, - no_wait_gpu); + ret = ttm_bo_mem_space(bo, &placement, &evict_mem, ctx); if (ret) { if (ret != -ERESTARTSYS) { pr_err("Failed to find memory space for buffer 0x%p eviction\n", @@ -701,8 +682,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, goto out; } - ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, interruptible, - no_wait_gpu); + ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, ctx); if (unlikely(ret)) { if (ret != -ERESTARTSYS) pr_err("Buffer eviction failed\n"); @@ -729,48 +709,56 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, EXPORT_SYMBOL(ttm_bo_eviction_valuable); static int ttm_mem_evict_first(struct ttm_bo_device *bdev, - uint32_t mem_type, - const struct ttm_place *place, - bool interruptible, - bool no_wait_gpu) + struct reservation_object *resv, + uint32_t mem_type, + const struct ttm_place *place, + struct ttm_operation_ctx *ctx) { struct ttm_bo_global *glob = bdev->glob; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; - struct ttm_buffer_object *bo; - int ret = -EBUSY; + struct ttm_buffer_object *bo = NULL; + bool locked = false; unsigned i; + int ret; spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { list_for_each_entry(bo, &man->lru[i], lru) { - ret = __ttm_bo_reserve(bo, false, true, NULL); - if (ret) - continue; + if (bo->resv == resv) { + if (list_empty(&bo->ddestroy)) + continue; + } else { + locked = reservation_object_trylock(bo->resv); + if (!locked) + continue; + } if (place && !bdev->driver->eviction_valuable(bo, place)) { - __ttm_bo_unreserve(bo); - ret = -EBUSY; + if (locked) + reservation_object_unlock(bo->resv); continue; } - break; } - if (!ret) + /* If the inner loop terminated early, we have our candidate */ + if (&bo->lru != &man->lru[i]) break; + + bo = NULL; } - if (ret) { + if (!bo) { spin_unlock(&glob->lru_lock); - return ret; + return -EBUSY; } kref_get(&bo->list_kref); if (!list_empty(&bo->ddestroy)) { - ret = ttm_bo_cleanup_refs_and_unlock(bo, interruptible, - no_wait_gpu); + ret = ttm_bo_cleanup_refs(bo, ctx->interruptible, + ctx->no_wait_gpu, locked); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -778,10 +766,14 @@ static int ttm_mem_evict_first(struct ttm_bo_device *bdev, ttm_bo_del_from_lru(bo); spin_unlock(&glob->lru_lock); - BUG_ON(ret != 0); - - ret = ttm_bo_evict(bo, interruptible, no_wait_gpu); - ttm_bo_unreserve(bo); + ret = ttm_bo_evict(bo, ctx); + if (locked) { + ttm_bo_unreserve(bo); + } else { + spin_lock(&glob->lru_lock); + ttm_bo_add_to_lru(bo); + spin_unlock(&glob->lru_lock); + } kref_put(&bo->list_kref, ttm_bo_release_list); return ret; @@ -832,8 +824,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, uint32_t mem_type, const struct ttm_place *place, struct ttm_mem_reg *mem, - bool interruptible, - bool no_wait_gpu) + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; @@ -845,8 +836,7 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo, return ret; if (mem->mm_node) break; - ret = ttm_mem_evict_first(bdev, mem_type, place, - interruptible, no_wait_gpu); + ret = ttm_mem_evict_first(bdev, bo->resv, mem_type, place, ctx); if (unlikely(ret != 0)) return ret; } while (1); @@ -909,8 +899,7 @@ static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man, int ttm_bo_mem_space(struct ttm_buffer_object *bo, struct ttm_placement *placement, struct ttm_mem_reg *mem, - bool interruptible, - bool no_wait_gpu) + struct ttm_operation_ctx *ctx) { struct ttm_bo_device *bdev = bo->bdev; struct ttm_mem_type_manager *man; @@ -1004,8 +993,7 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, return 0; } - ret = ttm_bo_mem_force_space(bo, mem_type, place, mem, - interruptible, no_wait_gpu); + ret = ttm_bo_mem_force_space(bo, mem_type, place, mem, ctx); if (ret == 0 && mem->mm_node) { mem->placement = cur_flags; return 0; @@ -1024,9 +1012,8 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, EXPORT_SYMBOL(ttm_bo_mem_space); static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, - struct ttm_placement *placement, - bool interruptible, - bool no_wait_gpu) + struct ttm_placement *placement, + struct ttm_operation_ctx *ctx) { int ret = 0; struct ttm_mem_reg mem; @@ -1041,12 +1028,10 @@ static int ttm_bo_move_buffer(struct ttm_buffer_object *bo, /* * Determine where to move the buffer. */ - ret = ttm_bo_mem_space(bo, placement, &mem, - interruptible, no_wait_gpu); + ret = ttm_bo_mem_space(bo, placement, &mem, ctx); if (ret) goto out_unlock; - ret = ttm_bo_handle_move_mem(bo, &mem, false, - interruptible, no_wait_gpu); + ret = ttm_bo_handle_move_mem(bo, &mem, false, ctx); out_unlock: if (ret && mem.mm_node) ttm_bo_mem_put(bo, &mem); @@ -1097,9 +1082,8 @@ bool ttm_bo_mem_compat(struct ttm_placement *placement, EXPORT_SYMBOL(ttm_bo_mem_compat); int ttm_bo_validate(struct ttm_buffer_object *bo, - struct ttm_placement *placement, - bool interruptible, - bool no_wait_gpu) + struct ttm_placement *placement, + struct ttm_operation_ctx *ctx) { int ret; uint32_t new_flags; @@ -1109,8 +1093,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, * Check whether we need to move buffer. */ if (!ttm_bo_mem_compat(placement, &bo->mem, &new_flags)) { - ret = ttm_bo_move_buffer(bo, placement, interruptible, - no_wait_gpu); + ret = ttm_bo_move_buffer(bo, placement, ctx); if (ret) return ret; } else { @@ -1139,7 +1122,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, enum ttm_bo_type type, struct ttm_placement *placement, uint32_t page_alignment, - bool interruptible, + struct ttm_operation_ctx *ctx, struct file *persistent_swap_storage, size_t acc_size, struct sg_table *sg, @@ -1226,7 +1209,7 @@ int ttm_bo_init_reserved(struct ttm_bo_device *bdev, } if (likely(!ret)) - ret = ttm_bo_validate(bo, placement, interruptible, false); + ret = ttm_bo_validate(bo, placement, ctx); if (unlikely(ret)) { if (!resv) @@ -1259,10 +1242,11 @@ int ttm_bo_init(struct ttm_bo_device *bdev, struct reservation_object *resv, void (*destroy) (struct ttm_buffer_object *)) { + struct ttm_operation_ctx ctx = { interruptible, false }; int ret; ret = ttm_bo_init_reserved(bdev, bo, size, type, placement, - page_alignment, interruptible, + page_alignment, &ctx, persistent_swap_storage, acc_size, sg, resv, destroy); if (ret) @@ -1334,6 +1318,7 @@ EXPORT_SYMBOL(ttm_bo_create); static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, unsigned mem_type) { + struct ttm_operation_ctx ctx = { false, false }; struct ttm_mem_type_manager *man = &bdev->man[mem_type]; struct ttm_bo_global *glob = bdev->glob; struct dma_fence *fence; @@ -1348,7 +1333,8 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { while (!list_empty(&man->lru[i])) { spin_unlock(&glob->lru_lock); - ret = ttm_mem_evict_first(bdev, mem_type, NULL, false, false); + ret = ttm_mem_evict_first(bdev, NULL, mem_type, + NULL, &ctx); if (ret) return ret; spin_lock(&glob->lru_lock); @@ -1554,13 +1540,10 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) cancel_delayed_work_sync(&bdev->wq); - while (ttm_bo_delayed_delete(bdev, true)) - ; - - spin_lock(&glob->lru_lock); - if (list_empty(&bdev->ddestroy)) + if (ttm_bo_delayed_delete(bdev, true)) TTM_DEBUG("Delayed destroy list was clean\n"); + spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) if (list_empty(&bdev->man[0].lru[0])) TTM_DEBUG("Swap list %d was clean\n", i); @@ -1718,7 +1701,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) spin_lock(&glob->lru_lock); for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i) { list_for_each_entry(bo, &glob->swap_lru[i], swap) { - ret = __ttm_bo_reserve(bo, false, true, NULL); + ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY; if (!ret) break; } @@ -1734,7 +1717,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) kref_get(&bo->list_kref); if (!list_empty(&bo->ddestroy)) { - ret = ttm_bo_cleanup_refs_and_unlock(bo, false, false); + ret = ttm_bo_cleanup_refs(bo, false, false, true); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -1748,6 +1731,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) if (bo->mem.mem_type != TTM_PL_SYSTEM || bo->ttm->caching_state != tt_cached) { + struct ttm_operation_ctx ctx = { false, false }; struct ttm_mem_reg evict_mem; evict_mem = bo->mem; @@ -1755,8 +1739,7 @@ static int ttm_bo_swapout(struct ttm_mem_shrink *shrink) evict_mem.placement = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED; evict_mem.mem_type = TTM_PL_SYSTEM; - ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, - false, false); + ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, &ctx); if (unlikely(ret != 0)) goto out; } @@ -1788,7 +1771,7 @@ out: * already swapped buffer. */ - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); kref_put(&bo->list_kref, ttm_bo_release_list); return ret; } @@ -1822,10 +1805,12 @@ int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo) return -ERESTARTSYS; if (!ww_mutex_is_locked(&bo->resv->lock)) goto out_unlock; - ret = __ttm_bo_reserve(bo, true, false, NULL); + ret = reservation_object_lock_interruptible(bo->resv, NULL); + if (ret == -EINTR) + ret = -ERESTARTSYS; if (unlikely(ret != 0)) goto out_unlock; - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); out_unlock: mutex_unlock(&bo->wu_mutex); diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c index 5e1bcabffef5..373ced0b2fc2 100644 --- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c +++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c @@ -38,7 +38,7 @@ static void ttm_eu_backoff_reservation_reverse(struct list_head *list, list_for_each_entry_continue_reverse(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } } @@ -69,7 +69,7 @@ void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket, struct ttm_buffer_object *bo = entry->bo; ttm_bo_add_to_lru(bo); - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } spin_unlock(&glob->lru_lock); @@ -112,7 +112,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket); if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) { - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); ret = -EBUSY; @@ -203,7 +203,7 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket, else reservation_object_add_excl_fence(bo->resv, fence); ttm_bo_add_to_lru(bo); - __ttm_bo_unreserve(bo); + reservation_object_unlock(bo->resv); } spin_unlock(&glob->lru_lock); if (ticket) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 8d7172e8381d..44343a2bf55c 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -81,6 +81,7 @@ struct ttm_page_pool { char *name; unsigned long nfrees; unsigned long nrefills; + unsigned int order; }; /** @@ -222,6 +223,17 @@ static struct kobj_type ttm_pool_kobj_type = { static struct ttm_pool_manager *_manager; #ifndef CONFIG_X86 +static int set_pages_wb(struct page *page, int numpages) +{ +#if IS_ENABLED(CONFIG_AGP) + int i; + + for (i = 0; i < numpages; i++) + unmap_page_from_agp(page++); +#endif + return 0; +} + static int set_pages_array_wb(struct page **pages, int addrinarray) { #if IS_ENABLED(CONFIG_AGP) @@ -284,13 +296,23 @@ static struct ttm_page_pool *ttm_get_pool(int flags, bool huge, } /* set memory back to wb and free the pages. */ -static void ttm_pages_put(struct page *pages[], unsigned npages) +static void ttm_pages_put(struct page *pages[], unsigned npages, + unsigned int order) { - unsigned i; - if (set_pages_array_wb(pages, npages)) - pr_err("Failed to set %d pages to wb!\n", npages); - for (i = 0; i < npages; ++i) - __free_page(pages[i]); + unsigned int i, pages_nr = (1 << order); + + if (order == 0) { + if (set_pages_array_wb(pages, npages)) + pr_err("Failed to set %d pages to wb!\n", npages); + } + + for (i = 0; i < npages; ++i) { + if (order > 0) { + if (set_pages_wb(pages[i], pages_nr)) + pr_err("Failed to set %d pages to wb!\n", pages_nr); + } + __free_pages(pages[i], order); + } } static void ttm_pool_update_free_locked(struct ttm_page_pool *pool, @@ -353,7 +375,7 @@ restart: */ spin_unlock_irqrestore(&pool->lock, irq_flags); - ttm_pages_put(pages_to_free, freed_pages); + ttm_pages_put(pages_to_free, freed_pages, pool->order); if (likely(nr_free != FREE_ALL_PAGES)) nr_free -= freed_pages; @@ -388,7 +410,7 @@ restart: spin_unlock_irqrestore(&pool->lock, irq_flags); if (freed_pages) - ttm_pages_put(pages_to_free, freed_pages); + ttm_pages_put(pages_to_free, freed_pages, pool->order); out: if (pages_to_free != static_buf) kfree(pages_to_free); @@ -412,6 +434,7 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) struct ttm_page_pool *pool; int shrink_pages = sc->nr_to_scan; unsigned long freed = 0; + unsigned int nr_free_pool; if (!mutex_trylock(&lock)) return SHRINK_STOP; @@ -419,12 +442,19 @@ ttm_pool_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) /* select start pool in round robin fashion */ for (i = 0; i < NUM_POOLS; ++i) { unsigned nr_free = shrink_pages; + unsigned page_nr; + if (shrink_pages == 0) break; + pool = &_manager->pools[(i + pool_offset)%NUM_POOLS]; + page_nr = (1 << pool->order); /* OK to use static buffer since global mutex is held. */ - shrink_pages = ttm_page_pool_free(pool, nr_free, true); - freed += nr_free - shrink_pages; + nr_free_pool = roundup(nr_free, page_nr) >> pool->order; + shrink_pages = ttm_page_pool_free(pool, nr_free_pool, true); + freed += (nr_free_pool - shrink_pages) << pool->order; + if (freed >= sc->nr_to_scan) + break; } mutex_unlock(&lock); return freed; @@ -436,9 +466,12 @@ ttm_pool_shrink_count(struct shrinker *shrink, struct shrink_control *sc) { unsigned i; unsigned long count = 0; + struct ttm_page_pool *pool; - for (i = 0; i < NUM_POOLS; ++i) - count += _manager->pools[i].npages; + for (i = 0; i < NUM_POOLS; ++i) { + pool = &_manager->pools[i]; + count += (pool->npages << pool->order); + } return count; } @@ -510,8 +543,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, int r = 0; unsigned i, j, cpages; unsigned npages = 1 << order; - unsigned max_cpages = min(count, - (unsigned)(PAGE_SIZE/sizeof(struct page *))); + unsigned max_cpages = min(count, (unsigned)NUM_PAGES_TO_ALLOC); /* allocate array for page caching change */ caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL); @@ -845,7 +877,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, #endif struct list_head plist; struct page *p = NULL; - unsigned count; + unsigned count, first; int r; /* No pool for cached pages */ @@ -886,6 +918,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, } #endif + first = i; while (npages) { p = alloc_page(gfp_flags); if (!p) { @@ -893,6 +926,10 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, return -ENOMEM; } + /* Swap the pages if we detect consecutive order */ + if (i > first && pages[i - 1] == p - 1) + swap(p, pages[i - 1]); + pages[i++] = p; --npages; } @@ -921,8 +958,15 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, r = ttm_page_pool_get_pages(pool, &plist, flags, cstate, npages - count, 0); - list_for_each_entry(p, &plist, lru) - pages[count++] = p; + first = count; + list_for_each_entry(p, &plist, lru) { + struct page *tmp = p; + + /* Swap the pages if we detect consecutive order */ + if (count > first && pages[count - 1] == tmp - 1) + swap(tmp, pages[count - 1]); + pages[count++] = tmp; + } if (r) { /* If there is any pages in the list put them back to @@ -937,7 +981,7 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, } static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags, - char *name) + char *name, unsigned int order) { spin_lock_init(&pool->lock); pool->fill_lock = false; @@ -945,11 +989,17 @@ static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, gfp_t flags, pool->npages = pool->nfrees = 0; pool->gfp_flags = flags; pool->name = name; + pool->order = order; } int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) { int ret; +#ifdef CONFIG_TRANSPARENT_HUGEPAGE + unsigned order = HPAGE_PMD_ORDER; +#else + unsigned order = 0; +#endif WARN_ON(_manager); @@ -957,23 +1007,23 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) _manager = kzalloc(sizeof(*_manager), GFP_KERNEL); - ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc"); + ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc", 0); - ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc"); + ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc", 0); ttm_page_pool_init_locked(&_manager->wc_pool_dma32, - GFP_USER | GFP_DMA32, "wc dma"); + GFP_USER | GFP_DMA32, "wc dma", 0); ttm_page_pool_init_locked(&_manager->uc_pool_dma32, - GFP_USER | GFP_DMA32, "uc dma"); + GFP_USER | GFP_DMA32, "uc dma", 0); ttm_page_pool_init_locked(&_manager->wc_pool_huge, GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP), - "wc huge"); + "wc huge", order); ttm_page_pool_init_locked(&_manager->uc_pool_huge, GFP_TRANSHUGE & ~(__GFP_MOVABLE | __GFP_COMP) - , "uc huge"); + , "uc huge", order); _manager->options.max_size = max_pages; _manager->options.small = SMALL_ALLOCATION; diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c index 6b2627fe9bc1..bda00b2ab51c 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c @@ -1244,15 +1244,12 @@ int ttm_dma_page_alloc_debugfs(struct seq_file *m, void *data) { struct device_pools *p; struct dma_pool *pool = NULL; - char *h[] = {"pool", "refills", "pages freed", "inuse", "available", - "name", "virt", "busaddr"}; if (!_manager) { seq_printf(m, "No pool allocator running.\n"); return 0; } - seq_printf(m, "%13s %12s %13s %8s %8s %8s\n", - h[0], h[1], h[2], h[3], h[4], h[5]); + seq_printf(m, " pool refills pages freed inuse available name\n"); mutex_lock(&_manager->lock); list_for_each_entry(p, &_manager->pools, pools) { struct device *dev = p->dev; diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c index 461f81aa1bbe..5720a0d4ac0a 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c @@ -56,6 +56,7 @@ static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, struct list_head *head) { + struct ttm_operation_ctx ctx = { false, false }; struct ttm_validate_buffer *buf; struct ttm_buffer_object *bo; struct virtio_gpu_object *qobj; @@ -68,7 +69,7 @@ static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, list_for_each_entry(buf, head, head) { bo = buf->bo; qobj = container_of(bo, struct virtio_gpu_object, tbo); - ret = ttm_bo_validate(bo, &qobj->placement, false, false); + ret = ttm_bo_validate(bo, &qobj->placement, &ctx); if (ret) { ttm_eu_backoff_reservation(ticket, head); return ret; @@ -352,6 +353,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, struct virtio_gpu_device *vgdev = dev->dev_private; struct virtio_gpu_fpriv *vfpriv = file->driver_priv; struct drm_virtgpu_3d_transfer_from_host *args = data; + struct ttm_operation_ctx ctx = { true, false }; struct drm_gem_object *gobj = NULL; struct virtio_gpu_object *qobj = NULL; struct virtio_gpu_fence *fence; @@ -372,8 +374,7 @@ static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, if (ret) goto out; - ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, - true, false); + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); if (unlikely(ret)) goto out_unres; @@ -399,6 +400,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, struct virtio_gpu_device *vgdev = dev->dev_private; struct virtio_gpu_fpriv *vfpriv = file->driver_priv; struct drm_virtgpu_3d_transfer_to_host *args = data; + struct ttm_operation_ctx ctx = { true, false }; struct drm_gem_object *gobj = NULL; struct virtio_gpu_object *qobj = NULL; struct virtio_gpu_fence *fence; @@ -416,8 +418,7 @@ static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, if (ret) goto out; - ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, - true, false); + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); if (unlikely(ret)) goto out_unres; diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c index cd389c5eaef5..488c6bd032fc 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ttm.c +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -369,14 +369,13 @@ static void virtio_gpu_move_null(struct ttm_buffer_object *bo, new_mem->mm_node = NULL; } -static int virtio_gpu_bo_move(struct ttm_buffer_object *bo, - bool evict, bool interruptible, - bool no_wait_gpu, +static int virtio_gpu_bo_move(struct ttm_buffer_object *bo, bool evict, + struct ttm_operation_ctx *ctx, struct ttm_mem_reg *new_mem) { int ret; - ret = ttm_bo_wait(bo, interruptible, no_wait_gpu); + ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); if (ret) return ret; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c index d87861bbe971..92df0b08c194 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c @@ -387,6 +387,7 @@ static int vmw_cotable_readback(struct vmw_resource *res) */ static int vmw_cotable_resize(struct vmw_resource *res, size_t new_size) { + struct ttm_operation_ctx ctx = { false, false }; struct vmw_private *dev_priv = res->dev_priv; struct vmw_cotable *vcotbl = vmw_cotable(res); struct vmw_dma_buffer *buf, *old_buf = res->backup; @@ -455,7 +456,7 @@ static int vmw_cotable_resize(struct vmw_resource *res, size_t new_size) } /* Unpin new buffer, and switch backup buffers. */ - ret = ttm_bo_validate(bo, &vmw_mob_placement, false, false); + ret = ttm_bo_validate(bo, &vmw_mob_placement, &ctx); if (unlikely(ret != 0)) { DRM_ERROR("Failed validating new COTable backup buffer.\n"); goto out_wait; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c index 0cd889015dc5..d45d2caffa5a 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_dmabuf.c @@ -47,6 +47,7 @@ int vmw_dmabuf_pin_in_placement(struct vmw_private *dev_priv, struct ttm_placement *placement, bool interruptible) { + struct ttm_operation_ctx ctx = {interruptible, false }; struct ttm_buffer_object *bo = &buf->base; int ret; uint32_t new_flags; @@ -65,7 +66,7 @@ int vmw_dmabuf_pin_in_placement(struct vmw_private *dev_priv, ret = ttm_bo_mem_compat(placement, &bo->mem, &new_flags) == true ? 0 : -EINVAL; else - ret = ttm_bo_validate(bo, placement, interruptible, false); + ret = ttm_bo_validate(bo, placement, &ctx); if (!ret) vmw_bo_pin_reserved(buf, true); @@ -95,6 +96,7 @@ int vmw_dmabuf_pin_in_vram_or_gmr(struct vmw_private *dev_priv, struct vmw_dma_buffer *buf, bool interruptible) { + struct ttm_operation_ctx ctx = {interruptible, false }; struct ttm_buffer_object *bo = &buf->base; int ret; uint32_t new_flags; @@ -115,12 +117,11 @@ int vmw_dmabuf_pin_in_vram_or_gmr(struct vmw_private *dev_priv, goto out_unreserve; } - ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, interruptible, - false); + ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, &ctx); if (likely(ret == 0) || ret == -ERESTARTSYS) goto out_unreserve; - ret = ttm_bo_validate(bo, &vmw_vram_placement, interruptible, false); + ret = ttm_bo_validate(bo, &vmw_vram_placement, &ctx); out_unreserve: if (!ret) @@ -170,6 +171,7 @@ int vmw_dmabuf_pin_in_start_of_vram(struct vmw_private *dev_priv, struct vmw_dma_buffer *buf, bool interruptible) { + struct ttm_operation_ctx ctx = {interruptible, false }; struct ttm_buffer_object *bo = &buf->base; struct ttm_placement placement; struct ttm_place place; @@ -200,14 +202,16 @@ int vmw_dmabuf_pin_in_start_of_vram(struct vmw_private *dev_priv, if (bo->mem.mem_type == TTM_PL_VRAM && bo->mem.start < bo->num_pages && bo->mem.start > 0 && - buf->pin_count == 0) - (void) ttm_bo_validate(bo, &vmw_sys_placement, false, false); + buf->pin_count == 0) { + ctx.interruptible = false; + (void) ttm_bo_validate(bo, &vmw_sys_placement, &ctx); + } if (buf->pin_count > 0) ret = ttm_bo_mem_compat(&placement, &bo->mem, &new_flags) == true ? 0 : -EINVAL; else - ret = ttm_bo_validate(bo, &placement, interruptible, false); + ret = ttm_bo_validate(bo, &placement, &ctx); /* For some reason we didn't end up at the start of vram */ WARN_ON(ret == 0 && bo->offset != 0); @@ -286,6 +290,7 @@ void vmw_bo_get_guest_ptr(const struct ttm_buffer_object *bo, */ void vmw_bo_pin_reserved(struct vmw_dma_buffer *vbo, bool pin) { + struct ttm_operation_ctx ctx = { false, true }; struct ttm_place pl; struct ttm_placement placement; struct ttm_buffer_object *bo = &vbo->base; @@ -314,7 +319,7 @@ void vmw_bo_pin_reserved(struct vmw_dma_buffer *vbo, bool pin) placement.num_placement = 1; placement.placement = &pl; - ret = ttm_bo_validate(bo, &placement, false, true); + ret = ttm_bo_validate(bo, &placement, &ctx); BUG_ON(ret != 0 || bo->mem.mem_type != old_mem_type); } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index 21c62a34e558..b700667f6f0b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -3701,14 +3701,14 @@ int vmw_validate_single_buffer(struct vmw_private *dev_priv, { struct vmw_dma_buffer *vbo = container_of(bo, struct vmw_dma_buffer, base); + struct ttm_operation_ctx ctx = { interruptible, true }; int ret; if (vbo->pin_count > 0) return 0; if (validate_as_mob) - return ttm_bo_validate(bo, &vmw_mob_placement, interruptible, - false); + return ttm_bo_validate(bo, &vmw_mob_placement, &ctx); /** * Put BO in VRAM if there is space, otherwise as a GMR. @@ -3717,8 +3717,7 @@ int vmw_validate_single_buffer(struct vmw_private *dev_priv, * used as a GMR, this will return -ENOMEM. */ - ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, interruptible, - false); + ret = ttm_bo_validate(bo, &vmw_vram_gmr_placement, &ctx); if (likely(ret == 0 || ret == -ERESTARTSYS)) return ret; @@ -3727,7 +3726,7 @@ int vmw_validate_single_buffer(struct vmw_private *dev_priv, * previous contents. */ - ret = ttm_bo_validate(bo, &vmw_vram_placement, interruptible, false); + ret = ttm_bo_validate(bo, &vmw_vram_placement, &ctx); return ret; } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c index a96f90f017d1..200904ff9a22 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c @@ -968,6 +968,7 @@ vmw_resource_check_buffer(struct vmw_resource *res, bool interruptible, struct ttm_validate_buffer *val_buf) { + struct ttm_operation_ctx ctx = { true, false }; struct list_head val_list; bool backup_dirty = false; int ret; @@ -992,7 +993,7 @@ vmw_resource_check_buffer(struct vmw_resource *res, backup_dirty = res->backup_dirty; ret = ttm_bo_validate(&res->backup->base, res->func->backup_placement, - true, false); + &ctx); if (unlikely(ret != 0)) goto out_no_validate; @@ -1446,6 +1447,7 @@ void vmw_resource_evict_all(struct vmw_private *dev_priv) */ int vmw_resource_pin(struct vmw_resource *res, bool interruptible) { + struct ttm_operation_ctx ctx = { interruptible, false }; struct vmw_private *dev_priv = res->dev_priv; int ret; @@ -1466,7 +1468,7 @@ int vmw_resource_pin(struct vmw_resource *res, bool interruptible) ret = ttm_bo_validate (&vbo->base, res->func->backup_placement, - interruptible, false); + &ctx); if (ret) { ttm_bo_unreserve(&vbo->base); goto out_no_validate; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c index 9b832f136813..004e18b8832c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c @@ -970,6 +970,7 @@ int vmw_compat_shader_add(struct vmw_private *dev_priv, size_t size, struct list_head *list) { + struct ttm_operation_ctx ctx = { false, true }; struct vmw_dma_buffer *buf; struct ttm_bo_kmap_obj map; bool is_iomem; @@ -1005,7 +1006,7 @@ int vmw_compat_shader_add(struct vmw_private *dev_priv, WARN_ON(is_iomem); ttm_bo_kunmap(&map); - ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, false, true); + ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, &ctx); WARN_ON(ret != 0); ttm_bo_unreserve(&buf->base); |