diff options
| author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2020-05-19 16:11:17 +0300 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2020-05-21 14:16:43 -0700 |
| commit | 82ea174dc5425d4e85e25d0c4ba961a2e494392a (patch) | |
| tree | 98155b751acc7ff1cf38e95dc3ca16a985a557b7 /drivers/gpu | |
| parent | cd19154608610ab4cdd6c039e9214b8dd281845c (diff) | |
drm/i915: Remove unneeded hack now for CDCLK
No need to bump up CDCLK now, as it is now correctly
calculated, accounting for DBuf BW as BSpec says.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200519131117.17190-8-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4c38d20db9c3..dda9bae02a86 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2070,18 +2070,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) /* Account for additional needs from the planes */ min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); - /* - * HACK. Currently for TGL platforms we calculate - * min_cdclk initially based on pixel_rate divided - * by 2, accounting for also plane requirements, - * however in some cases the lowest possible CDCLK - * doesn't work and causing the underruns. - * Explicitly stating here that this seems to be currently - * rather a Hack, than final solution. - */ - if (IS_TIGERLAKE(dev_priv)) - min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); - if (min_cdclk > dev_priv->max_cdclk_freq) { drm_dbg_kms(&dev_priv->drm, "required cdclk (%d kHz) exceeds max (%d kHz)\n", |