diff options
| author | Chuanxiao Dong <chuanxiao.dong@intel.com> | 2017-03-21 09:32:19 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-03-21 10:45:57 +0800 |
| commit | 4a53148868493bd5e0b18a9814aaa20bf74e3b26 (patch) | |
| tree | 9dbe854aa66387365f471f418fca2c7a1f025ffb /drivers/gpu | |
| parent | 975629c3f76ce3d86e1f943db9847e0312a98daf (diff) | |
drm/i915/gvt: fix wrong offset when loading RCS mocs
Fix the wrong offset of the RCS specific mocs
Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch")
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/render.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c index 95ee091ce085..0beb83563b08 100644 --- a/drivers/gpu/drm/i915/gvt/render.c +++ b/drivers/gpu/drm/i915/gvt/render.c @@ -207,7 +207,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) l3_offset.reg = 0xb020; for (i = 0; i < 32; i++) { gen9_render_mocs_L3[i] = I915_READ(l3_offset); - I915_WRITE(l3_offset, vgpu_vreg(vgpu, offset)); + I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset)); POSTING_READ(l3_offset); l3_offset.reg += 4; } |