diff options
| author | Dave Airlie <airlied@redhat.com> | 2021-06-24 07:15:17 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2021-06-24 07:21:16 +1000 |
| commit | 334200bf52f0637a5ab8331c557dfcecbb9c30fa (patch) | |
| tree | 506009c182f6204a0998e2b892716bfa8cbac6e0 /drivers/gpu | |
| parent | 61c0cb8ae7943b4fad5d62213c1748f1a07fe594 (diff) | |
| parent | e88bbc91849b2bf57683119c339e52916d34433f (diff) | |
Merge tag 'drm-msm-next-2021-06-23b' of https://gitlab.freedesktop.org/drm/msm into drm-next
* devcoredump support for display errors
* dpu: irq cleanup/refactor
* dpu: dt bindings conversion to yaml
* dsi: dt bindings conversion to yaml
* mdp5: alpha/blend_mode/zpos support
* a6xx: cached coherent buffer support
* a660 support
* gpu iova fault improvements:
- info about which block triggered the fault, etc
- generation of gpu devcoredump on fault
* assortment of other cleanups and fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs4=qsGBBbyn-4JWqW4-YUSTKh67X3DsPQ=T2D9aXKqNA@mail.gmail.com
Diffstat (limited to 'drivers/gpu')
117 files changed, 5990 insertions, 5847 deletions
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index a8bbb021684b..d820423fac32 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2014 Red Hat * Copyright (C) 2014 Intel Corp. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1609,9 +1610,20 @@ commit: } EXPORT_SYMBOL(__drm_atomic_helper_set_config); -void drm_atomic_print_state(const struct drm_atomic_state *state) +/** + * drm_atomic_print_new_state - prints drm atomic state + * @state: atomic configuration to check + * @p: drm printer + * + * This functions prints the drm atomic state snapshot using the drm printer + * which is passed to it. This snapshot can be used for debugging purposes. + * + * Note that this function looks into the new state objects and hence its not + * safe to be used after the call to drm_atomic_helper_commit_hw_done(). + */ +void drm_atomic_print_new_state(const struct drm_atomic_state *state, + struct drm_printer *p) { - struct drm_printer p = drm_info_printer(state->dev->dev); struct drm_plane *plane; struct drm_plane_state *plane_state; struct drm_crtc *crtc; @@ -1620,17 +1632,23 @@ void drm_atomic_print_state(const struct drm_atomic_state *state) struct drm_connector_state *connector_state; int i; + if (!p) { + DRM_ERROR("invalid drm printer\n"); + return; + } + DRM_DEBUG_ATOMIC("checking %p\n", state); for_each_new_plane_in_state(state, plane, plane_state, i) - drm_atomic_plane_print_state(&p, plane_state); + drm_atomic_plane_print_state(p, plane_state); for_each_new_crtc_in_state(state, crtc, crtc_state, i) - drm_atomic_crtc_print_state(&p, crtc_state); + drm_atomic_crtc_print_state(p, crtc_state); for_each_new_connector_in_state(state, connector, connector_state, i) - drm_atomic_connector_print_state(&p, connector_state); + drm_atomic_connector_print_state(p, connector_state); } +EXPORT_SYMBOL(drm_atomic_print_new_state); static void __drm_state_dump(struct drm_device *dev, struct drm_printer *p, bool take_locks) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 438e9585b225..7e48d40600ff 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -2,6 +2,7 @@ * Copyright (C) 2014 Red Hat * Copyright (C) 2014 Intel Corp. * Copyright (C) 2018 Intel Corp. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -1321,6 +1322,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, struct drm_out_fence_state *fence_state; int ret = 0; unsigned int i, j, num_fences; + struct drm_printer p = drm_info_printer(dev->dev); /* disallow for drivers not supporting atomic: */ if (!drm_core_check_feature(dev, DRIVER_ATOMIC)) @@ -1453,7 +1455,7 @@ retry: ret = drm_atomic_nonblocking_commit(state); } else { if (drm_debug_enabled(DRM_UT_STATE)) - drm_atomic_print_state(state); + drm_atomic_print_new_state(state, &p); ret = drm_atomic_commit(state); } diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 54d4cf1233e9..1ca51addb589 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -5,6 +5,7 @@ * Jesse Barnes <jesse.barnes@intel.com> * Copyright © 2014 Intel Corporation * Daniel Vetter <daniel.vetter@ffwll.ch> + * Copyright (c) 2020, The Linux Foundation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -236,7 +237,8 @@ int __drm_atomic_helper_disable_plane(struct drm_plane *plane, int __drm_atomic_helper_set_config(struct drm_mode_set *set, struct drm_atomic_state *state); -void drm_atomic_print_state(const struct drm_atomic_state *state); +void drm_atomic_print_new_state(const struct drm_atomic_state *state, + struct drm_printer *p); /* drm_atomic_uapi.c */ int drm_atomic_connector_commit_dpms(struct drm_atomic_state *state, diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 610d630326bb..2c00aa70b708 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -58,7 +58,6 @@ msm-y := \ disp/dpu1/dpu_encoder_phys_cmd.o \ disp/dpu1/dpu_encoder_phys_vid.o \ disp/dpu1/dpu_formats.o \ - disp/dpu1/dpu_hw_blk.o \ disp/dpu1/dpu_hw_catalog.o \ disp/dpu1/dpu_hw_ctl.o \ disp/dpu1/dpu_hw_interrupts.o \ @@ -77,6 +76,8 @@ msm-y := \ disp/dpu1/dpu_plane.o \ disp/dpu1/dpu_rm.o \ disp/dpu1/dpu_vbif.o \ + disp/msm_disp_snapshot.o \ + disp/msm_disp_snapshot_util.o \ msm_atomic.o \ msm_atomic_tracepoints.o \ msm_debugfs.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index 54e1b2aa57d5..4ff529576093 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -1258,11 +1258,17 @@ static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) #define REG_A2XX_NQWAIT_UNTIL 0x00000394 -#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 +#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395 -#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 +#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396 -#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 +#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397 + +#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398 + +#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399 + +#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a #define REG_A2XX_RBBM_DEBUG 0x0000039b @@ -2922,10 +2928,28 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 +#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05 + +#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06 + +#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07 + #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 +#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a + +#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b + +#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c + +#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d + +#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e + +#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f + #define REG_A2XX_SQ_TEX_0 0x00000000 #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h index 16f9ef453bf8..e106b65abe26 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -1215,7 +1215,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) { - return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; } static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } @@ -1328,7 +1328,7 @@ static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) { - return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; } #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 @@ -1342,7 +1342,7 @@ static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) { - return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; } #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 @@ -1356,7 +1356,7 @@ static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) { - return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; } #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 @@ -1370,7 +1370,7 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) { - return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; } #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h index a7eaf2c83fe2..b26ede96ae2a 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -1085,7 +1085,7 @@ static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) { - return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; } #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 @@ -1113,7 +1113,7 @@ static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) { - return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; } #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 @@ -1141,7 +1141,7 @@ static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) { - return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; } #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 @@ -1169,7 +1169,7 @@ static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) { - return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; } #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 7b9fcfe95c04..1e575ca1f270 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -2021,6 +2021,7 @@ static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 #define REG_A5XX_RBBM_STATUS3 0x00000530 +#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 @@ -2351,6 +2352,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 +#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 @@ -2808,7 +2810,19 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_GRAS_CL_CNTL 0x0000e000 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 -#define REG_A5XX_UNKNOWN_E001 0x0000e001 +#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001 +#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff +#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 +static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) +{ + return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; +} +#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 +#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 +static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) +{ + return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; +} #define REG_A5XX_UNKNOWN_E004 0x0000e004 @@ -3345,7 +3359,7 @@ static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) { - return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; } #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 @@ -3373,7 +3387,7 @@ static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) { - return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; } #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 @@ -3401,7 +3415,7 @@ static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) { - return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; } #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 @@ -3429,7 +3443,7 @@ static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) { - return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; + return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; } #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 @@ -3806,7 +3820,25 @@ static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 -#define REG_A5XX_UNKNOWN_E29A 0x0000e29a +#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a +#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff +#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0 +static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val) +{ + return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK; +} +#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; +} +#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; +} #define REG_A5XX_VPC_PACK 0x0000e29d #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff @@ -3910,7 +3942,13 @@ static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su } #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040 -#define REG_A5XX_UNKNOWN_E389 0x0000e389 +#define REG_A5XX_PC_CLIP_CNTL 0x0000e389 +#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff +#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0 +static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val) +{ + return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK; +} #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c @@ -4302,7 +4340,12 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 -#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001 +#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff +#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 +static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) +{ + return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; +} #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 @@ -5192,8 +5235,8 @@ static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) } #define REG_A5XX_TEX_SAMP_2 0x00000002 -#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0 -#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4 +#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80 +#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) { return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; @@ -5273,6 +5316,7 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) } #define REG_A5XX_TEX_CONST_2 0x00000002 +#define A5XX_TEX_CONST_2_UNK4 0x00000010 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val) @@ -5291,6 +5335,7 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) { return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; } +#define A5XX_TEX_CONST_2_UNK31 0x80000000 #define REG_A5XX_TEX_CONST_3 0x00000003 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index ce13d49e615b..7a271de9a212 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -902,7 +902,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) if (!a5xx_gpu->shadow_bo) { a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, sizeof(u32) * gpu->nr_rings, - MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, + MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &a5xx_gpu->shadow_bo, &a5xx_gpu->shadow_iova); @@ -1075,7 +1075,7 @@ bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return true; } -static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) +static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) { struct msm_gpu *gpu = arg; pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", @@ -1085,7 +1085,7 @@ static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)), gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7))); - return -EFAULT; + return 0; } static void a5xx_cp_err_irq(struct msm_gpu *gpu) @@ -1200,6 +1200,15 @@ static void a5xx_fault_detect_irq(struct msm_gpu *gpu) struct drm_device *dev = gpu->dev; struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); + /* + * If stalled on SMMU fault, we could trip the GPU's hang detection, + * but the fault handler will trigger the devcore dump, and we want + * to otherwise resume normally rather than killing the submit, so + * just bail. + */ + if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)) + return; + DRM_DEV_ERROR(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", ring ? ring->id : -1, ring ? ring->seqno : 0, gpu_read(gpu, REG_A5XX_RBBM_STATUS), @@ -1407,7 +1416,7 @@ static int a5xx_crashdumper_init(struct msm_gpu *gpu, struct a5xx_crashdumper *dumper) { dumper->ptr = msm_gem_kernel_new_locked(gpu->dev, - SZ_1M, MSM_BO_UNCACHED, gpu->aspace, + SZ_1M, MSM_BO_WC, gpu->aspace, &dumper->bo, &dumper->iova); if (!IS_ERR(dumper->ptr)) @@ -1523,6 +1532,7 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) { struct a5xx_gpu_state *a5xx_state = kzalloc(sizeof(*a5xx_state), GFP_KERNEL); + bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)); if (!a5xx_state) return ERR_PTR(-ENOMEM); @@ -1535,8 +1545,13 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS); - /* Get the HLSQ regs with the help of the crashdumper */ - a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state); + /* + * Get the HLSQ regs with the help of the crashdumper, but only if + * we are not stalled in an iommu fault (in which case the crashdumper + * would not have access to memory) + */ + if (!stalled) + a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state); a5xx_set_hwcg(gpu, true); @@ -1705,7 +1720,7 @@ static void check_speed_bin(struct device *dev) nvmem_cell_put(cell); } - dev_pm_opp_set_supported_hw(dev, &val, 1); + devm_pm_opp_set_supported_hw(dev, &val, 1); } struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index c35b06b46fcc..cdb165236a88 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -363,7 +363,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu) bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2; ptr = msm_gem_kernel_new_locked(drm, bosize, - MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, + MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &a5xx_gpu->gpmu_bo, &a5xx_gpu->gpmu_iova); if (IS_ERR(ptr)) return; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c index 42eaef7ad7c7..ee72510ff8ce 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_preempt.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_preempt.c @@ -230,7 +230,7 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, ptr = msm_gem_kernel_new(gpu->dev, A5XX_PREEMPT_RECORD_SIZE + A5XX_PREEMPT_COUNTER_SIZE, - MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova); + MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &bo, &iova); if (IS_ERR(ptr)) return PTR_ERR(ptr); @@ -238,7 +238,7 @@ static int preempt_init_ring(struct a5xx_gpu *a5xx_gpu, /* The buffer to store counters needs to be unprivileged */ counters = msm_gem_kernel_new(gpu->dev, A5XX_PREEMPT_COUNTER_SIZE, - MSM_BO_UNCACHED, gpu->aspace, &counters_bo, &counters_iova); + MSM_BO_WC, gpu->aspace, &counters_bo, &counters_iova); if (IS_ERR(counters)) { msm_gem_kernel_put(bo, gpu->aspace, true); return PTR_ERR(counters); diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 920c5e6b8e96..a3cb3d988ba4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -168,7 +168,7 @@ enum a6xx_format { FMT6_ASTC_10x10 = 204, FMT6_ASTC_12x10 = 205, FMT6_ASTC_12x12 = 206, - FMT6_S8Z24_UINT = 234, + FMT6_Z24_UINT_S8_UINT = 234, FMT6_NONE = 255, }; @@ -907,6 +907,11 @@ enum a6xx_tess_output { TESS_CCW_TRIS = 3, }; +enum a6xx_threadsize { + THREAD64 = 0, + THREAD128 = 1, +}; + enum a6xx_tex_filter { A6XX_TEX_NEAREST = 0, A6XX_TEX_LINEAR = 1, @@ -1007,9 +1012,7 @@ enum a6xx_tex_type { #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 -#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830 - -#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831 +#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 #define REG_A6XX_CP_MISC_CNTL 0x00000840 @@ -1104,33 +1107,7 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 -#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9 - -#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da - -#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db - -#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc - -#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd +static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 @@ -1176,15 +1153,21 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f -#define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e +#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 + +#define REG_A6XX_CP_MRB_BASE 0x00000931 -#define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931 +#define REG_A6XX_CP_MRB_BASE_HI 0x00000932 -#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932 +#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 -#define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934 +#define REG_A6XX_CP_VSD_BASE 0x00000934 -#define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935 +#define REG_A6XX_CP_VSD_BASE_HI 0x00000935 + +#define REG_A6XX_CP_MRB_DWORDS 0x00000946 + +#define REG_A6XX_CP_VSD_DWORDS 0x00000947 #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000 @@ -1202,6 +1185,14 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK; } +#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c +#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000 +#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16 +static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val) +{ + return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK; +} + #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 @@ -1212,6 +1203,10 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 +#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 + +#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 + #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 @@ -1247,505 +1242,37 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 -#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400 - -#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401 - -#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402 - -#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403 - -#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404 - -#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405 - -#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406 - -#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407 - -#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408 - -#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409 - -#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a - -#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b - -#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c - -#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d - -#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e - -#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f - -#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410 - -#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411 - -#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412 - -#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413 - -#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414 - -#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415 - -#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416 - -#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417 - -#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418 - -#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419 - -#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a - -#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b - -#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c - -#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d - -#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e - -#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f - -#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423 - -#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424 - -#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425 - -#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426 - -#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427 - -#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428 - -#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429 - -#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a - -#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b - -#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c - -#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d - -#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e - -#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f - -#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430 - -#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431 - -#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432 - -#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433 - -#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434 - -#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435 - -#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436 - -#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437 - -#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438 - -#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439 - -#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a - -#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b - -#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c - -#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d - -#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e - -#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f - -#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440 - -#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441 - -#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442 - -#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449 - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e - -#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f - -#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450 - -#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451 - -#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452 - -#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453 - -#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454 - -#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455 - -#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456 - -#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457 - -#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458 - -#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459 - -#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a - -#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b - -#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c - -#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d - -#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e - -#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f - -#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460 - -#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461 - -#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462 - -#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463 - -#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464 - -#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 - -#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 - -#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 - -#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 - -#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 - -#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a - -#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b - -#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c - -#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d - -#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e - -#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f - -#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470 - -#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471 - -#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472 - -#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473 - -#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474 - -#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a - -#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b - -#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c - -#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d - -#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e - -#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f - -#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489 - -#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a - -#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b - -#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c - -#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d - -#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e - -#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f - -#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490 - -#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491 - -#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492 - -#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493 - -#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494 - -#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495 - -#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496 - -#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497 - -#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498 - -#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499 - -#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a - -#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b - -#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c - -#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d - -#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e - -#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f - -#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0 - -#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1 - -#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2 - -#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3 - -#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4 - -#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5 - -#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6 - -#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7 - -#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8 - -#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9 - -#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa - -#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab - -#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac - -#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad - -#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae - -#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af - -#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0 - -#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1 - -#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2 - -#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3 - -#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4 - -#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba +static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb +static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc +static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd +static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be +static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf +static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } -#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4 - -#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5 - -#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6 - -#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7 - -#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8 - -#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9 - -#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca - -#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb - -#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc - -#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd - -#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce - -#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf - -#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0 - -#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1 - -#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2 - -#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3 - -#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4 - -#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5 - -#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6 - -#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7 - -#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8 - -#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9 - -#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da - -#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db - -#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc - -#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd - -#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de - -#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df - -#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0 - -#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1 - -#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2 - -#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3 - -#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4 - -#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5 - -#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6 - -#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7 - -#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8 - -#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9 - -#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea - -#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb - -#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec - -#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed - -#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee - -#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef - -#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0 - -#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1 - -#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2 - -#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3 - -#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4 - -#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5 - -#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6 - -#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7 - -#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8 - -#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9 +static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 @@ -1761,13 +1288,7 @@ static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509 - -#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a +static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b @@ -2240,46 +1761,12 @@ static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 -#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 - -#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 - -#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14 - -#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15 +static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 -#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616 - -#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617 - #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 @@ -2316,119 +1803,9 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; } -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26 - -#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 - -#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 - -#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a - -#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b +static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } -#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c - -#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d - -#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e - -#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f - -#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26 - -#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27 - -#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 - -#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b - -#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619 - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a - -#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b +#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c #define REG_A6XX_VBIF_VERSION 0x00003000 @@ -2507,6 +1884,8 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a +#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 + #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 @@ -2555,36 +1934,6 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 -#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 -#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff -#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; -} -#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; -} - -#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 -#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 -#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff -#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 -static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) -{ - return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; -} -#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000 -#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 -static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) -{ - return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; -} - #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 @@ -2599,10 +1948,6 @@ static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; } -#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03 - -#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04 - #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 @@ -2647,20 +1992,12 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; } -#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30 - -#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31 - #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 -#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34 - -#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35 - #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 @@ -2849,12 +2186,20 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; } #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 -#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000 +#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) { return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; } +#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 +#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 +#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 +#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 +static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) +{ + return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; +} #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff @@ -3205,11 +2550,12 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 -#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0 -#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5 -static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val) +#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 +#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0 +#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6 +static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val) { - return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK; + return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK; } #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 @@ -3222,10 +2568,6 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val) return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; } -#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103 - -#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104 - #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 @@ -3248,10 +2590,6 @@ static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; } -#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106 - -#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 - #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 @@ -3406,29 +2744,11 @@ static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612 - -#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613 +static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614 +static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615 - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616 - -#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617 - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618 - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619 - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a - -#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b +static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } #define REG_A6XX_RB_BIN_CONTROL 0x00008800 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f @@ -3889,10 +3209,6 @@ static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; } -static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } - static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } #define A6XX_RB_MRT_BASE__MASK 0xffffffff #define A6XX_RB_MRT_BASE__SHIFT 0 @@ -4025,10 +3341,6 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; } -#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875 - -#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876 - #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 @@ -4134,10 +3446,6 @@ static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; } -#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884 - -#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885 - #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 @@ -4355,10 +3663,6 @@ static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; } -#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8 - -#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9 - #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 @@ -4383,10 +3687,6 @@ static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; } -#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc - -#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd - #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 @@ -4412,7 +3712,7 @@ static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) #define REG_A6XX_RB_BLIT_INFO 0x000088e3 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 -#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 +#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 @@ -4459,10 +3759,6 @@ static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900 - -#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901 - #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 @@ -4493,10 +3789,6 @@ static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } - -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } - static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 @@ -4519,10 +3811,6 @@ static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } -#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927 - -#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928 - #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 @@ -4608,13 +3896,19 @@ static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; } #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 +#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 +#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 +#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 - -#define REG_A6XX_RB_2D_DST_LO 0x00008c18 - -#define REG_A6XX_RB_2D_DST_HI 0x00008c19 +#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 +#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 +static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) +{ + return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; +} +#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 #define REG_A6XX_RB_2D_DST 0x00008c18 #define A6XX_RB_2D_DST__MASK 0xffffffff @@ -4656,10 +3950,6 @@ static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; } -#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20 - -#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21 - #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 @@ -4740,41 +4030,13 @@ static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; } -#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16 - -#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17 - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18 - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19 - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a +static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } -#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b - -#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c +static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 -#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e - -#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f +static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b @@ -4895,6 +4157,8 @@ static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) } #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 +#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 +#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 @@ -4921,13 +4185,13 @@ static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } #define REG_A6XX_VPC_SO_CNTL 0x00009216 -#define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff -#define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val) +#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff +#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 +static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) { - return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK; + return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; } -#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000 +#define A6XX_VPC_SO_CNTL_RESET 0x00010000 #define REG_A6XX_VPC_SO_PROG 0x00009217 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 @@ -4957,10 +4221,6 @@ static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) } #define A6XX_VPC_SO_PROG_B_EN 0x00800000 -#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218 - -#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219 - #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 @@ -4979,10 +4239,6 @@ static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; } -static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } - static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 @@ -5009,10 +4265,6 @@ static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; } -static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } - -static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } - #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 @@ -5037,11 +4289,11 @@ static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) { return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; } -#define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000 -#define A6XX_VPC_VS_PACK_UNK24__SHIFT 24 -static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val) +#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 +#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 +static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) { - return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK; + return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; } #define REG_A6XX_VPC_GS_PACK 0x00009302 @@ -5063,11 +4315,11 @@ static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) { return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; } -#define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000 -#define A6XX_VPC_GS_PACK_UNK24__SHIFT 24 -static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val) +#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 +#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 +static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) { - return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK; + return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; } #define REG_A6XX_VPC_DS_PACK 0x00009303 @@ -5089,11 +4341,11 @@ static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) { return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; } -#define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000 -#define A6XX_VPC_DS_PACK_UNK24__SHIFT 24 -static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val) +#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 +#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 +static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) { - return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK; + return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; } #define REG_A6XX_VPC_CNTL_0 0x00009304 @@ -5110,24 +4362,43 @@ static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; } #define A6XX_VPC_CNTL_0_VARYING 0x00010000 -#define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000 -#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24 -static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val) +#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 +#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 +static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) { - return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK; + return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; } -#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305 -#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 -#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 -#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 -#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 -#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 -#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000 -#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16 -static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val) +#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 +#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 +#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 +static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) +{ + return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; +} +#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 +#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 +static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) +{ + return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; +} +#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 +#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 +static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) +{ + return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; +} +#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 +#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 +static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) { - return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK; + return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; +} +#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 +#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 +static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) +{ + return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; } #define REG_A6XX_VPC_SO_DISABLE 0x00009306 @@ -5141,32 +4412,22 @@ static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val) #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608 - -#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609 +static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 -#define REG_A6XX_PC_UNKNOWN_9801 0x00009801 -#define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff -#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0 -static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val) +#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 +#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff +#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 +static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) { - return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK; + return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; } -#define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000 -#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13 -static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val) +#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 +#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 +static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) { - return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK; + return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; } #define REG_A6XX_PC_TESS_CNTL 0x00009802 @@ -5221,6 +4482,8 @@ static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; } +#define REG_A6XX_PC_MARKER 0x00009880 + #define REG_A6XX_PC_POLYGON_MODE 0x00009981 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 @@ -5229,7 +4492,14 @@ static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; } -#define REG_A6XX_PC_UNKNOWN_9980 0x00009980 +#define REG_A6XX_PC_RASTER_CNTL 0x00009980 +#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 +#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 +static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) +{ + return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; +} +#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 @@ -5327,9 +4597,17 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; } -#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07 +#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 +#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 +#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 +#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c +#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 +static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) +{ + return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; +} -#define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08 +#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f @@ -5349,9 +4627,11 @@ static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 -#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08 +#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 -#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09 +#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 + +#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff @@ -5361,6 +4641,44 @@ static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; } +#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b +#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f +#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 +static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) +{ + return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; +} +#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 +#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 +static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) +{ + return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; +} +#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 +#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 +static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) +{ + return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; +} +#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 +#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 +static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) +{ + return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; +} +#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 +#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 +static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) +{ + return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; +} +#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 +#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 + +#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c + +#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d + #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 @@ -5397,21 +4715,10 @@ static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; } -#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38 +#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c +#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 -#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39 - -#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a - -#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b +static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 @@ -5448,6 +4755,12 @@ static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) { return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; } +#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 +#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 +static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) +{ + return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; +} #define REG_A6XX_VFD_CONTROL_2 0x0000a002 #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff @@ -5464,6 +4777,12 @@ static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) } #define REG_A6XX_VFD_CONTROL_3 0x0000a003 +#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff +#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0 +static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val) +{ + return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK; +} #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00 #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val) @@ -5484,6 +4803,12 @@ static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) } #define REG_A6XX_VFD_CONTROL_4 0x0000a004 +#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff +#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 +static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) +{ + return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; +} #define REG_A6XX_VFD_CONTROL_5 0x0000a005 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff @@ -5492,14 +4817,30 @@ static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) { return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; } +#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 +#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 +static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) +{ + return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; +} #define REG_A6XX_VFD_CONTROL_6 0x0000a006 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 +#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002 +#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004 -#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 +#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 +#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 +#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 +#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c +#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 +static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) +{ + return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; +} #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 @@ -5512,10 +4853,12 @@ static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } - -static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } +#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff +#define A6XX_VFD_FETCH_BASE__SHIFT 0 +static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) +{ + return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; +} static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } @@ -5572,7 +4915,19 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 +#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 + +static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } + #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 +#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 +#define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 +#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 +static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) +{ + return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; +} #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) @@ -5585,22 +4940,13 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } +#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; } -#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 @@ -5611,6 +4957,12 @@ static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) { return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; } +#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 +#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 +static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) +{ + return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; +} static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } @@ -5668,11 +5020,46 @@ static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; } -#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b +#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b -#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c +#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c +#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff +#define A6XX_SP_VS_OBJ_START__SHIFT 0 +static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) +{ + return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; +} -#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d +#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e +#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f +#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff +#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; +} + +#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 +#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} +#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 @@ -5694,7 +5081,7 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) { return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; } -#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000 +#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) { @@ -5703,7 +5090,22 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 +#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 +#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff +#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 +static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) +{ + return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK; +} + #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 +#define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000 +#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 +#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 +static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) +{ + return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; +} #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) @@ -5716,30 +5118,58 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } +#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; } -#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) + +#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 + +#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 + +#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 + +#define REG_A6XX_SP_HS_OBJ_START 0x0000a834 +#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff +#define A6XX_SP_HS_OBJ_START__SHIFT 0 +static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) { - return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; + return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; } -#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000 -#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831 - -#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833 +#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 +#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} -#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834 +#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 +#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff +#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; +} -#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835 +#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 +#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} +#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a @@ -5761,7 +5191,7 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) { return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; } -#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000 +#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) { @@ -5770,7 +5200,22 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c +#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d +#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff +#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 +static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) +{ + return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK; +} + #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 +#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000 +#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 +#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 +static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) +{ + return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; +} #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) @@ -5783,22 +5228,15 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } +#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; } -#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000 + +#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f @@ -5807,6 +5245,12 @@ static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) { return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; } +#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 +#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 +static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) +{ + return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; +} static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } @@ -5864,11 +5308,46 @@ static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; } -#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b +#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b -#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c +#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c +#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff +#define A6XX_SP_DS_OBJ_START__SHIFT 0 +static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) +{ + return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; +} -#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d +#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e +#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f +#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff +#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; +} + +#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 +#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} +#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 @@ -5890,7 +5369,7 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) { return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; } -#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000 +#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) { @@ -5899,7 +5378,22 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 +#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 +#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff +#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 +static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) +{ + return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK; +} + #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 +#define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000 +#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 +#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 +static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) +{ + return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; +} #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) @@ -5912,22 +5406,13 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } +#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; } -#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 @@ -6003,9 +5488,46 @@ static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; } -#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d +#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c + +#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d +#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff +#define A6XX_SP_GS_OBJ_START__SHIFT 0 +static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) +{ + return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; +} + +#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f +#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 +#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff +#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; +} -#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e +#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 +#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} +#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 @@ -6027,7 +5549,7 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) { return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; } -#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000 +#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) { @@ -6036,39 +5558,104 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 -#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0 - -#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1 - -#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2 - -#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3 - -#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4 - -#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5 - -#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6 - -#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7 +#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 +#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff +#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 +static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) +{ + return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK; +} -#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8 +#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 +#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff +#define A6XX_SP_VS_TEX_SAMP__SHIFT 0 +static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) +{ + return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; +} -#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9 +#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 +#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff +#define A6XX_SP_HS_TEX_SAMP__SHIFT 0 +static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) +{ + return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; +} -#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa +#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 +#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff +#define A6XX_SP_DS_TEX_SAMP__SHIFT 0 +static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) +{ + return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; +} -#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab +#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 +#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff +#define A6XX_SP_GS_TEX_SAMP__SHIFT 0 +static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) +{ + return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; +} -#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac +#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 +#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff +#define A6XX_SP_VS_TEX_CONST__SHIFT 0 +static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) +{ + return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; +} -#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad +#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa +#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff +#define A6XX_SP_HS_TEX_CONST__SHIFT 0 +static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) +{ + return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; +} -#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae +#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac +#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff +#define A6XX_SP_DS_TEX_CONST__SHIFT 0 +static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) +{ + return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; +} -#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af +#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae +#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff +#define A6XX_SP_GS_TEX_CONST__SHIFT 0 +static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) +{ + return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; +} #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 +#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 +#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 +static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; +} +#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 +#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 +#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 +#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 +#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 +#define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000 +#define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27 +static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val) +{ + return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK; +} +#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 +#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 +#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 +static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) +{ + return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; +} #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) @@ -6081,33 +5668,64 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } +#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; } -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 -#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982 +#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 -#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 +#define REG_A6XX_SP_FS_OBJ_START 0x0000a983 +#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff +#define A6XX_SP_FS_OBJ_START__SHIFT 0 +static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) +{ + return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; +} -#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 +#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 +#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 +#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff +#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; +} + +#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 +#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} +#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 -#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001 +#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff +#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 +static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) +{ + return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; +} #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 @@ -6201,6 +5819,17 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; } +static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } + +static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } +#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff +#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 +static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) +{ + return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; +} +#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 + static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } @@ -6212,6 +5841,7 @@ static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) } #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 +#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 @@ -6227,6 +5857,12 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) { return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK; } +#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000 +#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12 +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val) +{ + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK; +} static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } @@ -6272,13 +5908,13 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } -#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff +#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) { return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; } -#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000 +#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) { @@ -6289,50 +5925,31 @@ static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 -#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 -#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001 -#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0 -static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val) +#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 +#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff +#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 +static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) { - return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK; + return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK; } -#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3 - -#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba - -#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0 - -#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1 - -#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2 - -#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3 - -#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4 - -#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5 - -#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6 - -#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7 - -static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } - -static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } - -static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } - -static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } -#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff -#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 -static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) +#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 +#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 +#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 +static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) { - return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; + return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; +} +#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 +#define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000 +#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 +#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 +#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 +static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) +{ + return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; } -#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 - -#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) @@ -6345,26 +5962,68 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; } +#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; } -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) + +#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 +#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f +#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 +static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) { - return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; + return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; } -#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 +#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 +#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 -#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4 +#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 -#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5 +#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 + +#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 +#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff +#define A6XX_SP_CS_OBJ_START__SHIFT 0 +static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) +{ + return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; +} + +#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 +#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 +#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff +#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; +} + +#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 +#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} +#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 + +#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 @@ -6384,7 +6043,7 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) { return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; } -#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000 +#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) { @@ -6393,13 +6052,65 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc -#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2 +#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd +#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff +#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 +static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) +{ + return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK; +} -#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3 +#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 +#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff +#define A6XX_SP_FS_TEX_SAMP__SHIFT 0 +static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) +{ + return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; +} + +#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 +#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff +#define A6XX_SP_CS_TEX_SAMP__SHIFT 0 +static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) +{ + return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; +} + +#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 +#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff +#define A6XX_SP_FS_TEX_CONST__SHIFT 0 +static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) +{ + return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; +} + +#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 +#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff +#define A6XX_SP_CS_TEX_CONST__SHIFT 0 +static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) +{ + return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; +} + +static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } + +static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } + +#define REG_A6XX_SP_CS_IBO 0x0000a9f2 +#define A6XX_SP_CS_IBO__MASK 0xffffffff +#define A6XX_SP_CS_IBO__SHIFT 0 +static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) +{ + return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; +} #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 -#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00 +#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 +#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 +#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002 +#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004 +#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 @@ -6419,7 +6130,7 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) { return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; } -#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000 +#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) { @@ -6432,9 +6143,13 @@ static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab1 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } -#define REG_A6XX_SP_IBO_LO 0x0000ab1a - -#define REG_A6XX_SP_IBO_HI 0x0000ab1b +#define REG_A6XX_SP_IBO 0x0000ab1a +#define A6XX_SP_IBO__MASK 0xffffffff +#define A6XX_SP_IBO__SHIFT 0 +static inline uint32_t A6XX_SP_IBO(uint32_t val) +{ + return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; +} #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 @@ -6458,18 +6173,41 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 +#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 + +#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 + #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 -#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 +#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 +#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 + +#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f +#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 +#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 +#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 +#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 +#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 +#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 -#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f +static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 +#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff +#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; +} #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 +#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 + +#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 + #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 @@ -6477,6 +6215,12 @@ static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples v { return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; } +#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c +#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 +static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) +{ + return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; +} #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -6488,10 +6232,12 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 - -#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302 - -#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303 +#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff +#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 +static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) +{ + return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; +} #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 @@ -6597,6 +6343,20 @@ static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } +#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 +#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff +#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; +} +#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 +#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; +} + #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 @@ -6627,9 +6387,19 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; } #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 +#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 +#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 +#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 +#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 +#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 +static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) +{ + return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; +} +#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff @@ -6645,43 +6415,131 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; } -#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2 - -#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3 - #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 +#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff +#define A6XX_SP_PS_2D_SRC__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) +{ + return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; +} #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 -#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00 +#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff +#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) +{ + return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; +} +#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) { return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; } -#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca +#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 +#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff +#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) +{ + return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; +} -#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb +#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 +#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff +#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) +{ + return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; +} + +#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 +#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff +#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) +{ + return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; +} #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca +#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff +#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) +{ + return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; +} #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val) +#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff +#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 +static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) +{ + return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; +} + +#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd + +#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce + +#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf + +#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 + +#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 +#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff +#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; +} +#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 +#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; +} + +#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600 + +#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 + +#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 + +#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 +#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 +#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 +#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 +static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) +{ + return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; +} +#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 +#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 +#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 +static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK; + return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; } -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800 -#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11 -static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val) +#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 +#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 +static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) { - return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK; + return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; } -#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600 +#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 -#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605 +#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 + +#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 + +#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a + +#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b + +#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c + +static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff @@ -6722,10 +6580,31 @@ static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 +#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff +#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 +static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) +{ + return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; +} #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 -#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980 +#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 +#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 +#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 +static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; +} +#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 +#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc +#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 +static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) +{ + return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; +} + +#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 @@ -6808,6 +6687,18 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) } #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 +#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff +#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK; +} +#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00 +#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8 +static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK; +} #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff @@ -6899,17 +6790,17 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) { return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; } -#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 -#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 -static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) +#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 +#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 +static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) { - return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; + return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; } -#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 -#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 -static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) +#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 +#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 +static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) { - return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; + return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; } #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 @@ -6918,7 +6809,21 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; } -#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998 +#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 +#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff +#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; +} +#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 +#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 +#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 +static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; +} +#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 @@ -6929,6 +6834,12 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 +#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff +#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 +static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) +{ + return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; +} #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 @@ -7026,6 +6937,12 @@ static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 +#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 + +#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 + +static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } + #define REG_A6XX_CP_EVENT_START 0x0000d600 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 @@ -7135,11 +7052,11 @@ static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode v return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; } #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 -#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80 -#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7 -static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) +#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 +#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 +static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) { - return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; + return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; } #define REG_A6XX_TEX_SAMP_3 0x00000003 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 3d55e153fa9c..b349692219b7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -512,19 +512,26 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct platform_device *pdev = to_platform_device(gmu->dev); void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); - void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); + void __iomem *seqptr; uint32_t pdc_address_offset; + bool pdc_in_aop = false; - if (!pdcptr || !seqptr) + if (!pdcptr) goto err; - if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) + pdc_in_aop = true; + else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) pdc_address_offset = 0x30090; - else if (adreno_is_a650(adreno_gpu)) - pdc_address_offset = 0x300a0; else pdc_address_offset = 0x30080; + if (!pdc_in_aop) { + seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq"); + if (!seqptr) + goto err; + } + /* Disable SDE clock gating */ gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); @@ -542,7 +549,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); /* Load RSC sequencer uCode for sleep and wakeup */ - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); @@ -556,6 +563,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); } + if (pdc_in_aop) + goto setup_pdc; + /* Load PDC sequencer uCode for power up and power down sequence */ pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); @@ -587,7 +597,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); - if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu)) + if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); else pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); @@ -596,6 +606,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); /* Setup GPU PDC */ +setup_pdc: pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); @@ -687,7 +698,7 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) u32 itcm_base = 0x00000000; u32 dtcm_base = 0x00040000; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650_family(adreno_gpu)) dtcm_base = 0x10004000; if (gmu->legacy) { @@ -740,8 +751,10 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) int ret; u32 chipid; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650_family(adreno_gpu)) { + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1); gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); + } if (state == GMU_WARM_BOOT) { ret = a6xx_rpmh_start(gmu); @@ -1346,7 +1359,7 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) * The GMU handles its own frequency switching so build a list of * available frequencies to send during initialization */ - ret = dev_pm_opp_of_add_table(gmu->dev); + ret = devm_pm_opp_of_add_table(gmu->dev); if (ret) { DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n"); return ret; @@ -1483,12 +1496,28 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) if (ret) goto err_put_device; + + /* A660 now requires handling "prealloc requests" in GMU firmware + * For now just hardcode allocations based on the known firmware. + * note: there is no indication that these correspond to "dummy" or + * "debug" regions, but this "guess" allows reusing these BOs which + * are otherwise unused by a660. + */ + gmu->dummy.size = SZ_4K; + if (adreno_is_a660(adreno_gpu)) { + ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000); + if (ret) + goto err_memory; + + gmu->dummy.size = SZ_8K; + } + /* Allocate memory for the GMU dummy page */ - ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); + ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000); if (ret) goto err_memory; - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, SZ_16M - SZ_16K, 0x04000); if (ret) @@ -1530,7 +1559,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_memory; } - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); if (IS_ERR(gmu->rscc)) goto err_mmio; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 5a43d3090b0c..811589215834 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -292,6 +292,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 +#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1 + #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 @@ -439,6 +441,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42 +#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001 + #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004 #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index f6c1b62b901e..9c5e4618aa0a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -149,7 +149,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); - get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), rbmemptr_stats(ring, index, cpcycles_start)); /* @@ -185,7 +185,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) } } - get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, + get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), rbmemptr_stats(ring, index, cpcycles_end)); get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, rbmemptr_stats(ring, index, alwayson_end)); @@ -427,6 +427,59 @@ const struct adreno_reglist a650_hwcg[] = { {}, }; +const struct adreno_reglist a660_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -541,6 +594,51 @@ static const u32 a650_protect[] = { A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ }; +/* These are for a635 and a660 */ +static const u32 a660_protect[] = { + A6XX_PROTECT_RDONLY(0x00000, 0x04ff), + A6XX_PROTECT_RDONLY(0x00501, 0x0005), + A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), + A6XX_PROTECT_NORDWR(0x0050e, 0x0000), + A6XX_PROTECT_NORDWR(0x00510, 0x0000), + A6XX_PROTECT_NORDWR(0x00534, 0x0000), + A6XX_PROTECT_NORDWR(0x00800, 0x0082), + A6XX_PROTECT_NORDWR(0x008a0, 0x0008), + A6XX_PROTECT_NORDWR(0x008ab, 0x0024), + A6XX_PROTECT_RDONLY(0x008de, 0x00ae), + A6XX_PROTECT_NORDWR(0x00900, 0x004d), + A6XX_PROTECT_NORDWR(0x0098d, 0x0272), + A6XX_PROTECT_NORDWR(0x00e00, 0x0001), + A6XX_PROTECT_NORDWR(0x00e03, 0x000c), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), + A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), + A6XX_PROTECT_NORDWR(0x08630, 0x01cf), + A6XX_PROTECT_NORDWR(0x08e00, 0x0000), + A6XX_PROTECT_NORDWR(0x08e08, 0x0000), + A6XX_PROTECT_NORDWR(0x08e50, 0x001f), + A6XX_PROTECT_NORDWR(0x08e80, 0x027f), + A6XX_PROTECT_NORDWR(0x09624, 0x01db), + A6XX_PROTECT_NORDWR(0x09e60, 0x0011), + A6XX_PROTECT_NORDWR(0x09e78, 0x0187), + A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), + A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), + A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), + A6XX_PROTECT_NORDWR(0x0b604, 0x0000), + A6XX_PROTECT_NORDWR(0x0b608, 0x0006), + A6XX_PROTECT_NORDWR(0x0be02, 0x0001), + A6XX_PROTECT_NORDWR(0x0be20, 0x015f), + A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), + A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0443), + A6XX_PROTECT_RDONLY(0x1f844, 0x007b), + A6XX_PROTECT_NORDWR(0x1f860, 0x0000), + A6XX_PROTECT_NORDWR(0x1f887, 0x001b), + A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ +}; + static void a6xx_set_cp_protect(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -554,6 +652,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) regs = a650_protect; count = ARRAY_SIZE(a650_protect); count_max = 48; + } else if (adreno_is_a660(adreno_gpu)) { + regs = a660_protect; + count = ARRAY_SIZE(a660_protect); + count_max = 48; } /* @@ -584,7 +686,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a640(adreno_gpu)) amsbc = 1; - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ lower_bit = 3; amsbc = 1; @@ -648,6 +750,11 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, * Targets up to a640 (a618, a630 and a640) need to check for a * microcode version that is patched to support the whereami opcode or * one that is new enough to include it by default. + * + * a650 tier targets don't need whereami but still need to be + * equal to or newer than 0.95 for other security fixes + * + * a660 targets have all the critical security fixes from the start */ if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) || adreno_is_a640(adreno_gpu)) { @@ -671,27 +778,20 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, DRM_DEV_ERROR(&gpu->pdev->dev, "a630 SQE ucode is too old. Have version %x need at least %x\n", buf[0] & 0xfff, 0x190); - } else { - /* - * a650 tier targets don't need whereami but still need to be - * equal to or newer than 0.95 for other security fixes - */ - if (adreno_is_a650(adreno_gpu)) { - if ((buf[0] & 0xfff) >= 0x095) { - ret = true; - goto out; - } - - DRM_DEV_ERROR(&gpu->pdev->dev, - "a650 SQE ucode is too old. Have version %x need at least %x\n", - buf[0] & 0xfff, 0x095); + } else if (adreno_is_a650(adreno_gpu)) { + if ((buf[0] & 0xfff) >= 0x095) { + ret = true; + goto out; } - /* - * When a660 is added those targets should return true here - * since those have all the critical security fixes built in - * from the start - */ + DRM_DEV_ERROR(&gpu->pdev->dev, + "a650 SQE ucode is too old. Have version %x need at least %x\n", + buf[0] & 0xfff, 0x095); + } else if (adreno_is_a660(adreno_gpu)) { + ret = true; + } else { + DRM_DEV_ERROR(&gpu->pdev->dev, + "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); } out: msm_gem_put_vaddr(obj); @@ -727,8 +827,8 @@ static int a6xx_ucode_init(struct msm_gpu *gpu) } } - gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, - REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova); + gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, + REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova); return 0; } @@ -797,7 +897,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { + if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); @@ -822,7 +922,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); - if (!adreno_is_a650(adreno_gpu)) { + if (!adreno_is_a650_family(adreno_gpu)) { /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); @@ -835,22 +935,27 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); - if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) + if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); else gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + if (adreno_is_a660(adreno_gpu)) + gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); + /* Setting the mem pool size */ gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); - /* Setting the primFifo thresholds default values */ - if (adreno_is_a650(adreno_gpu)) - gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); + /* Setting the primFifo thresholds default values, + * and vccCacheSkipDis=1 bit (0x200) for A640 and newer + */ + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); else if (adreno_is_a640(adreno_gpu)) - gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else - gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); /* Set the AHB default slave response to "ERROR" */ gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); @@ -859,7 +964,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); /* Select CP0 to always count cycles */ - gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); + gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); a6xx_set_ubwc_config(gpu); @@ -870,7 +975,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); /* Set weights for bicubic filtering */ - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 0x3fe05ff4); @@ -885,6 +990,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu) /* Protect registers from the CP */ a6xx_set_cp_protect(gpu); + if (adreno_is_a660(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); + /* Set dualQ + disable afull for A660 GPU but not for A635 */ + gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); + } + /* Enable expanded apriv for targets that support it */ if (gpu->hw_apriv) { gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, @@ -925,7 +1037,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) if (!a6xx_gpu->shadow_bo) { a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev, sizeof(u32) * gpu->nr_rings, - MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, + MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->aspace, &a6xx_gpu->shadow_bo, &a6xx_gpu->shadow_iova); @@ -1032,18 +1144,113 @@ static void a6xx_recover(struct msm_gpu *gpu) msm_gpu_hw_init(gpu); } -static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) +static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) +{ + static const char *uche_clients[7] = { + "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", + }; + u32 val; + + if (mid < 1 || mid > 3) + return "UNKNOWN"; + + /* + * The source of the data depends on the mid ID read from FSYNR1. + * and the client ID read from the UCHE block + */ + val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); + + /* mid = 3 is most precise and refers to only one block per client */ + if (mid == 3) + return uche_clients[val & 7]; + + /* For mid=2 the source is TP or VFD except when the client id is 0 */ + if (mid == 2) + return ((val & 7) == 0) ? "TP" : "TP|VFD"; + + /* For mid=1 just return "UCHE" as a catchall for everything else */ + return "UCHE"; +} + +static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) +{ + if (id == 0) + return "CP"; + else if (id == 4) + return "CCU"; + else if (id == 6) + return "CDP Prefetch"; + + return a6xx_uche_fault_block(gpu, id); +} + +#define ARM_SMMU_FSR_TF BIT(1) +#define ARM_SMMU_FSR_PF BIT(3) +#define ARM_SMMU_FSR_EF BIT(4) + +static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) { struct msm_gpu *gpu = arg; + struct adreno_smmu_fault_info *info = data; + const char *type = "UNKNOWN"; + const char *block; + bool do_devcoredump = info && !READ_ONCE(gpu->crashstate); + + /* + * If we aren't going to be resuming later from fault_worker, then do + * it now. + */ + if (!do_devcoredump) { + gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); + } - pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", + /* + * Print a default message if we couldn't get the data from the + * adreno-smmu-priv + */ + if (!info) { + pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n", iova, flags, gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); - return -EFAULT; + return 0; + } + + if (info->fsr & ARM_SMMU_FSR_TF) + type = "TRANSLATION"; + else if (info->fsr & ARM_SMMU_FSR_PF) + type = "PERMISSION"; + else if (info->fsr & ARM_SMMU_FSR_EF) + type = "EXTERNAL"; + + block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); + + pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n", + info->ttbr0, iova, + flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ", + type, block, + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); + + if (do_devcoredump) { + /* Turn off the hangcheck timer to keep it from bothering us */ + del_timer(&gpu->hangcheck_timer); + + gpu->fault_info.ttbr0 = info->ttbr0; + gpu->fault_info.iova = iova; + gpu->fault_info.flags = flags; + gpu->fault_info.type = type; + gpu->fault_info.block = block; + + kthread_queue_work(gpu->worker, &gpu->fault_work); + } + + return 0; } static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) @@ -1095,6 +1302,15 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); /* + * If stalled on SMMU fault, we could trip the GPU's hang detection, + * but the fault handler will trigger the devcore dump, and we want + * to otherwise resume normally rather than killing the submit, so + * just bail. + */ + if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) + return; + + /* * Force the GPU to stay on until after we finish * collecting information */ @@ -1339,9 +1555,6 @@ static void a6xx_destroy(struct msm_gpu *gpu) adreno_gpu_cleanup(adreno_gpu); - if (a6xx_gpu->opp_table) - dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table); - kfree(a6xx_gpu); } @@ -1474,7 +1687,6 @@ static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, u32 revn) { - struct opp_table *opp_table; u32 supp_hw = UINT_MAX; u16 speedbin; int ret; @@ -1497,11 +1709,10 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, supp_hw = fuse_to_supp_hw(dev, revn, speedbin); done: - opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1); - if (IS_ERR(opp_table)) - return PTR_ERR(opp_table); + ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); + if (ret) + return ret; - a6xx_gpu->opp_table = opp_table; return 0; } @@ -1561,7 +1772,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) */ info = adreno_info(config->rev); - if (info && info->revn == 650) + if (info && (info->revn == 650 || info->revn == 660)) adreno_gpu->base.hw_apriv = true; a6xx_llc_slices_init(pdev, a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index bb544dfe5737..0bc2d062f54a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -33,8 +33,6 @@ struct a6xx_gpu { void *llc_slice; void *htw_llc_slice; bool have_mmu500; - - struct opp_table *opp_table; }; #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index c1699b4f9a89..ad4ea0ed5d99 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -113,7 +113,7 @@ static int a6xx_crashdumper_init(struct msm_gpu *gpu, struct a6xx_crashdumper *dumper) { dumper->ptr = msm_gem_kernel_new_locked(gpu->dev, - SZ_1M, MSM_BO_UNCACHED, gpu->aspace, + SZ_1M, MSM_BO_WC, gpu->aspace, &dumper->bo, &dumper->iova); if (!IS_ERR(dumper->ptr)) @@ -832,6 +832,20 @@ static void a6xx_get_registers(struct msm_gpu *gpu, a6xx_get_ahb_gpu_registers(gpu, a6xx_state, &a6xx_vbif_reglist, &a6xx_state->registers[index++]); + if (!dumper) { + /* + * We can't use the crashdumper when the SMMU is stalled, + * because the GPU has no memory access until we resume + * translation (but we don't want to do that until after + * we have captured as much useful GPU state as possible). + * So instead collect registers via the CPU: + */ + for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++) + a6xx_get_ahb_gpu_registers(gpu, + a6xx_state, &a6xx_reglist[i], + &a6xx_state->registers[index++]); + return; + } for (i = 0; i < ARRAY_SIZE(a6xx_reglist); i++) a6xx_get_crashdumper_registers(gpu, @@ -905,11 +919,13 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu, struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) { - struct a6xx_crashdumper dumper = { 0 }; + struct a6xx_crashdumper _dumper = { 0 }, *dumper = NULL; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gpu_state *a6xx_state = kzalloc(sizeof(*a6xx_state), GFP_KERNEL); + bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & + A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT); if (!a6xx_state) return ERR_PTR(-ENOMEM); @@ -928,14 +944,24 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) /* Get the banks of indexed registers */ a6xx_get_indexed_registers(gpu, a6xx_state); - /* Try to initialize the crashdumper */ - if (!a6xx_crashdumper_init(gpu, &dumper)) { - a6xx_get_registers(gpu, a6xx_state, &dumper); - a6xx_get_shaders(gpu, a6xx_state, &dumper); - a6xx_get_clusters(gpu, a6xx_state, &dumper); - a6xx_get_dbgahb_clusters(gpu, a6xx_state, &dumper); + /* + * Try to initialize the crashdumper, if we are not dumping state + * with the SMMU stalled. The crashdumper needs memory access to + * write out GPU state, so we need to skip this when the SMMU is + * stalled in response to an iova fault + */ + if (!stalled && !a6xx_crashdumper_init(gpu, &_dumper)) { + dumper = &_dumper; + } + + a6xx_get_registers(gpu, a6xx_state, dumper); + + if (dumper) { + a6xx_get_shaders(gpu, a6xx_state, dumper); + a6xx_get_clusters(gpu, a6xx_state, dumper); + a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper); - msm_gem_kernel_put(dumper.bo, gpu->aspace, true); + msm_gem_kernel_put(dumper->bo, gpu->aspace, true); } if (snapshot_debugbus) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index ccd44d0418f8..919433732b43 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -351,6 +351,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) msg->cnoc_cmds_data[1][0] = 0x60000001; } +static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) +{ + /* + * Send a single "off" entry just to get things running + * TODO: bus scaling + */ + msg->bw_level_num = 1; + + msg->ddr_cmds_num = 3; + msg->ddr_wait_bitmask = 0x01; + + msg->ddr_cmds_addrs[0] = 0x50004; + msg->ddr_cmds_addrs[1] = 0x500a0; + msg->ddr_cmds_addrs[2] = 0x50000; + + msg->ddr_cmds_data[0][0] = 0x40000000; + msg->ddr_cmds_data[0][1] = 0x40000000; + msg->ddr_cmds_data[0][2] = 0x40000000; + + /* + * These are the CX (CNOC) votes - these are used by the GMU but the + * votes are known and fixed for the target + */ + msg->cnoc_cmds_num = 1; + msg->cnoc_wait_bitmask = 0x01; + + msg->cnoc_cmds_addrs[0] = 0x50070; + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[1][0] = 0x60000001; +} + static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ @@ -401,6 +432,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) a640_build_bw_table(&msg); else if (adreno_is_a650(adreno_gpu)) a650_build_bw_table(&msg); + else if (adreno_is_a660(adreno_gpu)) + a660_build_bw_table(&msg); else a6xx_build_bw_table(&msg); diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h index 548f532417d1..c9389d9fb599 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 600d445fabe8..6dad8015c9a1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -287,6 +287,19 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, + }, { + .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .revn = 660, + .name = "A660", + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_1M + SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a660_zap.mdt", + .hwcg = a660_hwcg, }, }; @@ -466,6 +479,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; + priv->has_cached_coherent = config.rev.core >= 6; gpu = info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index cf897297656f..9f5a30234b33 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -239,7 +239,7 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) *value = adreno_gpu->gmem; return 0; case MSM_PARAM_GMEM_BASE: - *value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0; + *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: *value = adreno_gpu->rev.patchid | @@ -391,7 +391,7 @@ struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, void *ptr; ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, - MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); + MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); if (IS_ERR(ptr)) return ERR_CAST(ptr); @@ -408,7 +408,7 @@ int adreno_hw_init(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int ret, i; - DBG("%s", gpu->name); + VERB("%s", gpu->name); ret = adreno_load_fw(adreno_gpu); if (ret) @@ -684,6 +684,21 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, adreno_gpu->info->revn, adreno_gpu->rev.core, adreno_gpu->rev.major, adreno_gpu->rev.minor, adreno_gpu->rev.patchid); + /* + * If this is state collected due to iova fault, so fault related info + * + * TTBR0 would not be zero, so this is a good way to distinguish + */ + if (state->fault_info.ttbr0) { + const struct msm_gpu_fault_info *info = &state->fault_info; + + drm_puts(p, "fault-info:\n"); + drm_printf(p, " - ttbr0=%.16llx\n", info->ttbr0); + drm_printf(p, " - iova=%.16lx\n", info->iova); + drm_printf(p, " - dir=%s\n", info->flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ"); + drm_printf(p, " - type=%s\n", info->type); + drm_printf(p, " - source=%s\n", info->block); + } drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); @@ -841,7 +856,7 @@ static void adreno_get_pwrlevels(struct device *dev, if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) ret = adreno_get_legacy_pwrlevels(dev); else { - ret = dev_pm_opp_of_add_table(dev); + ret = devm_pm_opp_of_add_table(dev); if (ret) DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); } @@ -946,7 +961,4 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) pm_runtime_disable(&priv->gpu_pdev->dev); msm_gpu_cleanup(&adreno_gpu->base); - - icc_put(gpu->icc_path); - icc_put(gpu->ocmem_icc_path); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index ccac275aa7a2..8dbe0d157520 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,7 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; struct adreno_info { struct adreno_rev rev; @@ -247,6 +247,17 @@ static inline int adreno_is_a650(struct adreno_gpu *gpu) return gpu->revn == 650; } +static inline int adreno_is_a660(struct adreno_gpu *gpu) +{ + return gpu->revn == 660; +} + +/* check for a650, a660, or any derivatives */ +static inline int adreno_is_a650_family(struct adreno_gpu *gpu) +{ + return gpu->revn == 650 || gpu->revn == 620 || gpu->revn == 660; +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname); diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index 59bb8c1ffce6..e832ae4b937a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h @@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -247,9 +247,9 @@ enum adreno_pm4_type3_packets { CP_DRAW_INDX_INDIRECT = 41, CP_DRAW_INDIRECT_MULTI = 42, CP_DRAW_AUTO = 36, - CP_UNKNOWN_19 = 25, - CP_UNKNOWN_1A = 26, - CP_UNKNOWN_4E = 78, + CP_DRAW_PRED_ENABLE_GLOBAL = 25, + CP_DRAW_PRED_ENABLE_LOCAL = 26, + CP_DRAW_PRED_SET = 78, CP_WIDE_REG_WRITE = 116, CP_SCRATCH_TO_REG = 77, CP_REG_TO_SCRATCH = 74, @@ -267,6 +267,7 @@ enum adreno_pm4_type3_packets { CP_SKIP_IB2_ENABLE_GLOBAL = 29, CP_SKIP_IB2_ENABLE_LOCAL = 35, CP_SET_SUBDRAW_SIZE = 53, + CP_WHERE_AM_I = 98, CP_SET_VISIBILITY_OVERRIDE = 100, CP_PREEMPT_ENABLE_GLOBAL = 105, CP_PREEMPT_ENABLE_LOCAL = 106, @@ -298,7 +299,6 @@ enum adreno_pm4_type3_packets { CP_SET_BIN_DATA5_OFFSET = 46, CP_SET_CTXSWITCH_IB = 85, CP_REG_WRITE = 109, - CP_WHERE_AM_I = 98, }; enum adreno_state_block { @@ -400,6 +400,17 @@ enum a6xx_patch_type { enum a6xx_draw_indirect_opcode { INDIRECT_OP_NORMAL = 2, INDIRECT_OP_INDEXED = 4, + INDIRECT_OP_INDIRECT_COUNT = 6, + INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7, +}; + +enum cp_draw_pred_src { + PRED_SRC_MEM = 5, +}; + +enum cp_draw_pred_test { + NE_0_PASS = 0, + EQ_0_PASS = 1, }; enum cp_cond_function { @@ -1040,33 +1051,61 @@ static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK; } -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_2 0x00000002 -#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK 0xffffffff -#define A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT 0 -static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT(uint32_t val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_2_DRAW_COUNT__MASK; -} +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_ADDRESS_0 0x00000003 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_5 0x00000005 -#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK 0xffffffff -#define A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT 0 -static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0(uint32_t val) -{ - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_5_PARAM_0__MASK; -} +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 + +#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 + + +#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003 + +#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005 + +#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 +#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_8 0x00000008 -#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK 0xffffffff -#define A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT 0 -static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE(uint32_t val) + +#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003 + +#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005 + +#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007 + + +#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003 + +#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005 + +#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006 + +#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008 + +#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a + +#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000 +#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001 + +#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000 +#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001 + +#define REG_CP_DRAW_PRED_SET_0 0x00000000 +#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0 +#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4 +static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val) { - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_8_STRIDE__MASK; + return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK; } +#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100 +#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8 +static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) +{ + return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK; +} + +#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c index cdec3fbe6ff4..d2457490930b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c @@ -22,165 +22,20 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx) struct dpu_kms *dpu_kms = arg; struct dpu_irq *irq_obj = &dpu_kms->irq_obj; struct dpu_irq_callback *cb; - unsigned long irq_flags; - pr_debug("irq_idx=%d\n", irq_idx); + VERB("irq_idx=%d\n", irq_idx); - if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) { - DRM_ERROR("no registered cb, idx:%d enable_count:%d\n", irq_idx, - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])); - } + if (list_empty(&irq_obj->irq_cb_tbl[irq_idx])) + DRM_ERROR("no registered cb, idx:%d\n", irq_idx); atomic_inc(&irq_obj->irq_counts[irq_idx]); /* * Perform registered function callback */ - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list) if (cb->func) cb->func(cb->arg, irq_idx); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); - - /* - * Clear pending interrupt status in HW. - * NOTE: dpu_core_irq_callback_handler is protected by top-level - * spinlock, so it is safe to clear any interrupt status here. - */ - dpu_kms->hw_intr->ops.clear_intr_status_nolock( - dpu_kms->hw_intr, - irq_idx); -} - -int dpu_core_irq_idx_lookup(struct dpu_kms *dpu_kms, - enum dpu_intr_type intr_type, u32 instance_idx) -{ - if (!dpu_kms->hw_intr || !dpu_kms->hw_intr->ops.irq_idx_lookup) - return -EINVAL; - - return dpu_kms->hw_intr->ops.irq_idx_lookup(dpu_kms->hw_intr, - intr_type, instance_idx); -} - -/** - * _dpu_core_irq_enable - enable core interrupt given by the index - * @dpu_kms: Pointer to dpu kms context - * @irq_idx: interrupt index - */ -static int _dpu_core_irq_enable(struct dpu_kms *dpu_kms, int irq_idx) -{ - unsigned long irq_flags; - int ret = 0, enable_count; - - if (!dpu_kms->hw_intr || - !dpu_kms->irq_obj.enable_counts || - !dpu_kms->irq_obj.irq_counts) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { - DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); - return -EINVAL; - } - - enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); - DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); - trace_dpu_core_irq_enable_idx(irq_idx, enable_count); - - if (atomic_inc_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 1) { - ret = dpu_kms->hw_intr->ops.enable_irq( - dpu_kms->hw_intr, - irq_idx); - if (ret) - DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n", - irq_idx); - - DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret); - - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); - /* empty callback list but interrupt is enabled */ - if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) - DPU_ERROR("irq_idx=%d enabled with no callback\n", - irq_idx); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); - } - - return ret; -} - -int dpu_core_irq_enable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) -{ - int i, ret = 0, counts; - - if (!irq_idxs || !irq_count) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]); - if (counts) - DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); - - for (i = 0; (i < irq_count) && !ret; i++) - ret = _dpu_core_irq_enable(dpu_kms, irq_idxs[i]); - - return ret; -} - -/** - * _dpu_core_irq_disable - disable core interrupt given by the index - * @dpu_kms: Pointer to dpu kms context - * @irq_idx: interrupt index - */ -static int _dpu_core_irq_disable(struct dpu_kms *dpu_kms, int irq_idx) -{ - int ret = 0, enable_count; - - if (!dpu_kms->hw_intr || !dpu_kms->irq_obj.enable_counts) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { - DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); - return -EINVAL; - } - - enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); - DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); - trace_dpu_core_irq_disable_idx(irq_idx, enable_count); - - if (atomic_dec_return(&dpu_kms->irq_obj.enable_counts[irq_idx]) == 0) { - ret = dpu_kms->hw_intr->ops.disable_irq( - dpu_kms->hw_intr, - irq_idx); - if (ret) - DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n", - irq_idx); - DPU_DEBUG("irq_idx=%d ret=%d\n", irq_idx, ret); - } - - return ret; -} - -int dpu_core_irq_disable(struct dpu_kms *dpu_kms, int *irq_idxs, u32 irq_count) -{ - int i, ret = 0, counts; - - if (!irq_idxs || !irq_count) { - DPU_ERROR("invalid params\n"); - return -EINVAL; - } - - counts = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idxs[0]]); - if (counts == 2) - DRM_ERROR("irq_idx=%d enable_count=%d\n", irq_idxs[0], counts); - - for (i = 0; (i < irq_count) && !ret; i++) - ret = _dpu_core_irq_disable(dpu_kms, irq_idxs[i]); - - return ret; } u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear) @@ -217,19 +72,28 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx, return -EINVAL; } - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) { DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); + VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); + irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr); trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb); list_del_init(®ister_irq_cb->list); list_add_tail(®ister_irq_cb->list, &dpu_kms->irq_obj.irq_cb_tbl[irq_idx]); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); + if (list_is_first(®ister_irq_cb->list, + &dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) { + int ret = dpu_kms->hw_intr->ops.enable_irq_locked( + dpu_kms->hw_intr, + irq_idx); + if (ret) + DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n", + irq_idx); + } + dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags); return 0; } @@ -252,21 +116,27 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx, return -EINVAL; } - if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->irq_idx_tbl_size) { + if (irq_idx < 0 || irq_idx >= dpu_kms->hw_intr->total_irqs) { DPU_ERROR("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - DPU_DEBUG("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); + VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx); - spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags); + irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr); trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb); list_del_init(®ister_irq_cb->list); /* empty callback list but interrupt is still enabled */ - if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]) && - atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx])) - DPU_ERROR("irq_idx=%d enabled with no callback\n", irq_idx); - spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags); + if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) { + int ret = dpu_kms->hw_intr->ops.disable_irq_locked( + dpu_kms->hw_intr, + irq_idx); + if (ret) + DPU_ERROR("Fail to disable IRQ for irq_idx:%d\n", + irq_idx); + VERB("irq_idx=%d ret=%d\n", irq_idx, ret); + } + dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags); return 0; } @@ -290,26 +160,26 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) #ifdef CONFIG_DEBUG_FS static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v) { - struct dpu_irq *irq_obj = s->private; + struct dpu_kms *dpu_kms = s->private; + struct dpu_irq *irq_obj = &dpu_kms->irq_obj; struct dpu_irq_callback *cb; unsigned long irq_flags; - int i, irq_count, enable_count, cb_count; + int i, irq_count, cb_count; - if (WARN_ON(!irq_obj->enable_counts || !irq_obj->irq_cb_tbl)) + if (WARN_ON(!irq_obj->irq_cb_tbl)) return 0; for (i = 0; i < irq_obj->total_irqs; i++) { - spin_lock_irqsave(&irq_obj->cb_lock, irq_flags); + irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr); cb_count = 0; irq_count = atomic_read(&irq_obj->irq_counts[i]); - enable_count = atomic_read(&irq_obj->enable_counts[i]); list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list) cb_count++; - spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags); + dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags); - if (irq_count || enable_count || cb_count) - seq_printf(s, "idx:%d irq:%d enable:%d cb:%d\n", - i, irq_count, enable_count, cb_count); + if (irq_count || cb_count) + seq_printf(s, "idx:%d irq:%d cb:%d\n", + i, irq_count, cb_count); } return 0; @@ -320,7 +190,7 @@ DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq); void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms, struct dentry *parent) { - debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj, + debugfs_create_file("core_irq", 0600, parent, dpu_kms, &dpu_debugfs_core_irq_fops); } #endif @@ -334,19 +204,14 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms) dpu_disable_all_irqs(dpu_kms); pm_runtime_put_sync(&dpu_kms->pdev->dev); - spin_lock_init(&dpu_kms->irq_obj.cb_lock); - /* Create irq callbacks for all possible irq_idx */ - dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->irq_idx_tbl_size; + dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs; dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs, sizeof(struct list_head), GFP_KERNEL); - dpu_kms->irq_obj.enable_counts = kcalloc(dpu_kms->irq_obj.total_irqs, - sizeof(atomic_t), GFP_KERNEL); dpu_kms->irq_obj.irq_counts = kcalloc(dpu_kms->irq_obj.total_irqs, sizeof(atomic_t), GFP_KERNEL); for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) { INIT_LIST_HEAD(&dpu_kms->irq_obj.irq_cb_tbl[i]); - atomic_set(&dpu_kms->irq_obj.enable_counts[i], 0); atomic_set(&dpu_kms->irq_obj.irq_counts[i], 0); } } @@ -357,8 +222,7 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) pm_runtime_get_sync(&dpu_kms->pdev->dev); for (i = 0; i < dpu_kms->irq_obj.total_irqs; i++) - if (atomic_read(&dpu_kms->irq_obj.enable_counts[i]) || - !list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i])) + if (!list_empty(&dpu_kms->irq_obj.irq_cb_tbl[i])) DPU_ERROR("irq_idx=%d still enabled/registered\n", i); dpu_clear_all_irqs(dpu_kms); @@ -366,10 +230,8 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) pm_runtime_put_sync(&dpu_kms->pdev->dev); kfree(dpu_kms->irq_obj.irq_cb_tbl); - kfree(dpu_kms->irq_obj.enable_counts); kfree(dpu_kms->irq_obj.irq_counts); dpu_kms->irq_obj.irq_cb_tbl = NULL; - dpu_kms->irq_obj.enable_counts = NULL; dpu_kms->irq_obj.irq_counts = NULL; dpu_kms->irq_obj.total_irqs = 0; } @@ -377,21 +239,13 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms) irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) { /* - * Read interrupt status from all sources. Interrupt status are - * stored within hw_intr. - * Function will also clear the interrupt status after reading. - * Individual interrupt status bit will only get stored if it - * is enabled. - */ - dpu_kms->hw_intr->ops.get_interrupt_statuses(dpu_kms->hw_intr); - - /* * Dispatch to HW driver to handle interrupt lookup that is being * fired. When matching interrupt is located, HW driver will call to * dpu_core_irq_callback_handler with the irq_idx from the lookup table. * dpu_core_irq_callback_handler will perform the registered function * callback, and do the interrupt status clearing once the registered * callback is finished. + * Function will also clear the interrupt status after reading. */ dpu_kms->hw_intr->ops.dispatch_irqs( dpu_kms->hw_intr, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h index e30775e6585b..90ae6c9ccc95 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h @@ -30,49 +30,6 @@ void dpu_core_irq_uninstall(struct dpu_kms *dpu_kms); irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms); /** - * dpu_core_irq_idx_lookup - IRQ helper function for lookup irq_idx from HW - * interrupt mapping table. - * @dpu_kms: DPU handle - * @intr_type: DPU HW interrupt type for lookup - * @instance_idx: DPU HW block instance defined in dpu_hw_mdss.h - * @return: irq_idx or -EINVAL when fail to lookup - */ -int dpu_core_irq_idx_lookup( - struct dpu_kms *dpu_kms, - enum dpu_intr_type intr_type, - uint32_t instance_idx); - -/** - * dpu_core_irq_enable - IRQ helper function for enabling one or more IRQs - * @dpu_kms: DPU handle - * @irq_idxs: Array of irq index - * @irq_count: Number of irq_idx provided in the array - * @return: 0 for success enabling IRQ, otherwise failure - * - * This function increments count on each enable and decrements on each - * disable. Interrupts is enabled if count is 0 before increment. - */ -int dpu_core_irq_enable( - struct dpu_kms *dpu_kms, - int *irq_idxs, - uint32_t irq_count); - -/** - * dpu_core_irq_disable - IRQ helper function for disabling one of more IRQs - * @dpu_kms: DPU handle - * @irq_idxs: Array of irq index - * @irq_count: Number of irq_idx provided in the array - * @return: 0 for success disabling IRQ, otherwise failure - * - * This function increments count on each enable and decrements on each - * disable. Interrupts is disabled if count is 0 after decrement. - */ -int dpu_core_irq_disable( - struct dpu_kms *dpu_kms, - int *irq_idxs, - uint32_t irq_count); - -/** * dpu_core_irq_read - IRQ helper function for reading IRQ status * @dpu_kms: DPU handle * @irq_idx: irq index diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 7cba5bbdf4b7..60fe06018581 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -132,7 +132,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state); } - DPU_DEBUG( + DRM_DEBUG_ATOMIC( "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n", crtc->base.id, perf->core_clk_rate, perf->max_per_pipe_ib, perf->bw_ctl); @@ -178,7 +178,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, struct dpu_crtc_state *tmp_cstate = to_dpu_crtc_state(tmp_crtc->state); - DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n", + DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n", tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, tmp_cstate->bw_control); @@ -187,11 +187,11 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, /* convert bandwidth to kb */ bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000); - DPU_DEBUG("calculated bandwidth=%uk\n", bw); + DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw); threshold = kms->catalog->perf.max_bw_high; - DPU_DEBUG("final threshold bw limit = %d\n", threshold); + DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold); if (!threshold) { DPU_ERROR("no bandwidth limits specified\n"); @@ -228,7 +228,7 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, perf.bw_ctl += dpu_cstate->new_perf.bw_ctl; - DPU_DEBUG("crtc=%d bw=%llu paths:%d\n", + DRM_DEBUG_ATOMIC("crtc=%d bw=%llu paths:%d\n", tmp_crtc->base.id, dpu_cstate->new_perf.bw_ctl, kms->num_paths); } @@ -278,7 +278,7 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) /* Release the bandwidth */ if (kms->perf.enable_bw_release) { trace_dpu_cmd_release_bw(crtc->base.id); - DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("Release BW crtc=%d\n", crtc->base.id); dpu_crtc->cur_perf.bw_ctl = 0; _dpu_core_perf_crtc_update_bus(kms, crtc); } @@ -314,7 +314,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) clk_rate = kms->perf.fix_core_clk_rate; - DPU_DEBUG("clk:%llu\n", clk_rate); + DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); return clk_rate; } @@ -344,7 +344,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, dpu_crtc = to_dpu_crtc(crtc); dpu_cstate = to_dpu_crtc_state(crtc->state); - DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n", + DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n", crtc->base.id, stop_req, kms->perf.core_clk_rate); old = &dpu_crtc->cur_perf; @@ -362,7 +362,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, (new->max_per_pipe_ib > old->max_per_pipe_ib))) || (!params_changed && ((new->bw_ctl < old->bw_ctl) || (new->max_per_pipe_ib < old->max_per_pipe_ib)))) { - DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", + DRM_DEBUG_ATOMIC("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", crtc->base.id, params_changed, new->bw_ctl, old->bw_ctl); old->bw_ctl = new->bw_ctl; @@ -378,7 +378,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, update_clk = true; } } else { - DPU_DEBUG("crtc=%d disable\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc=%d disable\n", crtc->base.id); memset(old, 0, sizeof(*old)); update_bus = true; update_clk = true; @@ -413,7 +413,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, } kms->perf.core_clk_rate = clk_rate; - DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate); + DRM_DEBUG_ATOMIC("update clk rate = %lld HZ\n", clk_rate); } return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 18bc76b7f1a3..9a5c70c87cc8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -57,8 +57,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc) { struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - DPU_DEBUG("\n"); - if (!crtc) return; @@ -163,7 +161,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, lm->ops.setup_blend_config(lm, pstate->stage, 0xFF, 0, blend_op); - DPU_DEBUG("format:%p4cc, alpha_en:%u blend_op:0x%x\n", + DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n", &format->base.pixel_format, format->alpha_enable, blend_op); } @@ -220,7 +218,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); set_bit(dpu_plane_pipe(plane), fetch_active); - DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", + + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", crtc->base.id, pstate->stage, plane->base.id, @@ -278,7 +277,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_hw_mixer *lm; int i; - DPU_DEBUG("%s\n", dpu_crtc->name); + DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); for (i = 0; i < cstate->num_mixers; i++) { mixer[i].mixer_op_mode = 0; @@ -305,7 +304,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); - DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", + DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", mixer[i].hw_lm->idx - LM_0, mixer[i].mixer_op_mode, ctl->idx - CTL_0, @@ -388,7 +387,7 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) DPU_ATRACE_BEGIN("crtc_frame_event"); - DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, + DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, ktime_to_ns(fevent->ts)); if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE @@ -407,9 +406,6 @@ static void dpu_crtc_frame_event_work(struct kthread_work *work) fevent->event); } - if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) - dpu_core_perf_crtc_update(crtc, 0, false); - if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE | DPU_ENCODER_FRAME_EVENT_ERROR)) frame_done = true; @@ -477,6 +473,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event) void dpu_crtc_complete_commit(struct drm_crtc *crtc) { trace_dpu_crtc_complete_commit(DRMID(crtc)); + dpu_core_perf_crtc_update(crtc, 0, false); _dpu_crtc_complete_flip(crtc); } @@ -558,7 +555,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); - DPU_DEBUG("lm %d, ctl %d, flush mask 0x%x\n", + DRM_DEBUG_ATOMIC("lm %d, ctl %d, flush mask 0x%x\n", mixer[i].hw_lm->idx - DSPP_0, ctl->idx - CTL_0, mixer[i].flush_mask); @@ -572,12 +569,12 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_encoder *encoder; if (!crtc->state->enable) { - DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", + DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n", crtc->base.id, crtc->state->enable); return; } - DPU_DEBUG("crtc%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); _dpu_crtc_setup_lm_bounds(crtc, crtc->state); @@ -617,12 +614,12 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, struct dpu_crtc_state *cstate; if (!crtc->state->enable) { - DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", + DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n", crtc->base.id, crtc->state->enable); return; } - DPU_DEBUG("crtc%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); dpu_crtc = to_dpu_crtc(crtc); cstate = to_dpu_crtc_state(crtc->state); @@ -675,7 +672,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc, { struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); - DPU_DEBUG("crtc%d\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); __drm_atomic_helper_crtc_destroy_state(state); @@ -688,7 +685,7 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) int ret, rc = 0; if (!atomic_read(&dpu_crtc->frame_pending)) { - DPU_DEBUG("no frames pending\n"); + DRM_DEBUG_ATOMIC("no frames pending\n"); return 0; } @@ -731,9 +728,9 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { /* acquire bandwidth and other resources */ - DPU_DEBUG("crtc%d first commit\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id); } else - DPU_DEBUG("crtc%d commit\n", crtc->base.id); + DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id); dpu_crtc->play_count++; @@ -908,7 +905,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); if (!crtc_state->enable || !crtc_state->active) { - DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", + DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, crtc_state->active); memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); @@ -916,7 +913,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } mode = &crtc_state->adjusted_mode; - DPU_DEBUG("%s: check\n", dpu_crtc->name); + DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name); /* force a full mode set if active state changed */ if (crtc_state->active_changed) @@ -1024,7 +1021,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; - DPU_DEBUG("%s: zpos %d\n", dpu_crtc->name, z_pos); + DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); } for (i = 0; i < multirect_count; i++) { @@ -1376,6 +1373,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, /* initialize event handling */ spin_lock_init(&dpu_crtc->event_lock); - DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); + DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name); return crtc; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 8d942052db8a..1c04b7cce43e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <robdclark@gmail.com> */ @@ -26,14 +26,15 @@ #include "dpu_crtc.h" #include "dpu_trace.h" #include "dpu_core_irq.h" +#include "disp/msm_disp_snapshot.h" -#define DPU_DEBUG_ENC(e, fmt, ...) DPU_DEBUG("enc%d " fmt,\ +#define DPU_DEBUG_ENC(e, fmt, ...) DRM_DEBUG_ATOMIC("enc%d " fmt,\ (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) #define DPU_ERROR_ENC(e, fmt, ...) DPU_ERROR("enc%d " fmt,\ (e) ? (e)->base.base.id : -1, ##__VA_ARGS__) -#define DPU_DEBUG_PHYS(p, fmt, ...) DPU_DEBUG("enc%d intf%d pp%d " fmt,\ +#define DPU_DEBUG_PHYS(p, fmt, ...) DRM_DEBUG_ATOMIC("enc%d intf%d pp%d " fmt,\ (p) ? (p)->parent->base.id : -1, \ (p) ? (p)->intf_idx - INTF_0 : -1, \ (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \ @@ -253,7 +254,7 @@ void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, } static int dpu_encoder_helper_wait_event_timeout(int32_t drm_id, - int32_t hw_id, struct dpu_encoder_wait_info *info); + u32 irq_idx, struct dpu_encoder_wait_info *info); int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, enum dpu_intr_idx intr_idx, @@ -273,27 +274,27 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, /* return EWOULDBLOCK since we know the wait isn't necessary */ if (phys_enc->enable_state == DPU_ENC_DISABLED) { - DRM_ERROR("encoder is disabled id=%u, intr=%d, hw=%d, irq=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_ERROR("encoder is disabled id=%u, intr=%d, irq=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx); return -EWOULDBLOCK; } if (irq->irq_idx < 0) { - DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, hw=%d, irq=%s", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_DEBUG_KMS("skip irq wait id=%u, intr=%d, irq=%s", + DRMID(phys_enc->parent), intr_idx, irq->name); return 0; } - DRM_DEBUG_KMS("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, pending_cnt=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_DEBUG_KMS("id=%u, intr=%d, irq=%d, pp=%d, pending_cnt=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); ret = dpu_encoder_helper_wait_event_timeout( DRMID(phys_enc->parent), - irq->hw_idx, + irq->irq_idx, wait_info); if (ret <= 0) { @@ -303,9 +304,9 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, unsigned long flags; DRM_DEBUG_KMS("irq not triggered id=%u, intr=%d, " - "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", + "irq=%d, pp=%d, atomic_cnt=%d", DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx, + irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); local_irq_save(flags); @@ -315,16 +316,16 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, } else { ret = -ETIMEDOUT; DRM_DEBUG_KMS("irq timeout id=%u, intr=%d, " - "hw=%d, irq=%d, pp=%d, atomic_cnt=%d", + "irq=%d, pp=%d, atomic_cnt=%d", DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx, + irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); } } else { ret = 0; trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), - intr_idx, irq->hw_idx, irq->irq_idx, + intr_idx, irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(wait_info->atomic_cnt)); } @@ -344,19 +345,9 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, } irq = &phys_enc->irq[intr_idx]; - if (irq->irq_idx >= 0) { - DPU_DEBUG_PHYS(phys_enc, - "skipping already registered irq %s type %d\n", - irq->name, irq->intr_type); - return 0; - } - - irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, - irq->intr_type, irq->hw_idx); if (irq->irq_idx < 0) { DPU_ERROR_PHYS(phys_enc, - "failed to lookup IRQ index for %s type:%d\n", - irq->name, irq->intr_type); + "invalid IRQ index:%d\n", irq->irq_idx); return -EINVAL; } @@ -370,19 +361,8 @@ int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, return ret; } - ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); - if (ret) { - DRM_ERROR("enable failed id=%u, intr=%d, hw=%d, irq=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, - irq->irq_idx); - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - irq->irq_idx, &irq->cb); - irq->irq_idx = -EINVAL; - return ret; - } - trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx); + irq->irq_idx); return ret; } @@ -397,31 +377,22 @@ int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, /* silently skip irqs that weren't registered */ if (irq->irq_idx < 0) { - DRM_ERROR("duplicate unregister id=%u, intr=%d, hw=%d, irq=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_ERROR("duplicate unregister id=%u, intr=%d, irq=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx); return 0; } - ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); - if (ret) { - DRM_ERROR("disable failed id=%u, intr=%d, hw=%d, irq=%d ret=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, - irq->irq_idx, ret); - } - ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, &irq->cb); if (ret) { - DRM_ERROR("unreg cb fail id=%u, intr=%d, hw=%d, irq=%d ret=%d", - DRMID(phys_enc->parent), intr_idx, irq->hw_idx, + DRM_ERROR("unreg cb fail id=%u, intr=%d, irq=%d ret=%d", + DRMID(phys_enc->parent), intr_idx, irq->irq_idx, ret); } trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, - irq->hw_idx, irq->irq_idx); - - irq->irq_idx = -EINVAL; + irq->irq_idx); return 0; } @@ -820,13 +791,13 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, /* return if the resource control is already in ON state */ if (dpu_enc->rc_state == DPU_ENC_RC_STATE_ON) { - DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in ON state\n", + DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in ON state\n", DRMID(drm_enc), sw_event); mutex_unlock(&dpu_enc->rc_lock); return 0; } else if (dpu_enc->rc_state != DPU_ENC_RC_STATE_OFF && dpu_enc->rc_state != DPU_ENC_RC_STATE_IDLE) { - DRM_DEBUG_KMS("id;%u, sw_event:%d, rc in state %d\n", + DRM_DEBUG_ATOMIC("id;%u, sw_event:%d, rc in state %d\n", DRMID(drm_enc), sw_event, dpu_enc->rc_state); mutex_unlock(&dpu_enc->rc_lock); @@ -1336,6 +1307,11 @@ static void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, DPU_ATRACE_BEGIN("encoder_underrun_callback"); atomic_inc(&phy_enc->underrun_cnt); + + /* trigger dump only on the first underrun */ + if (atomic_read(&phy_enc->underrun_cnt) == 1) + msm_disp_snapshot_state(drm_enc->dev); + trace_dpu_enc_underrun_cb(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt)); DPU_ATRACE_END("encoder_underrun_callback"); @@ -1453,11 +1429,6 @@ static void dpu_encoder_off_work(struct work_struct *work) struct dpu_encoder_virt *dpu_enc = container_of(work, struct dpu_encoder_virt, delayed_off_work.work); - if (!dpu_enc) { - DPU_ERROR("invalid dpu encoder\n"); - return; - } - dpu_encoder_resource_control(&dpu_enc->base, DPU_ENC_RC_EVENT_ENTER_IDLE); @@ -1537,7 +1508,7 @@ void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) static int dpu_encoder_helper_wait_event_timeout( int32_t drm_id, - int32_t hw_id, + u32 irq_idx, struct dpu_encoder_wait_info *info) { int rc = 0; @@ -1550,7 +1521,7 @@ static int dpu_encoder_helper_wait_event_timeout( atomic_read(info->atomic_cnt) == 0, jiffies); time = ktime_to_ms(ktime_get()); - trace_dpu_enc_wait_event_timeout(drm_id, hw_id, rc, time, + trace_dpu_enc_wait_event_timeout(drm_id, irq_idx, rc, time, expected_time, atomic_read(info->atomic_cnt)); /* If we timed out, counter is valid and time is less, wait again */ @@ -1565,19 +1536,23 @@ static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) struct dpu_encoder_virt *dpu_enc; struct dpu_hw_ctl *ctl; int rc; + struct drm_encoder *drm_enc; dpu_enc = to_dpu_encoder_virt(phys_enc->parent); ctl = phys_enc->hw_ctl; + drm_enc = phys_enc->parent; if (!ctl->ops.reset) return; - DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), + DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc), ctl->idx); rc = ctl->ops.reset(ctl); - if (rc) + if (rc) { DPU_ERROR_ENC(dpu_enc, "ctl %d reset failure\n", ctl->idx); + msm_disp_snapshot_state(drm_enc->dev); + } phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -1797,11 +1772,6 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) struct dpu_encoder_virt, vsync_event_work); ktime_t wakeup_time; - if (!dpu_enc) { - DPU_ERROR("invalid dpu encoder\n"); - return; - } - if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) return; @@ -2068,8 +2038,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, phys_params.parent_ops = &dpu_encoder_parent_ops; phys_params.enc_spinlock = &dpu_enc->enc_spinlock; - DPU_DEBUG("\n"); - switch (disp_info->intf_type) { case DRM_MODE_ENCODER_DSI: intf_type = INTF_DSI; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index ecbc4be98980..e7270eb6b84b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -165,18 +165,14 @@ enum dpu_intr_idx { /** * dpu_encoder_irq - tracking structure for interrupts * @name: string name of interrupt - * @intr_type: Encoder interrupt type * @intr_idx: Encoder interrupt enumeration - * @hw_idx: HW Block ID * @irq_idx: IRQ interface lookup index from DPU IRQ framework * will be -EINVAL if IRQ is not registered * @irq_cb: interrupt callback */ struct dpu_encoder_irq { const char *name; - enum dpu_intr_type intr_type; enum dpu_intr_idx intr_idx; - int hw_idx; int irq_idx; struct dpu_irq_callback cb; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b2be39b9144e..aa01698d6b25 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ @@ -11,6 +11,7 @@ #include "dpu_core_irq.h" #include "dpu_formats.h" #include "dpu_trace.h" +#include "disp/msm_disp_snapshot.h" #define DPU_DEBUG_CMDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ (e) && (e)->base.parent ? \ @@ -143,28 +144,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg, int irq_idx) phys_enc); } -static void _dpu_encoder_phys_cmd_setup_irq_hw_idx( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_irq *irq; - - irq = &phys_enc->irq[INTR_IDX_CTL_START]; - irq->hw_idx = phys_enc->hw_ctl->idx; - irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_PINGPONG]; - irq->hw_idx = phys_enc->hw_pp->idx; - irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_RDPTR]; - irq->hw_idx = phys_enc->hw_pp->idx; - irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; - irq->hw_idx = phys_enc->intf_idx; - irq->irq_idx = -EINVAL; -} - static void dpu_encoder_phys_cmd_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_display_mode *mode, @@ -172,6 +151,7 @@ static void dpu_encoder_phys_cmd_mode_set( { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); + struct dpu_encoder_irq *irq; if (!mode || !adj_mode) { DPU_ERROR("invalid args\n"); @@ -181,7 +161,17 @@ static void dpu_encoder_phys_cmd_mode_set( DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n"); drm_mode_debug_printmodeline(adj_mode); - _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc); + irq = &phys_enc->irq[INTR_IDX_CTL_START]; + irq->irq_idx = phys_enc->hw_ctl->caps->intr_start; + + irq = &phys_enc->irq[INTR_IDX_PINGPONG]; + irq->irq_idx = phys_enc->hw_pp->caps->intr_done; + + irq = &phys_enc->irq[INTR_IDX_RDPTR]; + irq->irq_idx = phys_enc->hw_pp->caps->intr_rdptr; + + irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; + irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun; } static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( @@ -191,10 +181,13 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( to_dpu_encoder_phys_cmd(phys_enc); u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR; bool do_log = false; + struct drm_encoder *drm_enc; if (!phys_enc->hw_pp) return -EINVAL; + drm_enc = phys_enc->parent; + cmd_enc->pp_timeout_report_cnt++; if (cmd_enc->pp_timeout_report_cnt == PP_TIMEOUT_MAX_TRIALS) { frame_event |= DPU_ENCODER_FRAME_EVENT_PANEL_DEAD; @@ -203,7 +196,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( do_log = true; } - trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent), + trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(drm_enc), phys_enc->hw_pp->idx - PINGPONG_0, cmd_enc->pp_timeout_report_cnt, atomic_read(&phys_enc->pending_kickoff_cnt), @@ -212,12 +205,12 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( /* to avoid flooding, only log first time, and "dead" time */ if (do_log) { DRM_ERROR("id:%d pp:%d kickoff timeout %d cnt %d koff_cnt %d\n", - DRMID(phys_enc->parent), + DRMID(drm_enc), phys_enc->hw_pp->idx - PINGPONG_0, phys_enc->hw_ctl->idx - CTL_0, cmd_enc->pp_timeout_report_cnt, atomic_read(&phys_enc->pending_kickoff_cnt)); - + msm_disp_snapshot_state(drm_enc->dev); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR); } @@ -228,7 +221,7 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( if (phys_enc->parent_ops->handle_frame_done) phys_enc->parent_ops->handle_frame_done( - phys_enc->parent, phys_enc, frame_event); + drm_enc, phys_enc, frame_event); return -ETIMEDOUT; } @@ -685,10 +678,6 @@ static int dpu_encoder_phys_cmd_wait_for_tx_complete( static int dpu_encoder_phys_cmd_wait_for_commit_done( struct dpu_encoder_phys *phys_enc) { - struct dpu_encoder_phys_cmd *cmd_enc; - - cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - /* only required for master controller */ if (!dpu_encoder_phys_cmd_is_master(phys_enc)) return 0; @@ -795,31 +784,26 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( irq = &phys_enc->irq[i]; INIT_LIST_HEAD(&irq->cb.list); irq->irq_idx = -EINVAL; - irq->hw_idx = -EINVAL; irq->cb.arg = phys_enc; } irq = &phys_enc->irq[INTR_IDX_CTL_START]; irq->name = "ctl_start"; - irq->intr_type = DPU_IRQ_TYPE_CTL_START; irq->intr_idx = INTR_IDX_CTL_START; irq->cb.func = dpu_encoder_phys_cmd_ctl_start_irq; irq = &phys_enc->irq[INTR_IDX_PINGPONG]; irq->name = "pp_done"; - irq->intr_type = DPU_IRQ_TYPE_PING_PONG_COMP; irq->intr_idx = INTR_IDX_PINGPONG; irq->cb.func = dpu_encoder_phys_cmd_pp_tx_done_irq; irq = &phys_enc->irq[INTR_IDX_RDPTR]; irq->name = "pp_rd_ptr"; - irq->intr_type = DPU_IRQ_TYPE_PING_PONG_RD_PTR; irq->intr_idx = INTR_IDX_RDPTR; irq->cb.func = dpu_encoder_phys_cmd_pp_rd_ptr_irq; irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; irq->name = "underrun"; - irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN; irq->intr_idx = INTR_IDX_UNDERRUN; irq->cb.func = dpu_encoder_phys_cmd_underrun_irq; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 0e06b7e73c7a..185379b18572 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ @@ -9,6 +9,7 @@ #include "dpu_core_irq.h" #include "dpu_formats.h" #include "dpu_trace.h" +#include "disp/msm_disp_snapshot.h" #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ (e) && (e)->parent ? \ @@ -284,7 +285,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); if (phys_enc->hw_pp->merge_3d) - intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id; + intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, @@ -298,11 +299,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( true, phys_enc->hw_pp->idx); - if (phys_enc->hw_pp->merge_3d) { - struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d); - - merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d); - } + if (phys_enc->hw_pp->merge_3d) + phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -363,38 +361,24 @@ static bool dpu_encoder_phys_vid_needs_single_flush( return phys_enc->split_role != ENC_ROLE_SOLO; } -static void _dpu_encoder_phys_vid_setup_irq_hw_idx( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_irq *irq; - - /* - * Initialize irq->hw_idx only when irq is not registered. - * Prevent invalidating irq->irq_idx as modeset may be - * called many times during dfps. - */ - - irq = &phys_enc->irq[INTR_IDX_VSYNC]; - if (irq->irq_idx < 0) - irq->hw_idx = phys_enc->intf_idx; - - irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; - if (irq->irq_idx < 0) - irq->hw_idx = phys_enc->intf_idx; -} - static void dpu_encoder_phys_vid_mode_set( struct dpu_encoder_phys *phys_enc, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { + struct dpu_encoder_irq *irq; + if (adj_mode) { phys_enc->cached_mode = *adj_mode; drm_mode_debug_printmodeline(adj_mode); DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n"); } - _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc); + irq = &phys_enc->irq[INTR_IDX_VSYNC]; + irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync; + + irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; + irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun; } static int dpu_encoder_phys_vid_control_vblank_irq( @@ -416,7 +400,7 @@ static int dpu_encoder_phys_vid_control_vblank_irq( goto end; } - DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, + DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, atomic_read(&phys_enc->vblank_refcount)); if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) @@ -461,13 +445,14 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) - ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id); + ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); skip_flush: DPU_DEBUG_VIDENC(phys_enc, "update pending flush ctl %d intf %d\n", ctl->idx - CTL_0, phys_enc->hw_intf->idx); + atomic_set(&phys_enc->underrun_cnt, 0); /* ctl_flush & timing engine enable will be triggered by framework */ if (phys_enc->enable_state == DPU_ENC_DISABLED) @@ -537,6 +522,9 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( { struct dpu_hw_ctl *ctl; int rc; + struct drm_encoder *drm_enc; + + drm_enc = phys_enc->parent; ctl = phys_enc->hw_ctl; if (!ctl->ops.wait_reset_status) @@ -550,6 +538,7 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff( if (rc) { DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n", ctl->idx, rc); + msm_disp_snapshot_state(drm_enc->dev); dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC); } } @@ -636,7 +625,7 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, if (enable) { ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); - if (ret) + if (WARN_ON(ret)) return; dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); @@ -738,19 +727,16 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init( irq = &phys_enc->irq[i]; INIT_LIST_HEAD(&irq->cb.list); irq->irq_idx = -EINVAL; - irq->hw_idx = -EINVAL; irq->cb.arg = phys_enc; } irq = &phys_enc->irq[INTR_IDX_VSYNC]; irq->name = "vsync_irq"; - irq->intr_type = DPU_IRQ_TYPE_INTF_VSYNC; irq->intr_idx = INTR_IDX_VSYNC; irq->cb.func = dpu_encoder_phys_vid_vblank_irq; irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; irq->name = "underrun"; - irq->intr_type = DPU_IRQ_TYPE_INTF_UNDER_RUN; irq->intr_idx = INTR_IDX_UNDERRUN; irq->cb.func = dpu_encoder_phys_vid_underrun_irq; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 21ff8f9e5dfd..440ae93d7bd1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -992,7 +992,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( * Currently only support exactly zero or one modifier. * All planes use the same modifier. */ - DPU_DEBUG("plane format modifier 0x%llX\n", modifier); + DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier); switch (modifier) { case 0: @@ -1002,7 +1002,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( case DRM_FORMAT_MOD_QCOM_COMPRESSED: map = dpu_format_map_ubwc; map_size = ARRAY_SIZE(dpu_format_map_ubwc); - DPU_DEBUG("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n", + DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n", (char *)&format); break; default: @@ -1021,7 +1021,7 @@ const struct dpu_format *dpu_get_dpu_format_ext( DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n", (char *)&format, modifier); else - DPU_DEBUG("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n", + DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n", (char *)&format, modifier, DPU_FORMAT_IS_UBWC(fmt), DPU_FORMAT_IS_YUV(fmt)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c deleted file mode 100644 index 819b26e660b9..000000000000 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - */ - -#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ - -#include <linux/mutex.h> -#include <linux/errno.h> -#include <linux/slab.h> - -#include "dpu_hw_mdss.h" -#include "dpu_hw_blk.h" - -/* Serialization lock for dpu_hw_blk_list */ -static DEFINE_MUTEX(dpu_hw_blk_lock); - -/* List of all hw block objects */ -static LIST_HEAD(dpu_hw_blk_list); - -/** - * dpu_hw_blk_init - initialize hw block object - * @hw_blk: pointer to hw block object - * @type: hw block type - enum dpu_hw_blk_type - * @id: instance id of the hw block - * @ops: Pointer to block operations - */ -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops) -{ - INIT_LIST_HEAD(&hw_blk->list); - hw_blk->type = type; - hw_blk->id = id; - atomic_set(&hw_blk->refcount, 0); - - if (ops) - hw_blk->ops = *ops; - - mutex_lock(&dpu_hw_blk_lock); - list_add(&hw_blk->list, &dpu_hw_blk_list); - mutex_unlock(&dpu_hw_blk_lock); -} - -/** - * dpu_hw_blk_destroy - destroy hw block object. - * @hw_blk: pointer to hw block object - * return: none - */ -void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } - - if (atomic_read(&hw_blk->refcount)) - pr_err("hw_blk:%d.%d invalid refcount\n", hw_blk->type, - hw_blk->id); - - mutex_lock(&dpu_hw_blk_lock); - list_del(&hw_blk->list); - mutex_unlock(&dpu_hw_blk_lock); -} - -/** - * dpu_hw_blk_get - get hw_blk from free pool - * @hw_blk: if specified, increment reference count only - * @type: if hw_blk is not specified, allocate the next available of this type - * @id: if specified (>= 0), allocate the given instance of the above type - * return: pointer to hw block object - */ -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id) -{ - struct dpu_hw_blk *curr; - int rc, refcount; - - if (!hw_blk) { - mutex_lock(&dpu_hw_blk_lock); - list_for_each_entry(curr, &dpu_hw_blk_list, list) { - if ((curr->type != type) || - (id >= 0 && curr->id != id) || - (id < 0 && - atomic_read(&curr->refcount))) - continue; - - hw_blk = curr; - break; - } - mutex_unlock(&dpu_hw_blk_lock); - } - - if (!hw_blk) { - pr_debug("no hw_blk:%d\n", type); - return NULL; - } - - refcount = atomic_inc_return(&hw_blk->refcount); - - if (refcount == 1 && hw_blk->ops.start) { - rc = hw_blk->ops.start(hw_blk); - if (rc) { - pr_err("failed to start hw_blk:%d rc:%d\n", type, rc); - goto error_start; - } - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, - hw_blk->id, refcount); - return hw_blk; - -error_start: - dpu_hw_blk_put(hw_blk); - return ERR_PTR(rc); -} - -/** - * dpu_hw_blk_put - put hw_blk to free pool if decremented refcount is zero - * @hw_blk: hw block to be freed - */ -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk) -{ - if (!hw_blk) { - pr_err("invalid parameters\n"); - return; - } - - pr_debug("hw_blk:%d.%d refcount:%d\n", hw_blk->type, hw_blk->id, - atomic_read(&hw_blk->refcount)); - - if (!atomic_read(&hw_blk->refcount)) { - pr_err("hw_blk:%d.%d invalid put\n", hw_blk->type, hw_blk->id); - return; - } - - if (atomic_dec_return(&hw_blk->refcount)) - return; - - if (hw_blk->ops.stop) - hw_blk->ops.stop(hw_blk); -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h index 2bf737f8dd1b..52e92f37eda4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h @@ -7,19 +7,9 @@ #include <linux/types.h> #include <linux/list.h> -#include <linux/atomic.h> struct dpu_hw_blk; -/** - * struct dpu_hw_blk_ops - common hardware block operations - * @start: start operation on first get - * @stop: stop operation on last put - */ -struct dpu_hw_blk_ops { - int (*start)(struct dpu_hw_blk *); - void (*stop)(struct dpu_hw_blk *); -}; /** * struct dpu_hw_blk - definition of hardware block object @@ -29,17 +19,7 @@ struct dpu_hw_blk_ops { * @refcount: reference/usage count */ struct dpu_hw_blk { - struct list_head list; - u32 type; - int id; - atomic_t refcount; - struct dpu_hw_blk_ops ops; + /* opaque */ }; -void dpu_hw_blk_init(struct dpu_hw_blk *hw_blk, u32 type, int id, - struct dpu_hw_blk_ops *ops); -void dpu_hw_blk_destroy(struct dpu_hw_blk *hw_blk); - -struct dpu_hw_blk *dpu_hw_blk_get(struct dpu_hw_blk *hw_blk, u32 type, int id); -void dpu_hw_blk_put(struct dpu_hw_blk *hw_blk); #endif /*_DPU_HW_BLK_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b569030a0847..d01c4c919504 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -7,6 +7,7 @@ #include <linux/of_address.h> #include <linux/platform_device.h> #include "dpu_hw_mdss.h" +#include "dpu_hw_interrupts.h" #include "dpu_hw_catalog.h" #include "dpu_kms.h" @@ -56,12 +57,39 @@ #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) -#define INTR_SC7180_MASK \ - (BIT(DPU_IRQ_TYPE_PING_PONG_RD_PTR) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_WR_PTR) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_AUTO_REF) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK) |\ - BIT(DPU_IRQ_TYPE_PING_PONG_TE_CHECK)) +#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR) | \ + BIT(MDP_AD4_0_INTR) | \ + BIT(MDP_AD4_1_INTR)) + +#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR)) + +#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF5_7xxx_INTR)) + +#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF2_INTR) | \ + BIT(MDP_INTF3_INTR) | \ + BIT(MDP_INTF4_INTR)) + #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) #define DEFAULT_DPU_LINE_WIDTH 2048 @@ -315,27 +343,32 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0xE4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0xE4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0xE4, - .features = 0 + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0xE4, - .features = 0 + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0xE4, - .features = 0 + .features = 0, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; @@ -343,17 +376,20 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0xE4, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0xE4, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0xE4, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, }; @@ -361,32 +397,38 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x1000, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name = "ctl_5", .id = CTL_5, .base = 0x1a00, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; @@ -394,22 +436,26 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { { .name = "ctl_0", .id = CTL_0, .base = 0x15000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name = "ctl_1", .id = CTL_1, .base = 0x16000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name = "ctl_2", .id = CTL_2, .base = 0x17000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x18000, .len = 0x1E8, - .features = CTL_SC7280_MASK + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; @@ -690,42 +736,66 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { .len = 0x20, .version = 0x20000}, }; -#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk) \ +#define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0xd4, \ .features = PINGPONG_SDM845_SPLIT_MASK, \ .merge_3d = _merge_3d, \ - .sblk = &_sblk \ + .sblk = &_sblk, \ + .intr_done = _done, \ + .intr_rdptr = _rdptr, \ } -#define PP_BLK(_name, _id, _base, _merge_3d, _sblk) \ +#define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0xd4, \ .features = PINGPONG_SDM845_MASK, \ .merge_3d = _merge_3d, \ - .sblk = &_sblk \ + .sblk = &_sblk, \ + .intr_done = _done, \ + .intr_rdptr = _rdptr, \ } static const struct dpu_pingpong_cfg sdm845_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), }; static struct dpu_pingpong_cfg sc7180_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), }; static const struct dpu_pingpong_cfg sm8150_pp[] = { - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te), - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk), + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), }; /************************************************************* @@ -746,47 +816,49 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { }; static const struct dpu_pingpong_cfg sc7280_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk), - PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk), - PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk), - PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk), + PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), }; /************************************************************* * INTF sub blocks config *************************************************************/ -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features) \ +#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ {\ .name = _name, .id = _id, \ .base = _base, .len = 0x280, \ .features = _features, \ .type = _type, \ .controller_id = _ctrl_id, \ - .prog_fetch_lines_worst_case = _progfetch \ + .prog_fetch_lines_worst_case = _progfetch, \ + .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \ + .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ } static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; static const struct dpu_intf_cfg sc7180_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), }; static const struct dpu_intf_cfg sm8150_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK), - INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK), - INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK), - INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK), + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; static const struct dpu_intf_cfg sc7280_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK), - INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK), - INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK), + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_5", INTF_5, 0x39000, INTF_EDP, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), }; /************************************************************* @@ -1060,7 +1132,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sdm845_regdma, .perf = sdm845_perf_data, - .mdss_irqs = 0x3ff, + .mdss_irqs = IRQ_SDM845_MASK, }; } @@ -1091,8 +1163,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sdm845_regdma, .perf = sc7180_perf_data, - .mdss_irqs = 0x3f, - .obsolete_irq = INTR_SC7180_MASK, + .mdss_irqs = IRQ_SC7180_MASK, }; } @@ -1125,7 +1196,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sm8150_regdma, .perf = sm8150_perf_data, - .mdss_irqs = 0x3ff, + .mdss_irqs = IRQ_SDM845_MASK, }; } @@ -1158,7 +1229,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .reg_dma_count = 1, .dma_cfg = sm8250_regdma, .perf = sm8250_perf_data, - .mdss_irqs = 0xff, + .mdss_irqs = IRQ_SM8250_MASK, }; } @@ -1181,8 +1252,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = sc7280_perf_data, - .mdss_irqs = 0x1c07, - .obsolete_irq = INTR_SC7180_MASK, + .mdss_irqs = IRQ_SC7280_MASK, }; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4dfd8a20ad5c..d2a945a27cfa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. */ #ifndef _DPU_HW_CATALOG_H @@ -464,13 +464,15 @@ struct dpu_mdp_cfg { struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; -/* struct dpu_mdp_cfg : MDP TOP-BLK instance info +/* struct dpu_ctl_cfg : MDP CTL instance info * @id: index identifying this block * @base: register base offset to mdss * @features bit mask identifying sub-blocks/features + * @intr_start: interrupt index for CTL_START */ struct dpu_ctl_cfg { DPU_HW_BLK_INFO; + s32 intr_start; }; /** @@ -526,11 +528,15 @@ struct dpu_dspp_cfg { * @id enum identifying this block * @base register offset of this block * @features bit mask identifying sub-blocks/features + * @intr_done: index for PINGPONG done interrupt + * @intr_rdptr: index for PINGPONG readpointer done interrupt * @sblk sub-blocks information */ struct dpu_pingpong_cfg { DPU_HW_BLK_INFO; u32 merge_3d; + s32 intr_done; + s32 intr_rdptr; const struct dpu_pingpong_sub_blks *sblk; }; @@ -555,12 +561,16 @@ struct dpu_merge_3d_cfg { * @type: Interface type(DSI, DP, HDMI) * @controller_id: Controller Instance ID in case of multiple of intf type * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch + * @intr_underrun: index for INTF underrun interrupt + * @intr_vsync: index for INTF VSYNC interrupt */ struct dpu_intf_cfg { DPU_HW_BLK_INFO; u32 type; /* interface type*/ u32 controller_id; u32 prog_fetch_lines_worst_case; + s32 intr_underrun; + s32 intr_vsync; }; /** @@ -723,7 +733,6 @@ struct dpu_perf_cfg { * @cursor_formats Supported formats for cursor pipe * @vig_formats Supported formats for vig pipe * @mdss_irqs: Bitmap with the irqs supported by the target - * @obsolete_irq: Irq types that are obsolete for a particular target */ struct dpu_mdss_cfg { u32 hwversion; @@ -770,7 +779,6 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *vig_formats; unsigned long mdss_irqs; - unsigned long obsolete_irq; }; struct dpu_mdss_hw_cfg_handler { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 2d4645e01ebf..f8a74f6cdc4c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -589,8 +589,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -615,14 +613,10 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, c->mixer_count = m->mixer_count; c->mixer_hw_caps = m->mixer; - dpu_hw_blk_init(&c->base, DPU_HW_BLK_CTL, idx, &dpu_hw_ops); - return c; } void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx) { - if (ctx) - dpu_hw_blk_destroy(&ctx->base); kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index e42f901a7de5..a98e964c3b6f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -85,8 +85,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -112,16 +110,11 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx, c->cap = cfg; _setup_dspp_ops(c, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSPP, idx, &dpu_hw_ops); - return c; } void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp) { - if (dspp) - dpu_hw_blk_destroy(&dspp->base); - kfree(dspp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 48c96b812126..2e816f232e85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -30,145 +30,6 @@ #define MDP_INTF_5_OFF_REV_7xxx 0x39000 /** - * WB interrupt status bit definitions - */ -#define DPU_INTR_WB_0_DONE BIT(0) -#define DPU_INTR_WB_1_DONE BIT(1) -#define DPU_INTR_WB_2_DONE BIT(4) - -/** - * WDOG timer interrupt status bit definitions - */ -#define DPU_INTR_WD_TIMER_0_DONE BIT(2) -#define DPU_INTR_WD_TIMER_1_DONE BIT(3) -#define DPU_INTR_WD_TIMER_2_DONE BIT(5) -#define DPU_INTR_WD_TIMER_3_DONE BIT(6) -#define DPU_INTR_WD_TIMER_4_DONE BIT(7) - -/** - * Pingpong interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_0_DONE BIT(8) -#define DPU_INTR_PING_PONG_1_DONE BIT(9) -#define DPU_INTR_PING_PONG_2_DONE BIT(10) -#define DPU_INTR_PING_PONG_3_DONE BIT(11) -#define DPU_INTR_PING_PONG_0_RD_PTR BIT(12) -#define DPU_INTR_PING_PONG_1_RD_PTR BIT(13) -#define DPU_INTR_PING_PONG_2_RD_PTR BIT(14) -#define DPU_INTR_PING_PONG_3_RD_PTR BIT(15) -#define DPU_INTR_PING_PONG_0_WR_PTR BIT(16) -#define DPU_INTR_PING_PONG_1_WR_PTR BIT(17) -#define DPU_INTR_PING_PONG_2_WR_PTR BIT(18) -#define DPU_INTR_PING_PONG_3_WR_PTR BIT(19) -#define DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE BIT(20) -#define DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE BIT(21) -#define DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE BIT(22) -#define DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE BIT(23) - -/** - * Interface interrupt status bit definitions - */ -#define DPU_INTR_INTF_0_UNDERRUN BIT(24) -#define DPU_INTR_INTF_1_UNDERRUN BIT(26) -#define DPU_INTR_INTF_2_UNDERRUN BIT(28) -#define DPU_INTR_INTF_3_UNDERRUN BIT(30) -#define DPU_INTR_INTF_5_UNDERRUN BIT(22) -#define DPU_INTR_INTF_0_VSYNC BIT(25) -#define DPU_INTR_INTF_1_VSYNC BIT(27) -#define DPU_INTR_INTF_2_VSYNC BIT(29) -#define DPU_INTR_INTF_3_VSYNC BIT(31) -#define DPU_INTR_INTF_5_VSYNC BIT(23) - -/** - * Pingpong Secondary interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0) -#define DPU_INTR_PING_PONG_S0_WR_PTR BIT(4) -#define DPU_INTR_PING_PONG_S0_RD_PTR BIT(8) -#define DPU_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22) -#define DPU_INTR_PING_PONG_S0_TE_DETECTED BIT(28) - -/** - * Pingpong TEAR detection interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_0_TEAR_DETECTED BIT(16) -#define DPU_INTR_PING_PONG_1_TEAR_DETECTED BIT(17) -#define DPU_INTR_PING_PONG_2_TEAR_DETECTED BIT(18) -#define DPU_INTR_PING_PONG_3_TEAR_DETECTED BIT(19) - -/** - * Pingpong TE detection interrupt status bit definitions - */ -#define DPU_INTR_PING_PONG_0_TE_DETECTED BIT(24) -#define DPU_INTR_PING_PONG_1_TE_DETECTED BIT(25) -#define DPU_INTR_PING_PONG_2_TE_DETECTED BIT(26) -#define DPU_INTR_PING_PONG_3_TE_DETECTED BIT(27) - -/** - * Ctl start interrupt status bit definitions - */ -#define DPU_INTR_CTL_0_START BIT(9) -#define DPU_INTR_CTL_1_START BIT(10) -#define DPU_INTR_CTL_2_START BIT(11) -#define DPU_INTR_CTL_3_START BIT(12) -#define DPU_INTR_CTL_4_START BIT(13) - -/** - * Concurrent WB overflow interrupt status bit definitions - */ -#define DPU_INTR_CWB_2_OVERFLOW BIT(14) -#define DPU_INTR_CWB_3_OVERFLOW BIT(15) - -/** - * Histogram VIG done interrupt status bit definitions - */ -#define DPU_INTR_HIST_VIG_0_DONE BIT(0) -#define DPU_INTR_HIST_VIG_1_DONE BIT(4) -#define DPU_INTR_HIST_VIG_2_DONE BIT(8) -#define DPU_INTR_HIST_VIG_3_DONE BIT(10) - -/** - * Histogram VIG reset Sequence done interrupt status bit definitions - */ -#define DPU_INTR_HIST_VIG_0_RSTSEQ_DONE BIT(1) -#define DPU_INTR_HIST_VIG_1_RSTSEQ_DONE BIT(5) -#define DPU_INTR_HIST_VIG_2_RSTSEQ_DONE BIT(9) -#define DPU_INTR_HIST_VIG_3_RSTSEQ_DONE BIT(11) - -/** - * Histogram DSPP done interrupt status bit definitions - */ -#define DPU_INTR_HIST_DSPP_0_DONE BIT(12) -#define DPU_INTR_HIST_DSPP_1_DONE BIT(16) -#define DPU_INTR_HIST_DSPP_2_DONE BIT(20) -#define DPU_INTR_HIST_DSPP_3_DONE BIT(22) - -/** - * Histogram DSPP reset Sequence done interrupt status bit definitions - */ -#define DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE BIT(13) -#define DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE BIT(17) -#define DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE BIT(21) -#define DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE BIT(23) - -/** - * INTF interrupt status bit definitions - */ -#define DPU_INTR_VIDEO_INTO_STATIC BIT(0) -#define DPU_INTR_VIDEO_OUTOF_STATIC BIT(1) -#define DPU_INTR_DSICMD_0_INTO_STATIC BIT(2) -#define DPU_INTR_DSICMD_0_OUTOF_STATIC BIT(3) -#define DPU_INTR_DSICMD_1_INTO_STATIC BIT(4) -#define DPU_INTR_DSICMD_1_OUTOF_STATIC BIT(5) -#define DPU_INTR_DSICMD_2_INTO_STATIC BIT(6) -#define DPU_INTR_DSICMD_2_OUTOF_STATIC BIT(7) -#define DPU_INTR_PROG_LINE BIT(8) - -/** - * AD4 interrupt status bit definitions - */ -#define DPU_INTR_BACKLIGHT_UPDATED BIT(0) -/** * struct dpu_intr_reg - array of DPU register sets * @clr_off: offset to CLEAR reg * @en_off: offset to ENABLE reg @@ -180,22 +41,10 @@ struct dpu_intr_reg { u32 status_off; }; -/** - * struct dpu_irq_type - maps each irq with i/f - * @intr_type: type of interrupt listed in dpu_intr_type - * @instance_idx: instance index of the associated HW block in DPU - * @irq_mask: corresponding bit in the interrupt status reg - * @reg_idx: which reg set to use - */ -struct dpu_irq_type { - u32 intr_type; - u32 instance_idx; - u32 irq_mask; - u32 reg_idx; -}; - /* * struct dpu_intr_reg - List of DPU interrupt registers + * + * When making changes be sure to sync with dpu_hw_intr_reg */ static const struct dpu_intr_reg dpu_intr_set[] = { { @@ -265,1101 +114,22 @@ static const struct dpu_intr_reg dpu_intr_set[] = { }, }; -/* - * struct dpu_irq_type - IRQ mapping table use for lookup an irq_idx in this - * table that have a matching interface type and - * instance index. - */ -static const struct dpu_irq_type dpu_irq_map[] = { - /* BEGIN MAP_RANGE: 0-31, INTR */ - /* irq_idx: 0-3 */ - { DPU_IRQ_TYPE_WB_ROT_COMP, WB_0, DPU_INTR_WB_0_DONE, 0}, - { DPU_IRQ_TYPE_WB_ROT_COMP, WB_1, DPU_INTR_WB_1_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_0, DPU_INTR_WD_TIMER_0_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_1, DPU_INTR_WD_TIMER_1_DONE, 0}, - /* irq_idx: 4-7 */ - { DPU_IRQ_TYPE_WB_WFD_COMP, WB_2, DPU_INTR_WB_2_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_2, DPU_INTR_WD_TIMER_2_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_3, DPU_INTR_WD_TIMER_3_DONE, 0}, - { DPU_IRQ_TYPE_WD_TIMER, WD_TIMER_4, DPU_INTR_WD_TIMER_4_DONE, 0}, - /* irq_idx: 8-11 */ - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_0, - DPU_INTR_PING_PONG_0_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_1, - DPU_INTR_PING_PONG_1_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_2, - DPU_INTR_PING_PONG_2_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_COMP, PINGPONG_3, - DPU_INTR_PING_PONG_3_DONE, 0}, - /* irq_idx: 12-15 */ - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_0, - DPU_INTR_PING_PONG_0_RD_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_1, - DPU_INTR_PING_PONG_1_RD_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_2, - DPU_INTR_PING_PONG_2_RD_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_3, - DPU_INTR_PING_PONG_3_RD_PTR, 0}, - /* irq_idx: 16-19 */ - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_0, - DPU_INTR_PING_PONG_0_WR_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_1, - DPU_INTR_PING_PONG_1_WR_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_2, - DPU_INTR_PING_PONG_2_WR_PTR, 0}, - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_3, - DPU_INTR_PING_PONG_3_WR_PTR, 0}, - /* irq_idx: 20-23 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_0, - DPU_INTR_PING_PONG_0_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_1, - DPU_INTR_PING_PONG_1_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_2, - DPU_INTR_PING_PONG_2_AUTOREFRESH_DONE, 0}, - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_3, - DPU_INTR_PING_PONG_3_AUTOREFRESH_DONE, 0}, - /* irq_idx: 24-27 */ - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_0, DPU_INTR_INTF_0_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_0, DPU_INTR_INTF_0_VSYNC, 0}, - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_1, DPU_INTR_INTF_1_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_1, DPU_INTR_INTF_1_VSYNC, 0}, - /* irq_idx: 28-31 */ - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_2, DPU_INTR_INTF_2_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_2, DPU_INTR_INTF_2_VSYNC, 0}, - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_3, DPU_INTR_INTF_3_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_3, DPU_INTR_INTF_3_VSYNC, 0}, - /* irq_idx:32-33 */ - { DPU_IRQ_TYPE_INTF_UNDER_RUN, INTF_5, DPU_INTR_INTF_5_UNDERRUN, 0}, - { DPU_IRQ_TYPE_INTF_VSYNC, INTF_5, DPU_INTR_INTF_5_VSYNC, 0}, - /* irq_idx:34-63 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 0}, - /* BEGIN MAP_RANGE: 64-95, INTR2 */ - /* irq_idx: 64-67 */ - { DPU_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_AUTOREFRESH_DONE, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 68-71 */ - { DPU_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_WR_PTR, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 72 */ - { DPU_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_RD_PTR, 1}, - /* irq_idx: 73-77 */ - { DPU_IRQ_TYPE_CTL_START, CTL_0, - DPU_INTR_CTL_0_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_1, - DPU_INTR_CTL_1_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_2, - DPU_INTR_CTL_2_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_3, - DPU_INTR_CTL_3_START, 1}, - { DPU_IRQ_TYPE_CTL_START, CTL_4, - DPU_INTR_CTL_4_START, 1}, - /* irq_idx: 78-79 */ - { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_2, DPU_INTR_CWB_2_OVERFLOW, 1}, - { DPU_IRQ_TYPE_CWB_OVERFLOW, CWB_3, DPU_INTR_CWB_3_OVERFLOW, 1}, - /* irq_idx: 80-83 */ - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0, - DPU_INTR_PING_PONG_0_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1, - DPU_INTR_PING_PONG_1_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2, - DPU_INTR_PING_PONG_2_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3, - DPU_INTR_PING_PONG_3_TEAR_DETECTED, 1}, - /* irq_idx: 84-87 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_TEAR_DETECTED, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 88-91 */ - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0, - DPU_INTR_PING_PONG_0_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1, - DPU_INTR_PING_PONG_1_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2, - DPU_INTR_PING_PONG_2_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3, - DPU_INTR_PING_PONG_3_TE_DETECTED, 1}, - /* irq_idx: 92-95 */ - { DPU_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0, - DPU_INTR_PING_PONG_S0_TE_DETECTED, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* irq_idx: 96-127 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 1}, - /* BEGIN MAP_RANGE: 128-159 HIST */ - /* irq_idx: 128-131 */ - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG0, DPU_INTR_HIST_VIG_0_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG0, - DPU_INTR_HIST_VIG_0_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 132-135 */ - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG1, DPU_INTR_HIST_VIG_1_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG1, - DPU_INTR_HIST_VIG_1_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 136-139 */ - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG2, DPU_INTR_HIST_VIG_2_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG2, - DPU_INTR_HIST_VIG_2_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_DONE, SSPP_VIG3, DPU_INTR_HIST_VIG_3_DONE, 2}, - { DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, SSPP_VIG3, - DPU_INTR_HIST_VIG_3_RSTSEQ_DONE, 2}, - /* irq_idx: 140-143 */ - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_0, DPU_INTR_HIST_DSPP_0_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_0, - DPU_INTR_HIST_DSPP_0_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 144-147 */ - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_1, DPU_INTR_HIST_DSPP_1_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_1, - DPU_INTR_HIST_DSPP_1_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 148-151 */ - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_2, DPU_INTR_HIST_DSPP_2_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_2, - DPU_INTR_HIST_DSPP_2_RSTSEQ_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_DONE, DSPP_3, DPU_INTR_HIST_DSPP_3_DONE, 2}, - { DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, DSPP_3, - DPU_INTR_HIST_DSPP_3_RSTSEQ_DONE, 2}, - /* irq_idx: 152-155 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 156-159 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* irq_idx: 160-191 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 2}, - /* BEGIN MAP_RANGE: 192-255 INTF_0_INTR */ - /* irq_idx: 192-195 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, - DPU_INTR_VIDEO_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, - DPU_INTR_VIDEO_OUTOF_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, - DPU_INTR_DSICMD_0_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 3}, - /* irq_idx: 196-199 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, - DPU_INTR_DSICMD_1_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, - DPU_INTR_DSICMD_2_INTO_STATIC, 3}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 3}, - /* irq_idx: 200-203 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 204-207 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 208-211 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 212-215 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 216-219 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 220-223 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* irq_idx: 224-255 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 3}, - /* BEGIN MAP_RANGE: 256-319 INTF_1_INTR */ - /* irq_idx: 256-259 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, - DPU_INTR_VIDEO_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, - DPU_INTR_VIDEO_OUTOF_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, - DPU_INTR_DSICMD_0_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 4}, - /* irq_idx: 260-263 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, - DPU_INTR_DSICMD_1_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, - DPU_INTR_DSICMD_2_INTO_STATIC, 4}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 4}, - /* irq_idx: 264-267 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 268-271 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 272-275 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 276-279 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 280-283 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 284-287 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* irq_idx: 288-319 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 4}, - /* BEGIN MAP_RANGE: 320-383 INTF_2_INTR */ - /* irq_idx: 320-323 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_2, - DPU_INTR_VIDEO_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_2, - DPU_INTR_VIDEO_OUTOF_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_2, - DPU_INTR_DSICMD_0_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_2, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 5}, - /* irq_idx: 324-327 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_2, - DPU_INTR_DSICMD_1_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_2, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_2, - DPU_INTR_DSICMD_2_INTO_STATIC, 5}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_2, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 5}, - /* irq_idx: 328-331 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_2, DPU_INTR_PROG_LINE, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 332-335 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 336-339 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 340-343 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 344-347 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 348-351 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* irq_idx: 352-383 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 5}, - /* BEGIN MAP_RANGE: 384-447 INTF_3_INTR */ - /* irq_idx: 384-387 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_3, - DPU_INTR_VIDEO_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_3, - DPU_INTR_VIDEO_OUTOF_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_3, - DPU_INTR_DSICMD_0_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_3, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 6}, - /* irq_idx: 388-391 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_3, - DPU_INTR_DSICMD_1_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_3, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_3, - DPU_INTR_DSICMD_2_INTO_STATIC, 6}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_3, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 6}, - /* irq_idx: 392-395 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_3, DPU_INTR_PROG_LINE, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 396-399 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 400-403 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 404-407 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 408-411 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 412-415 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* irq_idx: 416-447*/ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 6}, - /* BEGIN MAP_RANGE: 448-511 INTF_4_INTR */ - /* irq_idx: 448-451 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_4, - DPU_INTR_VIDEO_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_4, - DPU_INTR_VIDEO_OUTOF_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_4, - DPU_INTR_DSICMD_0_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_4, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 7}, - /* irq_idx: 452-455 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_4, - DPU_INTR_DSICMD_1_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_4, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_4, - DPU_INTR_DSICMD_2_INTO_STATIC, 7}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_4, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 7}, - /* irq_idx: 456-459 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_4, DPU_INTR_PROG_LINE, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 460-463 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 464-467 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 468-471 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 472-475 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 476-479 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* irq_idx: 480-511 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 7}, - /* BEGIN MAP_RANGE: 512-575 AD4_0_INTR */ - /* irq_idx: 512-515 */ - { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_0, DPU_INTR_BACKLIGHT_UPDATED, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 516-519 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 520-523 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 524-527 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 528-531 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 532-535 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 536-539 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 540-543 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* irq_idx: 544-575*/ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 8}, - /* BEGIN MAP_RANGE: 576-639 AD4_1_INTR */ - /* irq_idx: 576-579 */ - { DPU_IRQ_TYPE_AD4_BL_DONE, DSPP_1, DPU_INTR_BACKLIGHT_UPDATED, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 580-583 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 584-587 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 588-591 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 592-595 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 596-599 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 600-603 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 604-607 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* irq_idx: 608-639 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 9}, - /* BEGIN MAP_RANGE: 640-703 INTF_0_SC7280_INTR */ - /* irq_idx: 640-643 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_0, - DPU_INTR_VIDEO_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_0, - DPU_INTR_VIDEO_OUTOF_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_0, - DPU_INTR_DSICMD_0_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_0, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 10}, - /* irq_idx: 644-647 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_0, - DPU_INTR_DSICMD_1_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_0, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_0, - DPU_INTR_DSICMD_2_INTO_STATIC, 10}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_0, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 10}, - /* irq_idx: 648-651 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_0, DPU_INTR_PROG_LINE, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 652-655 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 656-659 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 660-663 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 664-667 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 668-671 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* irq_idx: 672-703 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 10}, - /* BEGIN MAP_RANGE: 704-767 INTF_1_SC7280_INTR */ - /* irq_idx: 704-707 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_1, - DPU_INTR_VIDEO_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_1, - DPU_INTR_VIDEO_OUTOF_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_1, - DPU_INTR_DSICMD_0_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_1, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 11}, - /* irq_idx: 708-711 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_1, - DPU_INTR_DSICMD_1_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_1, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_1, - DPU_INTR_DSICMD_2_INTO_STATIC, 11}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_1, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 11}, - /* irq_idx: 712-715 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_1, DPU_INTR_PROG_LINE, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 716-719 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 720-723 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 724-727 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 728-731 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 732-735 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* irq_idx: 736-767 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 11}, - /* BEGIN MAP_RANGE: 768-831 INTF_5_SC7280_INTR */ - /* irq_idx: 768-771 */ - { DPU_IRQ_TYPE_SFI_VIDEO_IN, INTF_5, - DPU_INTR_VIDEO_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_VIDEO_OUT, INTF_5, - DPU_INTR_VIDEO_OUTOF_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_0_IN, INTF_5, - DPU_INTR_DSICMD_0_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_0_OUT, INTF_5, - DPU_INTR_DSICMD_0_OUTOF_STATIC, 12}, - /* irq_idx: 772-775 */ - { DPU_IRQ_TYPE_SFI_CMD_1_IN, INTF_5, - DPU_INTR_DSICMD_1_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_1_OUT, INTF_5, - DPU_INTR_DSICMD_1_OUTOF_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_2_IN, INTF_5, - DPU_INTR_DSICMD_2_INTO_STATIC, 12}, - { DPU_IRQ_TYPE_SFI_CMD_2_OUT, INTF_5, - DPU_INTR_DSICMD_2_OUTOF_STATIC, 12}, - /* irq_idx: 776-779 */ - { DPU_IRQ_TYPE_PROG_LINE, INTF_5, DPU_INTR_PROG_LINE, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 780-783 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 784-787 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 788-791 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 792-795 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 796-799 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - /* irq_idx: 800-831 */ - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, - { DPU_IRQ_TYPE_RESERVED, 0, 0, 12}, -}; +#define DPU_IRQ_REG(irq_idx) (irq_idx / 32) +#define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32)) -static int dpu_hw_intr_irqidx_lookup(struct dpu_hw_intr *intr, - enum dpu_intr_type intr_type, u32 instance_idx) +static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, + int irq_idx) { - int i; + int reg_idx; - for (i = 0; i < ARRAY_SIZE(dpu_irq_map); i++) { - if (intr_type == dpu_irq_map[i].intr_type && - instance_idx == dpu_irq_map[i].instance_idx && - !(intr->obsolete_irq & BIT(dpu_irq_map[i].intr_type))) - return i; - } + if (!intr) + return; - pr_debug("IRQ lookup fail!! intr_type=%d, instance_idx=%d\n", - intr_type, instance_idx); - return -EINVAL; + reg_idx = DPU_IRQ_REG(irq_idx); + DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, DPU_IRQ_MASK(irq_idx)); + + /* ensure register writes go through */ + wmb(); } static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, @@ -1368,9 +138,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, { int reg_idx; int irq_idx; - int start_idx; - int end_idx; u32 irq_status; + u32 enable_mask; + int bit; unsigned long irq_flags; if (!intr) @@ -1383,86 +153,92 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr, */ spin_lock_irqsave(&intr->irq_lock, irq_flags); for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { - irq_status = intr->save_irq_status[reg_idx]; + if (!test_bit(reg_idx, &intr->irq_mask)) + continue; - /* - * Each Interrupt register has a range of 64 indexes, and - * that is static for dpu_irq_map. - */ - start_idx = reg_idx * 64; - end_idx = start_idx + 64; + /* Read interrupt status */ + irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); + + /* Read enable mask */ + enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); + + /* and clear the interrupt */ + if (irq_status) + DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + irq_status); - if (!test_bit(reg_idx, &intr->irq_mask) || - start_idx >= ARRAY_SIZE(dpu_irq_map)) + /* Finally update IRQ status based on enable mask */ + irq_status &= enable_mask; + + if (!irq_status) continue; /* - * Search through matching intr status from irq map. - * start_idx and end_idx defined the search range in - * the dpu_irq_map. + * Search through matching intr status. */ - for (irq_idx = start_idx; - (irq_idx < end_idx) && irq_status; - irq_idx++) - if ((irq_status & dpu_irq_map[irq_idx].irq_mask) && - (dpu_irq_map[irq_idx].reg_idx == reg_idx) && - !(intr->obsolete_irq & - BIT(dpu_irq_map[irq_idx].intr_type))) { - /* - * Once a match on irq mask, perform a callback - * to the given cbfunc. cbfunc will take care - * the interrupt status clearing. If cbfunc is - * not provided, then the interrupt clearing - * is here. - */ - if (cbfunc) - cbfunc(arg, irq_idx); - else - intr->ops.clear_intr_status_nolock( - intr, irq_idx); - - /* - * When callback finish, clear the irq_status - * with the matching mask. Once irq_status - * is all cleared, the search can be stopped. - */ - irq_status &= ~dpu_irq_map[irq_idx].irq_mask; - } + while ((bit = ffs(irq_status)) != 0) { + irq_idx = DPU_IRQ_IDX(reg_idx, bit - 1); + /* + * Once a match on irq mask, perform a callback + * to the given cbfunc. cbfunc will take care + * the interrupt status clearing. If cbfunc is + * not provided, then the interrupt clearing + * is here. + */ + if (cbfunc) + cbfunc(arg, irq_idx); + + dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); + + /* + * When callback finish, clear the irq_status + * with the matching mask. Once irq_status + * is all cleared, the search can be stopped. + */ + irq_status &= ~BIT(bit - 1); + } } + + /* ensure register writes go through */ + wmb(); + spin_unlock_irqrestore(&intr->irq_lock, irq_flags); } -static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) +static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; - unsigned long irq_flags; const struct dpu_intr_reg *reg; - const struct dpu_irq_type *irq; const char *dbgstr = NULL; uint32_t cache_irq_mask; if (!intr) return -EINVAL; - if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { + if (irq_idx < 0 || irq_idx >= intr->total_irqs) { pr_err("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - irq = &dpu_irq_map[irq_idx]; - reg_idx = irq->reg_idx; + /* + * The cache_irq_mask and hardware RMW operations needs to be done + * under irq_lock and it's the caller's responsibility to ensure that's + * held. + */ + assert_spin_locked(&intr->irq_lock); + + reg_idx = DPU_IRQ_REG(irq_idx); reg = &dpu_intr_set[reg_idx]; - spin_lock_irqsave(&intr->irq_lock, irq_flags); cache_irq_mask = intr->cache_irq_mask[reg_idx]; - if (cache_irq_mask & irq->irq_mask) { + if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) { dbgstr = "DPU IRQ already set:"; } else { dbgstr = "DPU IRQ enabled:"; - cache_irq_mask |= irq->irq_mask; + cache_irq_mask |= DPU_IRQ_MASK(irq_idx); /* Cleaning any pending interrupt */ - DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); + DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); /* Enabling interrupts with the new mask */ DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); @@ -1471,45 +247,49 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx) intr->cache_irq_mask[reg_idx] = cache_irq_mask; } - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); - pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, - irq->irq_mask, cache_irq_mask); + pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr, + DPU_IRQ_MASK(irq_idx), cache_irq_mask); return 0; } -static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) +static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) { int reg_idx; const struct dpu_intr_reg *reg; - const struct dpu_irq_type *irq; const char *dbgstr = NULL; uint32_t cache_irq_mask; if (!intr) return -EINVAL; - if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { + if (irq_idx < 0 || irq_idx >= intr->total_irqs) { pr_err("invalid IRQ index: [%d]\n", irq_idx); return -EINVAL; } - irq = &dpu_irq_map[irq_idx]; - reg_idx = irq->reg_idx; + /* + * The cache_irq_mask and hardware RMW operations needs to be done + * under irq_lock and it's the caller's responsibility to ensure that's + * held. + */ + assert_spin_locked(&intr->irq_lock); + + reg_idx = DPU_IRQ_REG(irq_idx); reg = &dpu_intr_set[reg_idx]; cache_irq_mask = intr->cache_irq_mask[reg_idx]; - if ((cache_irq_mask & irq->irq_mask) == 0) { + if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) { dbgstr = "DPU IRQ is already cleared:"; } else { dbgstr = "DPU IRQ mask disable:"; - cache_irq_mask &= ~irq->irq_mask; + cache_irq_mask &= ~DPU_IRQ_MASK(irq_idx); /* Disable interrupts based on the new mask */ DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); /* Cleaning any pending interrupt */ - DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask); + DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); /* ensure register write goes through */ wmb(); @@ -1517,27 +297,8 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx) intr->cache_irq_mask[reg_idx] = cache_irq_mask; } - pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr, - irq->irq_mask, cache_irq_mask); - - return 0; -} - -static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx) -{ - unsigned long irq_flags; - - if (!intr) - return -EINVAL; - - if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) { - pr_err("invalid IRQ index: [%d]\n", irq_idx); - return -EINVAL; - } - - spin_lock_irqsave(&intr->irq_lock, irq_flags); - dpu_hw_intr_disable_irq_nolock(intr, irq_idx); - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); + pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr, + DPU_IRQ_MASK(irq_idx), cache_irq_mask); return 0; } @@ -1580,58 +341,6 @@ static int dpu_hw_intr_disable_irqs(struct dpu_hw_intr *intr) return 0; } -static void dpu_hw_intr_get_interrupt_statuses(struct dpu_hw_intr *intr) -{ - int i; - u32 enable_mask; - unsigned long irq_flags; - - if (!intr) - return; - - spin_lock_irqsave(&intr->irq_lock, irq_flags); - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { - if (!test_bit(i, &intr->irq_mask)) - continue; - - /* Read interrupt status */ - intr->save_irq_status[i] = DPU_REG_READ(&intr->hw, - dpu_intr_set[i].status_off); - - /* Read enable mask */ - enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[i].en_off); - - /* and clear the interrupt */ - if (intr->save_irq_status[i]) - DPU_REG_WRITE(&intr->hw, dpu_intr_set[i].clr_off, - intr->save_irq_status[i]); - - /* Finally update IRQ status based on enable mask */ - intr->save_irq_status[i] &= enable_mask; - } - - /* ensure register writes go through */ - wmb(); - - spin_unlock_irqrestore(&intr->irq_lock, irq_flags); -} - -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr *intr, - int irq_idx) -{ - int reg_idx; - - if (!intr) - return; - - reg_idx = dpu_irq_map[irq_idx].reg_idx; - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, - dpu_irq_map[irq_idx].irq_mask); - - /* ensure register writes go through */ - wmb(); -} - static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, int irq_idx, bool clear) { @@ -1642,17 +351,17 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, if (!intr) return 0; - if (irq_idx >= ARRAY_SIZE(dpu_irq_map) || irq_idx < 0) { + if (irq_idx < 0 || irq_idx >= intr->total_irqs) { pr_err("invalid IRQ index: [%d]\n", irq_idx); return 0; } spin_lock_irqsave(&intr->irq_lock, irq_flags); - reg_idx = dpu_irq_map[irq_idx].reg_idx; + reg_idx = DPU_IRQ_REG(irq_idx); intr_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off) & - dpu_irq_map[irq_idx].irq_mask; + DPU_IRQ_MASK(irq_idx); if (intr_status && clear) DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, intr_status); @@ -1665,17 +374,30 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr, return intr_status; } +static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&intr->irq_lock, irq_flags); + + return irq_flags; +} + +static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags) +{ + spin_unlock_irqrestore(&intr->irq_lock, irq_flags); +} + static void __setup_intr_ops(struct dpu_hw_intr_ops *ops) { - ops->irq_idx_lookup = dpu_hw_intr_irqidx_lookup; - ops->enable_irq = dpu_hw_intr_enable_irq; - ops->disable_irq = dpu_hw_intr_disable_irq; + ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked; + ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked; ops->dispatch_irqs = dpu_hw_intr_dispatch_irq; ops->clear_all_irqs = dpu_hw_intr_clear_irqs; ops->disable_all_irqs = dpu_hw_intr_disable_irqs; - ops->get_interrupt_statuses = dpu_hw_intr_get_interrupt_statuses; - ops->clear_intr_status_nolock = dpu_hw_intr_clear_intr_status_nolock; ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status; + ops->lock = dpu_hw_intr_lock; + ops->unlock = dpu_hw_intr_unlock; } static void __intr_offset(struct dpu_mdss_cfg *m, @@ -1701,7 +423,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, __intr_offset(m, addr, &intr->hw); __setup_intr_ops(&intr->ops); - intr->irq_idx_tbl_size = ARRAY_SIZE(dpu_irq_map); + intr->total_irqs = ARRAY_SIZE(dpu_intr_set) * 32; intr->cache_irq_mask = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), GFP_KERNEL); @@ -1710,16 +432,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, return ERR_PTR(-ENOMEM); } - intr->save_irq_status = kcalloc(ARRAY_SIZE(dpu_intr_set), sizeof(u32), - GFP_KERNEL); - if (intr->save_irq_status == NULL) { - kfree(intr->cache_irq_mask); - kfree(intr); - return ERR_PTR(-ENOMEM); - } - intr->irq_mask = m->mdss_irqs; - intr->obsolete_irq = m->obsolete_irq; spin_lock_init(&intr->irq_lock); @@ -1730,7 +443,6 @@ void dpu_hw_intr_destroy(struct dpu_hw_intr *intr) { if (intr) { kfree(intr->cache_irq_mask); - kfree(intr->save_irq_status); kfree(intr); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 5d6f9a7a5195..ac83c1159815 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -12,85 +12,32 @@ #include "dpu_hw_util.h" #include "dpu_hw_mdss.h" -/** - * dpu_intr_type - HW Interrupt Type - * @DPU_IRQ_TYPE_WB_ROT_COMP: WB rotator done - * @DPU_IRQ_TYPE_WB_WFD_COMP: WB WFD done - * @DPU_IRQ_TYPE_PING_PONG_COMP: PingPong done - * @DPU_IRQ_TYPE_PING_PONG_RD_PTR: PingPong read pointer - * @DPU_IRQ_TYPE_PING_PONG_WR_PTR: PingPong write pointer - * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF: PingPong auto refresh - * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK: PingPong Tear check - * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK: PingPong TE detection - * @DPU_IRQ_TYPE_INTF_UNDER_RUN: INTF underrun - * @DPU_IRQ_TYPE_INTF_VSYNC: INTF VSYNC - * @DPU_IRQ_TYPE_CWB_OVERFLOW: Concurrent WB overflow - * @DPU_IRQ_TYPE_HIST_VIG_DONE: VIG Histogram done - * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ: VIG Histogram reset - * @DPU_IRQ_TYPE_HIST_DSPP_DONE: DSPP Histogram done - * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ: DSPP Histogram reset - * @DPU_IRQ_TYPE_WD_TIMER: Watchdog timer - * @DPU_IRQ_TYPE_SFI_VIDEO_IN: Video static frame INTR into static - * @DPU_IRQ_TYPE_SFI_VIDEO_OUT: Video static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_0_IN: DSI CMD0 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_0_OUT: DSI CMD0 static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_1_IN: DSI CMD1 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_1_OUT: DSI CMD1 static frame INTR out-of static - * @DPU_IRQ_TYPE_SFI_CMD_2_IN: DSI CMD2 static frame INTR into static - * @DPU_IRQ_TYPE_SFI_CMD_2_OUT: DSI CMD2 static frame INTR out-of static - * @DPU_IRQ_TYPE_PROG_LINE: Programmable Line interrupt - * @DPU_IRQ_TYPE_AD4_BL_DONE: AD4 backlight - * @DPU_IRQ_TYPE_CTL_START: Control start - * @DPU_IRQ_TYPE_RESERVED: Reserved for expansion - */ -enum dpu_intr_type { - DPU_IRQ_TYPE_WB_ROT_COMP, - DPU_IRQ_TYPE_WB_WFD_COMP, - DPU_IRQ_TYPE_PING_PONG_COMP, - DPU_IRQ_TYPE_PING_PONG_RD_PTR, - DPU_IRQ_TYPE_PING_PONG_WR_PTR, - DPU_IRQ_TYPE_PING_PONG_AUTO_REF, - DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK, - DPU_IRQ_TYPE_PING_PONG_TE_CHECK, - DPU_IRQ_TYPE_INTF_UNDER_RUN, - DPU_IRQ_TYPE_INTF_VSYNC, - DPU_IRQ_TYPE_CWB_OVERFLOW, - DPU_IRQ_TYPE_HIST_VIG_DONE, - DPU_IRQ_TYPE_HIST_VIG_RSTSEQ, - DPU_IRQ_TYPE_HIST_DSPP_DONE, - DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ, - DPU_IRQ_TYPE_WD_TIMER, - DPU_IRQ_TYPE_SFI_VIDEO_IN, - DPU_IRQ_TYPE_SFI_VIDEO_OUT, - DPU_IRQ_TYPE_SFI_CMD_0_IN, - DPU_IRQ_TYPE_SFI_CMD_0_OUT, - DPU_IRQ_TYPE_SFI_CMD_1_IN, - DPU_IRQ_TYPE_SFI_CMD_1_OUT, - DPU_IRQ_TYPE_SFI_CMD_2_IN, - DPU_IRQ_TYPE_SFI_CMD_2_OUT, - DPU_IRQ_TYPE_PROG_LINE, - DPU_IRQ_TYPE_AD4_BL_DONE, - DPU_IRQ_TYPE_CTL_START, - DPU_IRQ_TYPE_RESERVED, +/* When making changes be sure to sync with dpu_intr_set */ +enum dpu_hw_intr_reg { + MDP_SSPP_TOP0_INTR, + MDP_SSPP_TOP0_INTR2, + MDP_SSPP_TOP0_HIST_INTR, + MDP_INTF0_INTR, + MDP_INTF1_INTR, + MDP_INTF2_INTR, + MDP_INTF3_INTR, + MDP_INTF4_INTR, + MDP_AD4_0_INTR, + MDP_AD4_1_INTR, + MDP_INTF0_7xxx_INTR, + MDP_INTF1_7xxx_INTR, + MDP_INTF5_7xxx_INTR, + MDP_INTR_MAX, }; +#define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) + struct dpu_hw_intr; /** * Interrupt operations. */ struct dpu_hw_intr_ops { - /** - * irq_idx_lookup - Lookup IRQ index on the HW interrupt type - * Used for all irq related ops - * @intr: HW interrupt handle - * @intr_type: Interrupt type defined in dpu_intr_type - * @instance_idx: HW interrupt block instance - * @return: irq_idx or -EINVAL for lookup fail - */ - int (*irq_idx_lookup)(struct dpu_hw_intr *intr, - enum dpu_intr_type intr_type, - u32 instance_idx); /** * enable_irq - Enable IRQ based on lookup IRQ index @@ -98,7 +45,7 @@ struct dpu_hw_intr_ops { * @irq_idx: Lookup irq index return from irq_idx_lookup * @return: 0 for success, otherwise failure */ - int (*enable_irq)( + int (*enable_irq_locked)( struct dpu_hw_intr *intr, int irq_idx); @@ -108,7 +55,7 @@ struct dpu_hw_intr_ops { * @irq_idx: Lookup irq index return from irq_idx_lookup * @return: 0 for success, otherwise failure */ - int (*disable_irq)( + int (*disable_irq_locked)( struct dpu_hw_intr *intr, int irq_idx); @@ -143,23 +90,6 @@ struct dpu_hw_intr_ops { void *arg); /** - * get_interrupt_statuses - Gets and store value from all interrupt - * status registers that are currently fired. - * @intr: HW interrupt handle - */ - void (*get_interrupt_statuses)( - struct dpu_hw_intr *intr); - - /** - * clear_intr_status_nolock() - clears the HW interrupts without lock - * @intr: HW interrupt handle - * @irq_idx: Lookup irq index return from irq_idx_lookup - */ - void (*clear_intr_status_nolock)( - struct dpu_hw_intr *intr, - int irq_idx); - - /** * get_interrupt_status - Gets HW interrupt status, and clear if set, * based on given lookup IRQ index. * @intr: HW interrupt handle @@ -170,6 +100,22 @@ struct dpu_hw_intr_ops { struct dpu_hw_intr *intr, int irq_idx, bool clear); + + /** + * lock - take the IRQ lock + * @intr: HW interrupt handle + * @return: irq_flags for the taken spinlock + */ + unsigned long (*lock)( + struct dpu_hw_intr *intr); + + /** + * unlock - take the IRQ lock + * @intr: HW interrupt handle + * @irq_flags: the irq_flags returned from lock + */ + void (*unlock)( + struct dpu_hw_intr *intr, unsigned long irq_flags); }; /** @@ -178,19 +124,17 @@ struct dpu_hw_intr_ops { * @ops: function pointer mapping for IRQ handling * @cache_irq_mask: array of IRQ enable masks reg storage created during init * @save_irq_status: array of IRQ status reg storage created during init - * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts + * @total_irqs: total number of irq_idx mapped in the hw_interrupts * @irq_lock: spinlock for accessing IRQ resources - * @obsolete_irq: irq types that are obsolete for a particular target */ struct dpu_hw_intr { struct dpu_hw_blk_reg_map hw; struct dpu_hw_intr_ops ops; u32 *cache_irq_mask; u32 *save_irq_status; - u32 irq_idx_tbl_size; + u32 total_irqs; spinlock_t irq_lock; unsigned long irq_mask; - unsigned long obsolete_irq; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 1599e3f49a4f..116e2b5b1a90 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -299,8 +299,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -327,15 +325,11 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->mdss = m; _setup_intf_ops(&c->ops, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx, &dpu_hw_ops); - return c; } void dpu_hw_intf_destroy(struct dpu_hw_intf *intf) { - if (intf) - dpu_hw_blk_destroy(&intf->base); kfree(intf); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 6ac0b5a0e057..cb6bb7a22c15 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -160,8 +160,6 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, ops->setup_border_color = dpu_hw_lm_setup_border_color; } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -184,14 +182,10 @@ struct dpu_hw_mixer *dpu_hw_lm_init(enum dpu_lm idx, c->cap = cfg; _setup_mixer_ops(m, &c->ops, c->cap->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_LM, idx, &dpu_hw_ops); - return c; } void dpu_hw_lm_destroy(struct dpu_hw_mixer *lm) { - if (lm) - dpu_hw_blk_destroy(&lm->base); kfree(lm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 09a3fb3e89f5..bb9ceadeb0bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -343,7 +343,7 @@ enum dpu_3d_blend_mode { /** struct dpu_format - defines the format configuration which * allows DPU HW to correctly fetch and decode the format - * @base: base msm_format struture containing fourcc code + * @base: base msm_format structure containing fourcc code * @fetch_planes: how the color components are packed in pixel format * @element: element color ordering * @bits: element bit widths diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index 720813e5a8ae..c06d595d5df0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -58,8 +58,6 @@ static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -81,14 +79,10 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, c->caps = cfg; _setup_merge_3d_ops(c, c->caps->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops); - return c; } void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *hw) { - if (hw) - dpu_hw_blk_destroy(&hw->base); kfree(hw); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 245a7a62b5c6..55766c97c4c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -261,8 +261,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c, c->ops.setup_dither = dpu_hw_pp_setup_dither; }; -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -284,14 +282,10 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, c->caps = cfg; _setup_pingpong_ops(c, c->caps->features); - dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); - return c; } void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) { - if (pp) - dpu_hw_blk_destroy(&pp->base); kfree(pp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 845b9ce80e31..89d08a715c16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -126,6 +126,8 @@ struct dpu_hw_pingpong_ops { struct dpu_hw_dither_cfg *cfg); }; +struct dpu_hw_merge_3d; + struct dpu_hw_pingpong { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; @@ -133,7 +135,7 @@ struct dpu_hw_pingpong { /* pingpong */ enum dpu_pingpong idx; const struct dpu_pingpong_cfg *caps; - struct dpu_hw_blk *merge_3d; + struct dpu_hw_merge_3d *merge_3d; /* ops */ struct dpu_hw_pingpong_ops ops; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 34d81aa16041..69eed7932486 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -706,8 +706,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, struct dpu_mdss_cfg *catalog, bool is_virtual_pipe) @@ -735,15 +733,11 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); - dpu_hw_blk_init(&hw_pipe->base, DPU_HW_BLK_SSPP, idx, &dpu_hw_ops); - return hw_pipe; } void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) { - if (ctx) - dpu_hw_blk_destroy(&ctx->base); kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 01b76766a9a8..282e3c6c6d48 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -295,8 +295,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, return ERR_PTR(-EINVAL); } -static struct dpu_hw_blk_ops dpu_hw_ops; - struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -324,15 +322,11 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features); - dpu_hw_blk_init(&mdp->base, DPU_HW_BLK_TOP, idx, &dpu_hw_ops); - return mdp; } void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp) { - if (mdp) - dpu_hw_blk_destroy(&mdp->base); kfree(mdp); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 93bc3575bf53..4fd913522931 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -19,6 +19,7 @@ #include "msm_drv.h" #include "msm_mmu.h" #include "msm_gem.h" +#include "disp/msm_disp_snapshot.h" #include "dpu_kms.h" #include "dpu_core_irq.h" @@ -798,6 +799,51 @@ static void dpu_irq_uninstall(struct msm_kms *kms) dpu_core_irq_uninstall(dpu_kms); } +static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) +{ + int i; + struct dpu_kms *dpu_kms; + struct dpu_mdss_cfg *cat; + struct dpu_hw_mdp *top; + + dpu_kms = to_dpu_kms(kms); + + cat = dpu_kms->catalog; + top = dpu_kms->hw_mdp; + + pm_runtime_get_sync(&dpu_kms->pdev->dev); + + /* dump CTL sub-blocks HW regs info */ + for (i = 0; i < cat->ctl_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, + dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); + + /* dump DSPP sub-blocks HW regs info */ + for (i = 0; i < cat->dspp_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, + dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); + + /* dump INTF sub-blocks HW regs info */ + for (i = 0; i < cat->intf_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, + dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); + + /* dump PP sub-blocks HW regs info */ + for (i = 0; i < cat->pingpong_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, + dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); + + /* dump SSPP sub-blocks HW regs info */ + for (i = 0; i < cat->sspp_count; i++) + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, + dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); + + msm_disp_snapshot_add_block(disp_state, top->hw.length, + dpu_kms->mmio + top->hw.blk_off, "top"); + + pm_runtime_put_sync(&dpu_kms->pdev->dev); +} + static const struct msm_kms_funcs kms_funcs = { .hw_init = dpu_kms_hw_init, .irq_preinstall = dpu_irq_preinstall, @@ -818,6 +864,7 @@ static const struct msm_kms_funcs kms_funcs = { .round_pixclk = dpu_kms_round_pixclk, .destroy = dpu_kms_destroy, .set_encoder_mode = _dpu_kms_set_encoder_mode, + .snapshot = dpu_kms_mdp_snapshot, #ifdef CONFIG_DEBUG_FS .debugfs_init = dpu_kms_debugfs_init, #endif @@ -1089,21 +1136,21 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) if (!dpu_kms) return -ENOMEM; - dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core"); - if (IS_ERR(dpu_kms->opp_table)) - return PTR_ERR(dpu_kms->opp_table); + ret = devm_pm_opp_set_clkname(dev, "core"); + if (ret) + return ret; /* OPP table is optional */ - ret = dev_pm_opp_of_add_table(dev); + ret = devm_pm_opp_of_add_table(dev); if (ret && ret != -ENODEV) { dev_err(dev, "invalid OPP table in device tree\n"); - goto put_clkname; + return ret; } mp = &dpu_kms->mp; ret = msm_dss_parse_clock(pdev, mp); if (ret) { DPU_ERROR("failed to parse clocks, ret=%d\n", ret); - goto err; + return ret; } platform_set_drvdata(pdev, dpu_kms); @@ -1111,7 +1158,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) ret = msm_kms_init(&dpu_kms->base, &kms_funcs); if (ret) { DPU_ERROR("failed to init kms, ret=%d\n", ret); - goto err; + return ret; } dpu_kms->dev = ddev; dpu_kms->pdev = pdev; @@ -1120,11 +1167,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) dpu_kms->rpm_enabled = true; priv->kms = &dpu_kms->base; - return ret; -err: - dev_pm_opp_of_remove_table(dev); -put_clkname: - dev_pm_opp_put_clkname(dpu_kms->opp_table); + return ret; } @@ -1140,9 +1183,6 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data) if (dpu_kms->rpm_enabled) pm_runtime_disable(&pdev->dev); - - dev_pm_opp_of_remove_table(dev); - dev_pm_opp_put_clkname(dpu_kms->opp_table); } static const struct component_ops dpu_ops = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d6717d6672f7..323a6bce9e64 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -82,16 +82,12 @@ struct dpu_irq_callback { * struct dpu_irq: IRQ structure contains callback registration info * @total_irq: total number of irq_idx obtained from HW interrupts mapping * @irq_cb_tbl: array of IRQ callbacks setting - * @enable_counts array of IRQ enable counts - * @cb_lock: callback lock * @debugfs_file: debugfs file for irq statistics */ struct dpu_irq { u32 total_irqs; struct list_head *irq_cb_tbl; - atomic_t *enable_counts; atomic_t *irq_counts; - spinlock_t cb_lock; }; struct dpu_kms { @@ -130,8 +126,6 @@ struct dpu_kms { struct platform_device *pdev; bool rpm_enabled; - struct opp_table *opp_table; - struct dss_module_power mp; /* reference count bandwidth requests, so we know when we can @@ -258,7 +252,7 @@ void dpu_kms_encoder_enable(struct drm_encoder *encoder); /** * dpu_kms_get_clk_rate() - get the clock rate - * @dpu_kms: poiner to dpu_kms structure + * @dpu_kms: pointer to dpu_kms structure * @clock_name: clock name to get the rate * * Return: current clock rate diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index 06b56fec04e0..6b0a7bc87eb7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -225,7 +225,7 @@ int dpu_mdss_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct dpu_mdss *dpu_mdss; struct dss_module_power *mp; - int ret = 0; + int ret; int irq; dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL); @@ -253,8 +253,10 @@ int dpu_mdss_init(struct drm_device *dev) goto irq_domain_error; irq = platform_get_irq(pdev, 0); - if (irq < 0) + if (irq < 0) { + ret = irq; goto irq_error; + } irq_set_chained_handler_and_data(irq, dpu_mdss_irq, dpu_mdss); @@ -263,7 +265,7 @@ int dpu_mdss_init(struct drm_device *dev) pm_runtime_enable(dev->dev); - return ret; + return 0; irq_error: _dpu_mdss_irq_domain_fini(dpu_mdss); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 7a993547eb75..ec4a6f04394a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -25,7 +25,7 @@ #include "dpu_vbif.h" #include "dpu_plane.h" -#define DPU_DEBUG_PLANE(pl, fmt, ...) DPU_DEBUG("plane%d " fmt,\ +#define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\ (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__) #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\ @@ -284,8 +284,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, } } - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", - plane->base.id, pdpu->pipe - SSPP_VIG0, + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", + pdpu->pipe - SSPP_VIG0, (char *)&fmt->base.pixel_format, src_width, total_fl); @@ -354,8 +354,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, (fmt) ? fmt->base.pixel_format : 0, pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", - plane->base.id, + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); @@ -364,7 +363,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, } /** - * _dpu_plane_set_panic_lut - set danger/safe LUT of the given plane + * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane * @plane: Pointer to drm plane * @fb: Pointer to framebuffer associated with the given plane */ @@ -407,8 +406,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, pdpu->pipe_qos_cfg.danger_lut, pdpu->pipe_qos_cfg.safe_lut); - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", - plane->base.id, + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, fmt ? fmt->fetch_mode : -1, @@ -451,8 +449,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pdpu->pipe_qos_cfg.danger_safe_en = false; } - DPU_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", - plane->base.id, + DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", pdpu->pipe - SSPP_VIG0, pdpu->pipe_qos_cfg.danger_safe_en, pdpu->pipe_qos_cfg.vblank_en, @@ -491,7 +488,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, } /** - * _dpu_plane_set_vbif_qos - set vbif QoS for the given plane + * _dpu_plane_set_qos_remap - set vbif QoS for the given plane * @plane: Pointer to drm plane */ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) @@ -507,8 +504,8 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; - DPU_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", - plane->base.id, qos_params.num, + DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", + qos_params.num, qos_params.vbif_idx, qos_params.xin_id, qos_params.is_rt, qos_params.clk_ctrl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index fd2d104f0a91..f9c83d6e427a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -162,7 +162,7 @@ int dpu_rm_init(struct dpu_rm *rm, goto fail; } if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX) - hw->merge_3d = rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]; + hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]); rm->pingpong_blks[pp->id - PINGPONG_0] = &hw->base; } @@ -428,7 +428,7 @@ static int _dpu_rm_reserve_ctls( features = ctl->caps->features; has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features; - DPU_DEBUG("ctl %d caps 0x%lX\n", rm->ctl_blks[j]->id, features); + DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features); if (needs_split_display != has_split_display) continue; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 6714b088970f..37bba57675a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -168,44 +168,41 @@ TRACE_EVENT(dpu_perf_crtc_update, ); DECLARE_EVENT_CLASS(dpu_enc_irq_template, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx), + TP_ARGS(drm_id, intr_idx, irq_idx), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_intr_idx, intr_idx ) - __field( int, hw_idx ) __field( int, irq_idx ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->intr_idx = intr_idx; - __entry->hw_idx = hw_idx; __entry->irq_idx = irq_idx; ), - TP_printk("id=%u, intr=%d, hw=%d, irq=%d", - __entry->drm_id, __entry->intr_idx, __entry->hw_idx, + TP_printk("id=%u, intr=%d, irq=%d", + __entry->drm_id, __entry->intr_idx, __entry->irq_idx) ); DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) + TP_ARGS(drm_id, intr_idx, irq_idx) ); DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx) + TP_ARGS(drm_id, intr_idx, irq_idx) ); TRACE_EVENT(dpu_enc_irq_wait_success, - TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx, + TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt), - TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt), + TP_ARGS(drm_id, intr_idx, irq_idx, pp_idx, atomic_cnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_intr_idx, intr_idx ) - __field( int, hw_idx ) __field( int, irq_idx ) __field( enum dpu_pingpong, pp_idx ) __field( int, atomic_cnt ) @@ -213,13 +210,12 @@ TRACE_EVENT(dpu_enc_irq_wait_success, TP_fast_assign( __entry->drm_id = drm_id; __entry->intr_idx = intr_idx; - __entry->hw_idx = hw_idx; __entry->irq_idx = irq_idx; __entry->pp_idx = pp_idx; __entry->atomic_cnt = atomic_cnt; ), - TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d", - __entry->drm_id, __entry->intr_idx, __entry->hw_idx, + TP_printk("id=%u, intr=%d, irq=%d, pp=%d, atomic_cnt=%d", + __entry->drm_id, __entry->intr_idx, __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt) ); @@ -514,12 +510,12 @@ DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, ); TRACE_EVENT(dpu_enc_wait_event_timeout, - TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time, + TP_PROTO(uint32_t drm_id, int irq_idx, int rc, s64 time, s64 expected_time, int atomic_cnt), - TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt), + TP_ARGS(drm_id, irq_idx, rc, time, expected_time, atomic_cnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) - __field( int32_t, hw_id ) + __field( int, irq_idx ) __field( int, rc ) __field( s64, time ) __field( s64, expected_time ) @@ -527,14 +523,14 @@ TRACE_EVENT(dpu_enc_wait_event_timeout, ), TP_fast_assign( __entry->drm_id = drm_id; - __entry->hw_id = hw_id; + __entry->irq_idx = irq_idx; __entry->rc = rc; __entry->time = time; __entry->expected_time = expected_time; __entry->atomic_cnt = atomic_cnt; ), - TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d", - __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time, + TP_printk("id=%u, irq_idx=%d, rc=%d, time=%lld, expected=%lld cnt=%d", + __entry->drm_id, __entry->irq_idx, __entry->rc, __entry->time, __entry->expected_time, __entry->atomic_cnt) ); @@ -879,29 +875,6 @@ TRACE_EVENT(dpu_pp_connect_ext_te, TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) ); -DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template, - TP_PROTO(int irq_idx, int enable_count), - TP_ARGS(irq_idx, enable_count), - TP_STRUCT__entry( - __field( int, irq_idx ) - __field( int, enable_count ) - ), - TP_fast_assign( - __entry->irq_idx = irq_idx; - __entry->enable_count = enable_count; - ), - TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx, - __entry->enable_count) -); -DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx, - TP_PROTO(int irq_idx, int enable_count), - TP_ARGS(irq_idx, enable_count) -); -DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx, - TP_PROTO(int irq_idx, int enable_count), - TP_ARGS(irq_idx, enable_count) -); - DECLARE_EVENT_CLASS(dpu_core_irq_callback_template, TP_PROTO(int irq_idx, struct dpu_irq_callback *callback), TP_ARGS(irq_idx, callback), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c index 7e08f40e7e6f..21d20373eb8b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c @@ -46,7 +46,7 @@ static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) vbif->idx - VBIF_0, xin_id); } else { rc = 0; - DPU_DEBUG("VBIF %d client %d is halted\n", + DRM_DEBUG_ATOMIC("VBIF %d client %d is halted\n", vbif->idx - VBIF_0, xin_id); } @@ -87,7 +87,7 @@ static void _dpu_vbif_apply_dynamic_ot_limit(struct dpu_hw_vbif *vbif, } } - DPU_DEBUG("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n", + DRM_DEBUG_ATOMIC("vbif:%d xin:%d w:%d h:%d fps:%d pps:%llu ot:%u\n", vbif->idx - VBIF_0, params->xin_id, params->width, params->height, params->frame_rate, pps, *ot_lim); @@ -133,7 +133,7 @@ static u32 _dpu_vbif_get_ot_limit(struct dpu_hw_vbif *vbif, } exit: - DPU_DEBUG("vbif:%d xin:%d ot_lim:%d\n", + DRM_DEBUG_ATOMIC("vbif:%d xin:%d ot_lim:%d\n", vbif->idx - VBIF_0, params->xin_id, ot_lim); return ot_lim; } @@ -163,7 +163,7 @@ void dpu_vbif_set_ot_limit(struct dpu_kms *dpu_kms, } if (!vbif || !mdp) { - DPU_DEBUG("invalid arguments vbif %d mdp %d\n", + DRM_DEBUG_ATOMIC("invalid arguments vbif %d mdp %d\n", vbif != NULL, mdp != NULL); return; } @@ -230,7 +230,7 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, } if (!vbif->ops.set_qos_remap || !mdp->ops.setup_clk_force_ctrl) { - DPU_DEBUG("qos remap not supported\n"); + DRM_DEBUG_ATOMIC("qos remap not supported\n"); return; } @@ -238,14 +238,14 @@ void dpu_vbif_set_qos_remap(struct dpu_kms *dpu_kms, &vbif->cap->qos_nrt_tbl; if (!qos_tbl->npriority_lvl || !qos_tbl->priority_lvl) { - DPU_DEBUG("qos tbl not defined\n"); + DRM_DEBUG_ATOMIC("qos tbl not defined\n"); return; } forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); for (i = 0; i < qos_tbl->npriority_lvl; i++) { - DPU_DEBUG("vbif:%d xin:%d lvl:%d/%d\n", + DRM_DEBUG_ATOMIC("vbif:%d xin:%d lvl:%d/%d\n", params->vbif_idx, params->xin_id, i, qos_tbl->priority_lvl[i]); vbif->ops.set_qos_remap(vbif, params->xin_id, i, diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h index f1d1de578e4c..c82d1bd09359 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h index 4cf0953009f7..0e21cf3f9e2e 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -80,6 +88,10 @@ enum mdp5_pipe { SSPP_CURSOR1 = 12, }; +enum mdp5_format { + DUMMY = 0, +}; + enum mdp5_ctl_mode { MODE_NONE = 0, MODE_WB_0_BLOCK = 1, diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 94ce62a26daf..9741544ffc35 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -95,6 +95,11 @@ static const struct mdp5_cfg_hw msm8x74v1_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 200, + .ib_inefficiency = 120, + .clk_inefficiency = 125 + }, .max_clk = 200000000, }; @@ -177,6 +182,11 @@ static const struct mdp5_cfg_hw msm8x74v2_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 200, + .ib_inefficiency = 120, + .clk_inefficiency = 125 + }, .max_clk = 320000000, }; @@ -272,6 +282,11 @@ static const struct mdp5_cfg_hw apq8084_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 200, + .ib_inefficiency = 120, + .clk_inefficiency = 105 + }, .max_clk = 320000000, }; @@ -339,6 +354,11 @@ static const struct mdp5_cfg_hw msm8x16_config = { [1] = INTF_DSI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 320000000, }; @@ -414,6 +434,11 @@ static const struct mdp5_cfg_hw msm8x36_config = { [2] = INTF_DSI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 366670000, }; @@ -509,6 +534,11 @@ static const struct mdp5_cfg_hw msm8x94_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 100, + .clk_inefficiency = 105 + }, .max_clk = 400000000, }; @@ -617,6 +647,11 @@ static const struct mdp5_cfg_hw msm8x96_config = { [3] = INTF_HDMI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 412500000, }; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h index 1c50d01f15f5..6b03d7899309 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h @@ -76,6 +76,12 @@ struct mdp5_intf_block { u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */ }; +struct mdp5_perf_block { + u32 ab_inefficiency; + u32 ib_inefficiency; + u32 clk_inefficiency; +}; + struct mdp5_cfg_hw { char *name; @@ -93,6 +99,7 @@ struct mdp5_cfg_hw { struct mdp5_sub_block dsc; struct mdp5_sub_block cdm; struct mdp5_intf_block intf; + struct mdp5_perf_block perf; uint32_t max_clk; }; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index f5d71b274079..f482e0911d03 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -291,8 +291,8 @@ static void blend_setup(struct drm_crtc *crtc) plane = pstates[i]->base.plane; blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST); - fg_alpha = pstates[i]->alpha; - bg_alpha = 0xFF - pstates[i]->alpha; + fg_alpha = pstates[i]->base.alpha >> 8; + bg_alpha = 0xFF - fg_alpha; if (!format->alpha_enable && bg_alpha_enabled) mixer_op_mode = 0; @@ -301,7 +301,8 @@ static void blend_setup(struct drm_crtc *crtc) DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha); - if (format->alpha_enable && pstates[i]->premultiplied) { + if (format->alpha_enable && + pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); if (fg_alpha != 0xff) { @@ -312,7 +313,8 @@ static void blend_setup(struct drm_crtc *crtc) } else { blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; } - } else if (format->alpha_enable) { + } else if (format->alpha_enable && + pstates[i]->base.pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); if (fg_alpha != 0xff) { @@ -648,7 +650,7 @@ static int pstate_cmp(const void *a, const void *b) { struct plane_state *pa = (struct plane_state *)a; struct plane_state *pb = (struct plane_state *)b; - return pa->state->zpos - pb->state->zpos; + return pa->state->base.normalized_zpos - pb->state->base.normalized_zpos; } /* is there a helper for this? */ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index 128866742593..ac269a6802df 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -98,11 +98,6 @@ struct mdp5_plane_state { struct mdp5_hw_pipe *hwpipe; struct mdp5_hw_pipe *r_hwpipe; /* right hwpipe */ - /* aligned with property */ - uint8_t premultiplied; - uint8_t zpos; - uint8_t alpha; - /* assigned by crtc blender */ enum mdp_mixer_stage_id stage; }; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index 8c9f2f492178..c6b69afcbac8 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -44,8 +44,9 @@ static void mdp5_plane_destroy(struct drm_plane *plane) kfree(mdp5_plane); } -static void mdp5_plane_install_rotation_property(struct drm_device *dev, - struct drm_plane *plane) +/* helper to install properties which are common to planes and crtcs */ +static void mdp5_plane_install_properties(struct drm_plane *plane, + struct drm_mode_object *obj) { drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, @@ -53,104 +54,12 @@ static void mdp5_plane_install_rotation_property(struct drm_device *dev, DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y); -} - -/* helper to install properties which are common to planes and crtcs */ -static void mdp5_plane_install_properties(struct drm_plane *plane, - struct drm_mode_object *obj) -{ - struct drm_device *dev = plane->dev; - struct msm_drm_private *dev_priv = dev->dev_private; - struct drm_property *prop; - -#define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \ - prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \ - if (!prop) { \ - prop = drm_property_##fnc(dev, 0, #name, \ - ##__VA_ARGS__); \ - if (!prop) { \ - dev_warn(dev->dev, \ - "Create property %s failed\n", \ - #name); \ - return; \ - } \ - dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \ - } \ - drm_object_attach_property(&plane->base, prop, init_val); \ - } while (0) - -#define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \ - INSTALL_PROPERTY(name, NAME, init_val, \ - create_range, min, max) - -#define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \ - INSTALL_PROPERTY(name, NAME, init_val, \ - create_enum, name##_prop_enum_list, \ - ARRAY_SIZE(name##_prop_enum_list)) - - INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1); - - mdp5_plane_install_rotation_property(dev, plane); - -#undef INSTALL_RANGE_PROPERTY -#undef INSTALL_ENUM_PROPERTY -#undef INSTALL_PROPERTY -} - -static int mdp5_plane_atomic_set_property(struct drm_plane *plane, - struct drm_plane_state *state, struct drm_property *property, - uint64_t val) -{ - struct drm_device *dev = plane->dev; - struct mdp5_plane_state *pstate; - struct msm_drm_private *dev_priv = dev->dev_private; - int ret = 0; - - pstate = to_mdp5_plane_state(state); - -#define SET_PROPERTY(name, NAME, type) do { \ - if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ - pstate->name = (type)val; \ - DBG("Set property %s %d", #name, (type)val); \ - goto done; \ - } \ - } while (0) - - SET_PROPERTY(zpos, ZPOS, uint8_t); - - DRM_DEV_ERROR(dev->dev, "Invalid property\n"); - ret = -EINVAL; -done: - return ret; -#undef SET_PROPERTY -} - -static int mdp5_plane_atomic_get_property(struct drm_plane *plane, - const struct drm_plane_state *state, - struct drm_property *property, uint64_t *val) -{ - struct drm_device *dev = plane->dev; - struct mdp5_plane_state *pstate; - struct msm_drm_private *dev_priv = dev->dev_private; - int ret = 0; - - pstate = to_mdp5_plane_state(state); - -#define GET_PROPERTY(name, NAME, type) do { \ - if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \ - *val = pstate->name; \ - DBG("Get property %s %lld", #name, *val); \ - goto done; \ - } \ - } while (0) - - GET_PROPERTY(zpos, ZPOS, uint8_t); - - DRM_DEV_ERROR(dev->dev, "Invalid property\n"); - ret = -EINVAL; -done: - return ret; -#undef SET_PROPERTY + drm_plane_create_alpha_property(plane); + drm_plane_create_blend_mode_property(plane, + BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE)); + drm_plane_create_zpos_property(plane, 1, 1, 255); } static void @@ -166,9 +75,10 @@ mdp5_plane_atomic_print_state(struct drm_printer *p, drm_printf(p, "\tright-hwpipe=%s\n", pstate->r_hwpipe ? pstate->r_hwpipe->name : "(null)"); - drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied); - drm_printf(p, "\tzpos=%u\n", pstate->zpos); - drm_printf(p, "\talpha=%u\n", pstate->alpha); + drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode); + drm_printf(p, "\tzpos=%u\n", pstate->base.zpos); + drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos); + drm_printf(p, "\talpha=%u\n", pstate->base.alpha); drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage)); } @@ -176,24 +86,19 @@ static void mdp5_plane_reset(struct drm_plane *plane) { struct mdp5_plane_state *mdp5_state; - if (plane->state && plane->state->fb) - drm_framebuffer_put(plane->state->fb); + if (plane->state) + __drm_atomic_helper_plane_destroy_state(plane->state); kfree(to_mdp5_plane_state(plane->state)); mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL); - /* assign default blend parameters */ - mdp5_state->alpha = 255; - mdp5_state->premultiplied = 0; - if (plane->type == DRM_PLANE_TYPE_PRIMARY) - mdp5_state->zpos = STAGE_BASE; + mdp5_state->base.zpos = STAGE_BASE; else - mdp5_state->zpos = STAGE0 + drm_plane_index(plane); - - mdp5_state->base.plane = plane; + mdp5_state->base.zpos = STAGE0 + drm_plane_index(plane); + mdp5_state->base.normalized_zpos = mdp5_state->base.zpos; - plane->state = &mdp5_state->base; + __drm_atomic_helper_plane_reset(plane, &mdp5_state->base); } static struct drm_plane_state * @@ -229,8 +134,6 @@ static const struct drm_plane_funcs mdp5_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = mdp5_plane_destroy, - .atomic_set_property = mdp5_plane_atomic_set_property, - .atomic_get_property = mdp5_plane_atomic_get_property, .reset = mdp5_plane_reset, .atomic_duplicate_state = mdp5_plane_duplicate_state, .atomic_destroy_state = mdp5_plane_destroy_state, diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h b/drivers/gpu/drm/msm/disp/mdp_common.xml.h index 4f51bea8fd3f..bb0066a63732 100644 --- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h +++ b/drivers/gpu/drm/msm/disp/mdp_common.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c new file mode 100644 index 000000000000..a4a7cb06bc87 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ + +#include "msm_disp_snapshot.h" + +static ssize_t __maybe_unused disp_devcoredump_read(char *buffer, loff_t offset, + size_t count, void *data, size_t datalen) +{ + struct drm_print_iterator iter; + struct drm_printer p; + struct msm_disp_state *disp_state; + + disp_state = data; + + iter.data = buffer; + iter.offset = 0; + iter.start = offset; + iter.remain = count; + + p = drm_coredump_printer(&iter); + + msm_disp_state_print(disp_state, &p); + + return count - iter.remain; +} + +static void _msm_disp_snapshot_work(struct kthread_work *work) +{ + struct msm_kms *kms = container_of(work, struct msm_kms, dump_work); + struct drm_device *drm_dev = kms->dev; + struct msm_disp_state *disp_state; + struct drm_printer p; + + disp_state = kzalloc(sizeof(struct msm_disp_state), GFP_KERNEL); + if (!disp_state) + return; + + disp_state->dev = drm_dev->dev; + disp_state->drm_dev = drm_dev; + + INIT_LIST_HEAD(&disp_state->blocks); + + /* Serialize dumping here */ + mutex_lock(&kms->dump_mutex); + + msm_disp_snapshot_capture_state(disp_state); + + mutex_unlock(&kms->dump_mutex); + + if (MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE) { + p = drm_info_printer(disp_state->drm_dev->dev); + msm_disp_state_print(disp_state, &p); + } + + /* + * If COREDUMP is disabled, the stub will call the free function. + * If there is a codedump pending for the device, the dev_coredumpm() + * will also free new coredump state. + */ + dev_coredumpm(disp_state->dev, THIS_MODULE, disp_state, 0, GFP_KERNEL, + disp_devcoredump_read, msm_disp_state_free); +} + +void msm_disp_snapshot_state(struct drm_device *drm_dev) +{ + struct msm_drm_private *priv; + struct msm_kms *kms; + + if (!drm_dev) { + DRM_ERROR("invalid params\n"); + return; + } + + priv = drm_dev->dev_private; + kms = priv->kms; + + kthread_queue_work(kms->dump_worker, &kms->dump_work); +} + +int msm_disp_snapshot_init(struct drm_device *drm_dev) +{ + struct msm_drm_private *priv; + struct msm_kms *kms; + + if (!drm_dev) { + DRM_ERROR("invalid params\n"); + return -EINVAL; + } + + priv = drm_dev->dev_private; + kms = priv->kms; + + mutex_init(&kms->dump_mutex); + + kms->dump_worker = kthread_create_worker(0, "%s", "disp_snapshot"); + if (IS_ERR(kms->dump_worker)) + DRM_ERROR("failed to create disp state task\n"); + + kthread_init_work(&kms->dump_work, _msm_disp_snapshot_work); + + return 0; +} + +void msm_disp_snapshot_destroy(struct drm_device *drm_dev) +{ + struct msm_kms *kms; + struct msm_drm_private *priv; + + if (!drm_dev) { + DRM_ERROR("invalid params\n"); + return; + } + + priv = drm_dev->dev_private; + kms = priv->kms; + + if (kms->dump_worker) + kthread_destroy_worker(kms->dump_worker); + + mutex_destroy(&kms->dump_mutex); +} diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h new file mode 100644 index 000000000000..c92a9508c8d3 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#ifndef MSM_DISP_SNAPSHOT_H_ +#define MSM_DISP_SNAPSHOT_H_ + +#include <drm/drm_atomic_helper.h> +#include <drm/drm_device.h> +#include "../../../drm_crtc_internal.h" +#include <drm/drm_print.h> +#include <drm/drm_atomic.h> +#include <linux/debugfs.h> +#include <linux/list.h> +#include <linux/delay.h> +#include <linux/spinlock.h> +#include <linux/ktime.h> +#include <linux/debugfs.h> +#include <linux/uaccess.h> +#include <linux/dma-buf.h> +#include <linux/slab.h> +#include <linux/list_sort.h> +#include <linux/pm.h> +#include <linux/pm_runtime.h> +#include <linux/kthread.h> +#include <linux/devcoredump.h> +#include <stdarg.h> +#include "msm_kms.h" + +#define MSM_DISP_SNAPSHOT_MAX_BLKS 10 + +/* debug option to print the registers in logs */ +#define MSM_DISP_SNAPSHOT_DUMP_IN_CONSOLE 0 + +/* print debug ranges in groups of 4 u32s */ +#define REG_DUMP_ALIGN 16 + +/** + * struct msm_disp_state - structure to store current dpu state + * @dev: device pointer + * @drm_dev: drm device pointer + * @atomic_state: atomic state duplicated at the time of the error + * @timestamp: timestamp at which the coredump was captured + */ +struct msm_disp_state { + struct device *dev; + struct drm_device *drm_dev; + + struct list_head blocks; + + struct drm_atomic_state *atomic_state; + + ktime_t timestamp; +}; + +/** + * struct msm_disp_state_block - structure to store each hardware block state + * @name: name of the block + * @drm_dev: handle to the linked list head + * @size: size of the register space of this hardware block + * @state: array holding the register dump of this hardware block + * @base_addr: starting address of this hardware block's register space + */ +struct msm_disp_state_block { + char name[SZ_128]; + struct list_head node; + unsigned int size; + u32 *state; + void __iomem *base_addr; +}; + +/** + * msm_disp_snapshot_init - initialize display snapshot + * @drm_dev: drm device handle + * + * Returns: 0 or -ERROR + */ +int msm_disp_snapshot_init(struct drm_device *drm_dev); + +/** + * msm_disp_snapshot_destroy - destroy the display snapshot + * @drm_dev: drm device handle + * + * Returns: none + */ +void msm_disp_snapshot_destroy(struct drm_device *drm_dev); + +/** + * msm_disp_snapshot_state - trigger to dump the display snapshot + * @drm_dev: handle to drm device + + * Returns: none + */ +void msm_disp_snapshot_state(struct drm_device *drm_dev); + +/** + * msm_disp_state_print - print out the current dpu state + * @disp_state: handle to drm device + * @p: handle to drm printer + * + * Returns: none + */ +void msm_disp_state_print(struct msm_disp_state *disp_state, struct drm_printer *p); + +/** + * msm_disp_snapshot_capture_state - utility to capture atomic state and hw registers + * @disp_state: handle to msm_disp_state struct + + * Returns: none + */ +void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state); + +/** + * msm_disp_state_free - free the memory after the coredump has been read + * @data: handle to struct msm_disp_state + + * Returns: none + */ +void msm_disp_state_free(void *data); + +/** + * msm_disp_snapshot_add_block - add a hardware block with its register dump + * @disp_state: handle to struct msm_disp_state + * @name: name of the hardware block + * @len: size of the register space of the hardware block + * @base_addr: starting address of the register space of the hardware block + * @fmt: format in which the block names need to be printed + * + * Returns: none + */ +__printf(4, 5) +void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len, + void __iomem *base_addr, const char *fmt, ...); + +#endif /* MSM_DISP_SNAPSHOT_H_ */ diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c new file mode 100644 index 000000000000..cabe15190ec1 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + */ + +#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ + +#include "msm_disp_snapshot.h" + +static void msm_disp_state_dump_regs(u32 **reg, u32 aligned_len, void __iomem *base_addr) +{ + u32 len_padded; + u32 num_rows; + u32 x0, x4, x8, xc; + void __iomem *addr; + u32 *dump_addr = NULL; + void __iomem *end_addr; + int i; + + len_padded = aligned_len * REG_DUMP_ALIGN; + num_rows = aligned_len / REG_DUMP_ALIGN; + + addr = base_addr; + end_addr = base_addr + aligned_len; + + if (!(*reg)) + *reg = kzalloc(len_padded, GFP_KERNEL); + + if (*reg) + dump_addr = *reg; + + for (i = 0; i < num_rows; i++) { + x0 = (addr < end_addr) ? readl_relaxed(addr + 0x0) : 0; + x4 = (addr + 0x4 < end_addr) ? readl_relaxed(addr + 0x4) : 0; + x8 = (addr + 0x8 < end_addr) ? readl_relaxed(addr + 0x8) : 0; + xc = (addr + 0xc < end_addr) ? readl_relaxed(addr + 0xc) : 0; + + if (dump_addr) { + dump_addr[i * 4] = x0; + dump_addr[i * 4 + 1] = x4; + dump_addr[i * 4 + 2] = x8; + dump_addr[i * 4 + 3] = xc; + } + + addr += REG_DUMP_ALIGN; + } +} + +static void msm_disp_state_print_regs(u32 **reg, u32 len, void __iomem *base_addr, + struct drm_printer *p) +{ + int i; + u32 *dump_addr = NULL; + void __iomem *addr; + u32 num_rows; + + addr = base_addr; + num_rows = len / REG_DUMP_ALIGN; + + if (*reg) + dump_addr = *reg; + + for (i = 0; i < num_rows; i++) { + drm_printf(p, "0x%lx : %08x %08x %08x %08x\n", + (unsigned long)(addr - base_addr), + dump_addr[i * 4], dump_addr[i * 4 + 1], + dump_addr[i * 4 + 2], dump_addr[i * 4 + 3]); + addr += REG_DUMP_ALIGN; + } +} + +void msm_disp_state_print(struct msm_disp_state *state, struct drm_printer *p) +{ + struct msm_disp_state_block *block, *tmp; + + if (!p) { + DRM_ERROR("invalid drm printer\n"); + return; + } + + drm_printf(p, "---\n"); + + drm_printf(p, "module: " KBUILD_MODNAME "\n"); + drm_printf(p, "dpu devcoredump\n"); + drm_printf(p, "timestamp %lld\n", ktime_to_ns(state->timestamp)); + + list_for_each_entry_safe(block, tmp, &state->blocks, node) { + drm_printf(p, "====================%s================\n", block->name); + msm_disp_state_print_regs(&block->state, block->size, block->base_addr, p); + } + + drm_printf(p, "===================dpu drm state================\n"); + + if (state->atomic_state) + drm_atomic_print_new_state(state->atomic_state, p); +} + +static void msm_disp_capture_atomic_state(struct msm_disp_state *disp_state) +{ + struct drm_device *ddev; + struct drm_modeset_acquire_ctx ctx; + + disp_state->timestamp = ktime_get(); + + ddev = disp_state->drm_dev; + + drm_modeset_acquire_init(&ctx, 0); + + while (drm_modeset_lock_all_ctx(ddev, &ctx) != 0) + drm_modeset_backoff(&ctx); + + disp_state->atomic_state = drm_atomic_helper_duplicate_state(ddev, + &ctx); + drm_modeset_drop_locks(&ctx); + drm_modeset_acquire_fini(&ctx); +} + +void msm_disp_snapshot_capture_state(struct msm_disp_state *disp_state) +{ + struct msm_drm_private *priv; + struct drm_device *drm_dev; + struct msm_kms *kms; + int i; + + drm_dev = disp_state->drm_dev; + priv = drm_dev->dev_private; + kms = priv->kms; + + if (priv->dp) + msm_dp_snapshot(disp_state, priv->dp); + + for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) { + if (!priv->dsi[i]) + continue; + + msm_dsi_snapshot(disp_state, priv->dsi[i]); + } + + if (kms->funcs->snapshot) + kms->funcs->snapshot(disp_state, kms); + + msm_disp_capture_atomic_state(disp_state); +} + +void msm_disp_state_free(void *data) +{ + struct msm_disp_state *disp_state = data; + struct msm_disp_state_block *block, *tmp; + + if (disp_state->atomic_state) { + drm_atomic_state_put(disp_state->atomic_state); + disp_state->atomic_state = NULL; + } + + list_for_each_entry_safe(block, tmp, &disp_state->blocks, node) { + list_del(&block->node); + kfree(block->state); + kfree(block); + } + + kfree(disp_state); +} + +void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len, + void __iomem *base_addr, const char *fmt, ...) +{ + struct msm_disp_state_block *new_blk; + struct va_format vaf; + va_list va; + + new_blk = kzalloc(sizeof(struct msm_disp_state_block), GFP_KERNEL); + + va_start(va, fmt); + + vaf.fmt = fmt; + vaf.va = &va; + snprintf(new_blk->name, sizeof(new_blk->name), "%pV", &vaf); + + va_end(va); + + INIT_LIST_HEAD(&new_blk->node); + new_blk->size = ALIGN(len, REG_DUMP_ALIGN); + new_blk->base_addr = base_addr; + + msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr); + list_add(&new_blk->node, &disp_state->blocks); +} diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index 7c22bfe0fc7d..4a3293b590b0 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -9,7 +9,15 @@ #include "dp_reg.h" #include "dp_aux.h" -#define DP_AUX_ENUM_STR(x) #x +enum msm_dp_aux_err { + DP_AUX_ERR_NONE, + DP_AUX_ERR_ADDR, + DP_AUX_ERR_TOUT, + DP_AUX_ERR_NACK, + DP_AUX_ERR_DEFER, + DP_AUX_ERR_NACK_DEFER, + DP_AUX_ERR_PHY, +}; struct dp_aux_private { struct device *dev; @@ -18,7 +26,7 @@ struct dp_aux_private { struct mutex mutex; struct completion comp; - u32 aux_error_num; + enum msm_dp_aux_err aux_error_num; u32 retry_cnt; bool cmd_busy; bool native; @@ -27,69 +35,51 @@ struct dp_aux_private { bool no_send_stop; u32 offset; u32 segment; - u32 isr; struct drm_dp_aux dp_aux; }; #define MAX_AUX_RETRIES 5 -static const char *dp_aux_get_error(u32 aux_error) -{ - switch (aux_error) { - case DP_AUX_ERR_NONE: - return DP_AUX_ENUM_STR(DP_AUX_ERR_NONE); - case DP_AUX_ERR_ADDR: - return DP_AUX_ENUM_STR(DP_AUX_ERR_ADDR); - case DP_AUX_ERR_TOUT: - return DP_AUX_ENUM_STR(DP_AUX_ERR_TOUT); - case DP_AUX_ERR_NACK: - return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK); - case DP_AUX_ERR_DEFER: - return DP_AUX_ENUM_STR(DP_AUX_ERR_DEFER); - case DP_AUX_ERR_NACK_DEFER: - return DP_AUX_ENUM_STR(DP_AUX_ERR_NACK_DEFER); - default: - return "unknown"; - } -} - -static u32 dp_aux_write(struct dp_aux_private *aux, +static ssize_t dp_aux_write(struct dp_aux_private *aux, struct drm_dp_aux_msg *msg) { - u32 data[4], reg, len; + u8 data[4]; + u32 reg; + ssize_t len; u8 *msgdata = msg->buffer; int const AUX_CMD_FIFO_LEN = 128; int i = 0; if (aux->read) - len = 4; + len = 0; else - len = msg->size + 4; + len = msg->size; /* * cmd fifo only has depth of 144 bytes * limit buf length to 128 bytes here */ - if (len > AUX_CMD_FIFO_LEN) { + if (len > AUX_CMD_FIFO_LEN - 4) { DRM_ERROR("buf size greater than allowed size of 128 bytes\n"); - return 0; + return -EINVAL; } /* Pack cmd and write to HW */ - data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */ + data[0] = (msg->address >> 16) & 0xf; /* addr[19:16] */ if (aux->read) - data[0] |= BIT(4); /* R/W */ + data[0] |= BIT(4); /* R/W */ - data[1] = (msg->address >> 8) & 0xff; /* addr[15:8] */ - data[2] = msg->address & 0xff; /* addr[7:0] */ - data[3] = (msg->size - 1) & 0xff; /* len[7:0] */ + data[1] = msg->address >> 8; /* addr[15:8] */ + data[2] = msg->address; /* addr[7:0] */ + data[3] = msg->size - 1; /* len[7:0] */ - for (i = 0; i < len; i++) { + for (i = 0; i < len + 4; i++) { reg = (i < 4) ? data[i] : msgdata[i - 4]; + reg <<= DP_AUX_DATA_OFFSET; + reg &= DP_AUX_DATA_MASK; + reg |= DP_AUX_DATA_WRITE; /* index = 0, write */ - reg = (((reg) << DP_AUX_DATA_OFFSET) - & DP_AUX_DATA_MASK) | DP_AUX_DATA_WRITE; if (i == 0) reg |= DP_AUX_DATA_INDEX_WRITE; aux->catalog->aux_data = reg; @@ -117,39 +107,27 @@ static u32 dp_aux_write(struct dp_aux_private *aux, return len; } -static int dp_aux_cmd_fifo_tx(struct dp_aux_private *aux, +static ssize_t dp_aux_cmd_fifo_tx(struct dp_aux_private *aux, struct drm_dp_aux_msg *msg) { - u32 ret, len, timeout; - int aux_timeout_ms = HZ/4; + ssize_t ret; + unsigned long time_left; reinit_completion(&aux->comp); - len = dp_aux_write(aux, msg); - if (len == 0) { - DRM_ERROR("DP AUX write failed\n"); - return -EINVAL; - } + ret = dp_aux_write(aux, msg); + if (ret < 0) + return ret; - timeout = wait_for_completion_timeout(&aux->comp, aux_timeout_ms); - if (!timeout) { - DRM_ERROR("aux %s timeout\n", (aux->read ? "read" : "write")); + time_left = wait_for_completion_timeout(&aux->comp, + msecs_to_jiffies(250)); + if (!time_left) return -ETIMEDOUT; - } - - if (aux->aux_error_num == DP_AUX_ERR_NONE) { - ret = len; - } else { - DRM_ERROR_RATELIMITED("aux err: %s\n", - dp_aux_get_error(aux->aux_error_num)); - - ret = -EINVAL; - } return ret; } -static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux, +static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux, struct drm_dp_aux_msg *msg) { u32 data; @@ -176,15 +154,14 @@ static void dp_aux_cmd_fifo_rx(struct dp_aux_private *aux, actual_i = (data >> DP_AUX_DATA_INDEX_OFFSET) & 0xFF; if (i != actual_i) - DRM_ERROR("Index mismatch: expected %d, found %d\n", - i, actual_i); + break; } + + return i; } -static void dp_aux_native_handler(struct dp_aux_private *aux) +static void dp_aux_native_handler(struct dp_aux_private *aux, u32 isr) { - u32 isr = aux->isr; - if (isr & DP_INTR_AUX_I2C_DONE) aux->aux_error_num = DP_AUX_ERR_NONE; else if (isr & DP_INTR_WRONG_ADDR) @@ -197,14 +174,10 @@ static void dp_aux_native_handler(struct dp_aux_private *aux) aux->aux_error_num = DP_AUX_ERR_PHY; dp_catalog_aux_clear_hw_interrupts(aux->catalog); } - - complete(&aux->comp); } -static void dp_aux_i2c_handler(struct dp_aux_private *aux) +static void dp_aux_i2c_handler(struct dp_aux_private *aux, u32 isr) { - u32 isr = aux->isr; - if (isr & DP_INTR_AUX_I2C_DONE) { if (isr & (DP_INTR_I2C_NACK | DP_INTR_I2C_DEFER)) aux->aux_error_num = DP_AUX_ERR_NACK; @@ -226,8 +199,6 @@ static void dp_aux_i2c_handler(struct dp_aux_private *aux) dp_catalog_aux_clear_hw_interrupts(aux->catalog); } } - - complete(&aux->comp); } static void dp_aux_update_offset_and_segment(struct dp_aux_private *aux, @@ -338,30 +309,29 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, ssize_t ret; int const aux_cmd_native_max = 16; int const aux_cmd_i2c_max = 128; - struct dp_aux_private *aux = container_of(dp_aux, - struct dp_aux_private, dp_aux); + struct dp_aux_private *aux; - mutex_lock(&aux->mutex); + aux = container_of(dp_aux, struct dp_aux_private, dp_aux); aux->native = msg->request & (DP_AUX_NATIVE_WRITE & DP_AUX_NATIVE_READ); /* Ignore address only message */ - if ((msg->size == 0) || (msg->buffer == NULL)) { + if (msg->size == 0 || !msg->buffer) { msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; - ret = msg->size; - goto unlock_exit; + return msg->size; } /* msg sanity check */ - if ((aux->native && (msg->size > aux_cmd_native_max)) || - (msg->size > aux_cmd_i2c_max)) { + if ((aux->native && msg->size > aux_cmd_native_max) || + msg->size > aux_cmd_i2c_max) { DRM_ERROR("%s: invalid msg: size(%zu), request(%x)\n", __func__, msg->size, msg->request); - ret = -EINVAL; - goto unlock_exit; + return -EINVAL; } + mutex_lock(&aux->mutex); + dp_aux_update_offset_and_segment(aux, msg); dp_aux_transfer_helper(aux, msg, true); @@ -377,41 +347,44 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, } ret = dp_aux_cmd_fifo_tx(aux, msg); - if (ret < 0) { if (aux->native) { aux->retry_cnt++; if (!(aux->retry_cnt % MAX_AUX_RETRIES)) dp_catalog_aux_update_cfg(aux->catalog); } - usleep_range(400, 500); /* at least 400us to next try */ - goto unlock_exit; - } - - if (aux->aux_error_num == DP_AUX_ERR_NONE) { - if (aux->read) - dp_aux_cmd_fifo_rx(aux, msg); - - msg->reply = aux->native ? - DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; } else { - /* Reply defer to retry */ - msg->reply = aux->native ? - DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER; + aux->retry_cnt = 0; + switch (aux->aux_error_num) { + case DP_AUX_ERR_NONE: + if (aux->read) + ret = dp_aux_cmd_fifo_rx(aux, msg); + msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK; + break; + case DP_AUX_ERR_DEFER: + msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_DEFER : DP_AUX_I2C_REPLY_DEFER; + break; + case DP_AUX_ERR_PHY: + case DP_AUX_ERR_ADDR: + case DP_AUX_ERR_NACK: + case DP_AUX_ERR_NACK_DEFER: + msg->reply = aux->native ? DP_AUX_NATIVE_REPLY_NACK : DP_AUX_I2C_REPLY_NACK; + break; + case DP_AUX_ERR_TOUT: + ret = -ETIMEDOUT; + break; + } } - /* Return requested size for success or retry */ - ret = msg->size; - aux->retry_cnt = 0; - -unlock_exit: aux->cmd_busy = false; mutex_unlock(&aux->mutex); + return ret; } void dp_aux_isr(struct drm_dp_aux *dp_aux) { + u32 isr; struct dp_aux_private *aux; if (!dp_aux) { @@ -421,15 +394,17 @@ void dp_aux_isr(struct drm_dp_aux *dp_aux) aux = container_of(dp_aux, struct dp_aux_private, dp_aux); - aux->isr = dp_catalog_aux_get_irq(aux->catalog); + isr = dp_catalog_aux_get_irq(aux->catalog); if (!aux->cmd_busy) return; if (aux->native) - dp_aux_native_handler(aux); + dp_aux_native_handler(aux, isr); else - dp_aux_i2c_handler(aux); + dp_aux_i2c_handler(aux, isr); + + complete(&aux->comp); } void dp_aux_reconfig(struct drm_dp_aux *dp_aux) diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index f8b8ba919465..0728cc09c9ec 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -9,14 +9,6 @@ #include "dp_catalog.h" #include <drm/drm_dp_helper.h> -#define DP_AUX_ERR_NONE 0 -#define DP_AUX_ERR_ADDR -1 -#define DP_AUX_ERR_TOUT -2 -#define DP_AUX_ERR_NACK -3 -#define DP_AUX_ERR_DEFER -4 -#define DP_AUX_ERR_NACK_DEFER -5 -#define DP_AUX_ERR_PHY -6 - int dp_aux_register(struct drm_dp_aux *dp_aux); void dp_aux_unregister(struct drm_dp_aux *dp_aux); void dp_aux_isr(struct drm_dp_aux *dp_aux); diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index b1a9b1b98f5f..ca96e3514790 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -62,6 +62,15 @@ struct dp_catalog_private { u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX]; }; +void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state) +{ + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + msm_disp_snapshot_add_block(disp_state, catalog->io->dp_controller.len, + catalog->io->dp_controller.base, "dp_ctrl"); +} + static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { offset += MSM_DP_CONTROLLER_AUX_OFFSET; @@ -193,7 +202,7 @@ int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog) /** * dp_catalog_aux_reset() - reset AUX controller * - * @aux: DP catalog structure + * @dp_catalog: DP catalog structure * * return: void * @@ -292,7 +301,7 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) dump_regs(catalog->io->dp_controller.base + offset, len); } -int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) +u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); @@ -582,10 +591,9 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog) u32 reftimer = dp_read_aux(catalog, REG_DP_DP_HPD_REFTIMER); - /* enable HPD interrupts */ + /* enable HPD plug and unplug interrupts */ dp_catalog_hpd_config_intr(dp_catalog, - DP_DP_HPD_PLUG_INT_MASK | DP_DP_IRQ_HPD_INT_MASK - | DP_DP_HPD_UNPLUG_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); + DP_DP_HPD_PLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK, true); /* Configure REFTIMER and enable it */ reftimer |= DP_DP_HPD_REFTIMER_ENABLE; diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 176a9020a520..6965afa81aad 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -9,6 +9,7 @@ #include <drm/drm_modes.h> #include "dp_parser.h" +#include "disp/msm_disp_snapshot.h" /* interrupts */ #define DP_INTR_HPD BIT(0) @@ -71,6 +72,9 @@ struct dp_catalog { u32 audio_data; }; +/* Debug module */ +void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state); + /* AUX APIs */ u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog); int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog); @@ -80,7 +84,7 @@ int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog); void dp_catalog_aux_reset(struct dp_catalog *dp_catalog); void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog); -int dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); +u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); /* DP Controller APIs */ void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state); @@ -124,7 +128,6 @@ void dp_catalog_audio_get_header(struct dp_catalog *catalog); void dp_catalog_audio_set_header(struct dp_catalog *catalog); void dp_catalog_audio_config_acr(struct dp_catalog *catalog); void dp_catalog_audio_enable(struct dp_catalog *catalog); -void dp_catalog_audio_enable(struct dp_catalog *catalog); void dp_catalog_audio_config_sdp(struct dp_catalog *catalog); void dp_catalog_audio_init(struct dp_catalog *catalog); void dp_catalog_audio_sfe_level(struct dp_catalog *catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 2cebd17a7289..ee221d835fa0 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -77,8 +77,6 @@ struct dp_ctrl_private { struct dp_parser *parser; struct dp_catalog *catalog; - struct opp_table *opp_table; - struct completion idle_comp; struct completion video_comp; }; @@ -1809,6 +1807,63 @@ end: return ret; } +int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; + int ret; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; + + /* set dongle to D3 (power off) mode */ + dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); + + dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); + + if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) { + ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); + if (ret) { + DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); + return ret; + } + } + + ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); + if (ret) { + DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); + return ret; + } + + phy_power_off(phy); + + /* aux channel down, reinit phy */ + phy_exit(phy); + phy_init(phy); + + DRM_DEBUG_DP("DP off link/stream done\n"); + return ret; +} + +void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + struct dp_io *dp_io; + struct phy *phy; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dp_io = &ctrl->parser->io; + phy = dp_io->phy; + + dp_catalog_ctrl_reset(ctrl->catalog); + + phy_exit(phy); + + DRM_DEBUG_DP("DP off phy done\n"); +} + int dp_ctrl_off(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; @@ -1886,20 +1941,17 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, return ERR_PTR(-ENOMEM); } - ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link"); - if (IS_ERR(ctrl->opp_table)) { + ret = devm_pm_opp_set_clkname(dev, "ctrl_link"); + if (ret) { dev_err(dev, "invalid DP OPP table in device tree\n"); - /* caller do PTR_ERR(ctrl->opp_table) */ - return (struct dp_ctrl *)ctrl->opp_table; + /* caller do PTR_ERR(opp_table) */ + return (struct dp_ctrl *)ERR_PTR(ret); } /* OPP table is optional */ - ret = dev_pm_opp_of_add_table(dev); - if (ret) { + ret = devm_pm_opp_of_add_table(dev); + if (ret) dev_err(dev, "failed to add DP OPP table\n"); - dev_pm_opp_put_clkname(ctrl->opp_table); - ctrl->opp_table = NULL; - } init_completion(&ctrl->idle_comp); init_completion(&ctrl->video_comp); @@ -1915,16 +1967,3 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, return &ctrl->dp_ctrl; } - -void dp_ctrl_put(struct dp_ctrl *dp_ctrl) -{ - struct dp_ctrl_private *ctrl; - - ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - - if (ctrl->opp_table) { - dev_pm_opp_of_remove_table(ctrl->dev); - dev_pm_opp_put_clkname(ctrl->opp_table); - ctrl->opp_table = NULL; - } -} diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index a836bd358447..2363a2df9597 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -23,6 +23,8 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset); void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl); +int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl); +void dp_ctrl_off_phy(struct dp_ctrl *dp_ctrl); int dp_ctrl_off(struct dp_ctrl *dp_ctrl); void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl); void dp_ctrl_isr(struct dp_ctrl *dp_ctrl); @@ -31,6 +33,5 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, struct dp_panel *panel, struct drm_dp_aux *aux, struct dp_power *power, struct dp_catalog *catalog, struct dp_parser *parser); -void dp_ctrl_put(struct dp_ctrl *dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 1784e119269b..051c1be1de7e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -208,10 +208,6 @@ static int dp_display_bind(struct device *dev, struct device *master, dp = container_of(g_dp_display, struct dp_display_private, dp_display); - if (!dp) { - DRM_ERROR("DP driver bind failed. Invalid driver data\n"); - return -EINVAL; - } dp->dp_display.drm_dev = drm; priv = drm->dev_private; @@ -252,10 +248,6 @@ static void dp_display_unbind(struct device *dev, struct device *master, dp = container_of(g_dp_display, struct dp_display_private, dp_display); - if (!dp) { - DRM_ERROR("Invalid DP driver data\n"); - return; - } dp_power_client_deinit(dp->power); dp_aux_unregister(dp->aux); @@ -346,6 +338,12 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes; + /* + * set sink to normal operation mode -- D0 + * before dpcd read + */ + dp_link_psm_config(dp->link, &dp->panel->link_info, false); + dp_link_reset_phy_params_vx_px(dp->link); rc = dp_ctrl_on_link(dp->ctrl); if (rc) { @@ -406,19 +404,9 @@ static int dp_display_usbpd_configure_cb(struct device *dev) dp = container_of(g_dp_display, struct dp_display_private, dp_display); - if (!dp) { - DRM_ERROR("no driver data found\n"); - rc = -ENODEV; - goto end; - } dp_display_host_init(dp, false); - /* - * set sink to normal operation mode -- D0 - * before dpcd read - */ - dp_link_psm_config(dp->link, &dp->panel->link_info, false); rc = dp_display_process_hpd_high(dp); end: return rc; @@ -437,11 +425,6 @@ static int dp_display_usbpd_disconnect_cb(struct device *dev) dp = container_of(g_dp_display, struct dp_display_private, dp_display); - if (!dp) { - DRM_ERROR("no driver data found\n"); - rc = -ENODEV; - return rc; - } dp_add_event(dp, EV_USER_NOTIFICATION, false, 0); @@ -502,7 +485,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev) int rc = 0; u32 sink_request; struct dp_display_private *dp; - struct dp_usbpd *hpd; if (!dev) { DRM_ERROR("invalid dev\n"); @@ -511,12 +493,6 @@ static int dp_display_usbpd_attention_cb(struct device *dev) dp = container_of(g_dp_display, struct dp_display_private, dp_display); - if (!dp) { - DRM_ERROR("no driver data found\n"); - return -ENODEV; - } - - hpd = dp->usbpd; /* check for any test request issued by sink */ rc = dp_link_process_request(dp->link); @@ -579,6 +555,10 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) dp_add_event(dp, EV_CONNECT_PENDING_TIMEOUT, 0, tout); } + /* enable HDP irq_hpd/replug interrupt */ + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); + mutex_unlock(&dp->event_mutex); /* uevent will complete connection part */ @@ -628,7 +608,26 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) mutex_lock(&dp->event_mutex); state = dp->hpd_state; - if (state == ST_DISCONNECT_PENDING || state == ST_DISCONNECTED) { + + /* disable irq_hpd/replug interrupts */ + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false); + + /* unplugged, no more irq_hpd handle */ + dp_del_event(dp, EV_IRQ_HPD_INT); + + if (state == ST_DISCONNECTED) { + /* triggered by irq_hdp with sink_count = 0 */ + if (dp->link->sink_count == 0) { + dp_ctrl_off_phy(dp->ctrl); + hpd->hpd_high = 0; + dp->core_initialized = false; + } + mutex_unlock(&dp->event_mutex); + return 0; + } + + if (state == ST_DISCONNECT_PENDING) { mutex_unlock(&dp->event_mutex); return 0; } @@ -642,9 +641,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) dp->hpd_state = ST_DISCONNECT_PENDING; - /* disable HPD plug interrupt until disconnect is done */ - dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK - | DP_DP_IRQ_HPD_INT_MASK, false); + /* disable HPD plug interrupts */ + dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); hpd->hpd_high = 0; @@ -660,8 +658,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) /* signal the disconnect event early to ensure proper teardown */ dp_display_handle_plugged_change(g_dp_display, false); - dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK | - DP_DP_IRQ_HPD_INT_MASK, true); + /* enable HDP plug interrupt to prepare for next plugin */ + dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, true); /* uevent will complete disconnection part */ mutex_unlock(&dp->event_mutex); @@ -692,7 +690,7 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) /* irq_hpd can happen at either connected or disconnected state */ state = dp->hpd_state; - if (state == ST_DISPLAY_OFF) { + if (state == ST_DISPLAY_OFF || state == ST_SUSPENDED) { mutex_unlock(&dp->event_mutex); return 0; } @@ -724,7 +722,6 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) static void dp_display_deinit_sub_modules(struct dp_display_private *dp) { dp_debug_put(dp->debug); - dp_ctrl_put(dp->ctrl); dp_panel_put(dp->panel); dp_aux_put(dp->aux); dp_audio_put(dp->audio); @@ -818,13 +815,11 @@ static int dp_init_sub_modules(struct dp_display_private *dp) rc = PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc = %d\n", rc); dp->audio = NULL; - goto error_audio; + goto error_ctrl; } return rc; -error_audio: - dp_ctrl_put(dp->ctrl); error_ctrl: dp_panel_put(dp->panel); error_link: @@ -910,9 +905,13 @@ static int dp_display_disable(struct dp_display_private *dp, u32 data) dp_display->audio_enabled = false; - dp_ctrl_off(dp->ctrl); - - dp->core_initialized = false; + /* triggered by irq_hpd with sink_count = 0 */ + if (dp->link->sink_count == 0) { + dp_ctrl_off_link_stream(dp->ctrl); + } else { + dp_ctrl_off(dp->ctrl); + dp->core_initialized = false; + } dp_display->power_on = false; @@ -1012,6 +1011,33 @@ int dp_display_get_test_bpp(struct msm_dp *dp) dp_display->link->test_video.test_bit_depth); } +void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) +{ + struct dp_display_private *dp_display; + struct drm_device *drm; + + dp_display = container_of(dp, struct dp_display_private, dp_display); + drm = dp->drm_dev; + + /* + * if we are reading registers we need the link clocks to be on + * however till DP cable is connected this will not happen as we + * do not know the resolution to power up with. Hence check the + * power_on status before dumping DP registers to avoid crash due + * to unclocked access + */ + mutex_lock(&dp_display->event_mutex); + + if (!dp->power_on) { + mutex_unlock(&dp_display->event_mutex); + return; + } + + dp_catalog_snapshot(dp_display->catalog, disp_state); + + mutex_unlock(&dp_display->event_mutex); +} + static void dp_display_config_hpd(struct dp_display_private *dp) { @@ -1300,8 +1326,13 @@ static int dp_pm_suspend(struct device *dev) mutex_lock(&dp->event_mutex); - if (dp->core_initialized == true) + if (dp->core_initialized == true) { + /* mainlink enabled */ + if (dp_power_clk_status(dp->power, DP_CTRL_PM)) + dp_ctrl_off_link_stream(dp->ctrl); + dp_display_host_deinit(dp); + } dp->hpd_state = ST_SUSPENDED; diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 5173c89eedf7..8b47cdabb67e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -8,6 +8,7 @@ #include "dp_panel.h" #include <sound/hdmi-codec.h> +#include "disp/msm_disp_snapshot.h" struct msm_dp { struct drm_device *drm_dev; diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c index be986da78c4a..1195044a7a3b 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -364,7 +364,7 @@ static int dp_link_parse_timing_params3(struct dp_link_private *link, } /** - * dp_parse_video_pattern_params() - parses video pattern parameters from DPCD + * dp_link_parse_video_pattern_params() - parses video pattern parameters from DPCD * @link: Display Port Driver data * * Returns 0 if it successfully parses the video link pattern and the link @@ -563,7 +563,7 @@ static int dp_link_parse_link_training_params(struct dp_link_private *link) } /** - * dp_parse_phy_test_params() - parses the phy link parameters + * dp_link_parse_phy_test_params() - parses the phy link parameters * @link: Display Port Driver data * * Parses the DPCD (Byte 0x248) for the DP PHY link pattern that is being @@ -843,10 +843,8 @@ bool dp_link_send_edid_checksum(struct dp_link *dp_link, u8 checksum) return ret == 1; } -static int dp_link_parse_vx_px(struct dp_link_private *link) +static void dp_link_parse_vx_px(struct dp_link_private *link) { - int ret = 0; - DRM_DEBUG_DP("vx: 0=%d, 1=%d, 2=%d, 3=%d\n", drm_dp_get_adjust_request_voltage(link->link_status, 0), drm_dp_get_adjust_request_voltage(link->link_status, 1), @@ -876,8 +874,6 @@ static int dp_link_parse_vx_px(struct dp_link_private *link) DRM_DEBUG_DP("Requested: v_level = 0x%x, p_level = 0x%x\n", link->dp_link.phy_params.v_level, link->dp_link.phy_params.p_level); - - return ret; } /** @@ -891,8 +887,6 @@ static int dp_link_parse_vx_px(struct dp_link_private *link) static int dp_link_process_phy_test_pattern_request( struct dp_link_private *link) { - int ret = 0; - if (!(link->request.test_requested & DP_TEST_LINK_PHY_TEST_PATTERN)) { DRM_DEBUG_DP("no phy test\n"); return -EINVAL; @@ -918,12 +912,9 @@ static int dp_link_process_phy_test_pattern_request( link->dp_link.link_params.rate = drm_dp_bw_code_to_link_rate(link->request.test_link_rate); - ret = dp_link_parse_vx_px(link); - - if (ret) - DRM_ERROR("parse_vx_px failed. ret=%d\n", ret); + dp_link_parse_vx_px(link); - return ret; + return 0; } static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) @@ -961,7 +952,7 @@ static int dp_link_process_link_status_update(struct dp_link_private *link) } /** - * dp_link_process_downstream_port_status_change() - process port status changes + * dp_link_process_ds_port_status_change() - process port status changes * @link: Display Port Driver data * * This function will handle downstream port updates that are initiated by diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 9cc816663668..440b32753430 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -141,7 +141,6 @@ static int dp_panel_update_modes(struct drm_connector *connector, return rc; } rc = drm_add_edid_modes(connector, edid); - DRM_DEBUG_DP("%s -", __func__); return rc; } @@ -351,7 +350,6 @@ void dp_panel_dump_regs(struct dp_panel *dp_panel) int dp_panel_timing_cfg(struct dp_panel *dp_panel) { - int rc = 0; u32 data, total_ver, total_hor; struct dp_catalog *catalog; struct dp_panel_private *panel; @@ -404,7 +402,7 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel) dp_catalog_panel_timing_cfg(catalog); panel->panel_on = true; - return rc; + return 0; } int dp_panel_init_panel_info(struct dp_panel *dp_panel) diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h index 7d0327bbc0d5..e3f959ffae12 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.h +++ b/drivers/gpu/drm/msm/dp/dp_power.h @@ -88,7 +88,7 @@ int dp_power_client_init(struct dp_power *power); * return: 0 for success, error for failure. * * This API will de-initialize the DisplayPort's clocks and regulator - * modueles. + * modules. */ void dp_power_client_deinit(struct dp_power *power); @@ -100,7 +100,7 @@ void dp_power_client_deinit(struct dp_power *power); * * This API will configure the DisplayPort's power module and provides * methods to be called by the client to configure the power related - * modueles. + * modules. */ struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser); diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 627048851d99..75afc12a7b25 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -266,3 +266,9 @@ fail: return ret; } +void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) +{ + msm_dsi_host_snapshot(disp_state, msm_dsi->host); + msm_dsi_phy_snapshot(disp_state, msm_dsi->phy); +} + diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 7abfeab08165..9b8e9b07eced 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -15,6 +15,7 @@ #include <drm/drm_panel.h> #include "msm_drv.h" +#include "disp/msm_disp_snapshot.h" #define DSI_0 0 #define DSI_1 1 @@ -146,7 +147,7 @@ int dsi_clk_init_v2(struct msm_dsi_host *msm_host); int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi); - +void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); /* dsi phy */ struct msm_dsi_phy; struct msm_dsi_phy_shared_timings { @@ -173,6 +174,7 @@ int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy, struct clk **byte_clk_provider, struct clk **pixel_clk_provider); void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy); int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy); +void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy); #endif /* __DSI_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 50eb4d1b8fdd..eadbcc78fd72 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -621,1693 +629,7 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; } -#define REG_DSI_PHY_PLL_CTRL_0 0x00000200 -#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 - -#define REG_DSI_PHY_PLL_CTRL_1 0x00000204 - -#define REG_DSI_PHY_PLL_CTRL_2 0x00000208 - -#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c - -#define REG_DSI_PHY_PLL_CTRL_4 0x00000210 - -#define REG_DSI_PHY_PLL_CTRL_5 0x00000214 - -#define REG_DSI_PHY_PLL_CTRL_6 0x00000218 - -#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c - -#define REG_DSI_PHY_PLL_CTRL_8 0x00000220 - -#define REG_DSI_PHY_PLL_CTRL_9 0x00000224 - -#define REG_DSI_PHY_PLL_CTRL_10 0x00000228 - -#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c - -#define REG_DSI_PHY_PLL_CTRL_12 0x00000230 - -#define REG_DSI_PHY_PLL_CTRL_13 0x00000234 - -#define REG_DSI_PHY_PLL_CTRL_14 0x00000238 - -#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c - -#define REG_DSI_PHY_PLL_CTRL_16 0x00000240 - -#define REG_DSI_PHY_PLL_CTRL_17 0x00000244 - -#define REG_DSI_PHY_PLL_CTRL_18 0x00000248 - -#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c - -#define REG_DSI_PHY_PLL_CTRL_20 0x00000250 - -#define REG_DSI_PHY_PLL_STATUS 0x00000280 -#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001 - -#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258 - -#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c - -#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c - -#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c - -#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288 - -#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c - -#define REG_DSI_8x60_PHY_CTRL_0 0x00000290 - -#define REG_DSI_8x60_PHY_CTRL_1 0x00000294 - -#define REG_DSI_8x60_PHY_CTRL_2 0x00000298 - -#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c - -#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0 - -#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4 - -#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8 - -#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac - -#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc - -#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0 - -#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4 - -#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8 - -#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc - -#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0 - -#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4 - -#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc -#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } - -#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 - -#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 - -#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 - -#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c - -#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 - -#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 -#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 -#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 -#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 -#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 -#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 -#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c -#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 -#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 -#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; -} - -#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c -#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 - -#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 - -#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 - -#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c - -#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 - -#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 - -#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 - -#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c - -#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 - -#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 - -#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 -#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 -#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c - -#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 - -#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 -#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 - -static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } - -static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } - -#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 - -#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 - -#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 - -#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c - -#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 - -#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 - -#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 - -#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c - -#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 - -#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 -#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 -#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 -#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c -#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 - -#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 -#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 -#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 -#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c -#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 -#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 -#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; -} - -#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c -#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -#define REG_DSI_28nm_PHY_CTRL_0 0x00000170 - -#define REG_DSI_28nm_PHY_CTRL_1 0x00000174 - -#define REG_DSI_28nm_PHY_CTRL_2 0x00000178 - -#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c - -#define REG_DSI_28nm_PHY_CTRL_4 0x00000180 - -#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 - -#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 - -#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 - -#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 - -#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc - -#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 - -#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 - -#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 - -#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 -#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 - -#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 - -#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 - -#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 - -#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 -#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 - -#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 - -#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 - -#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c - -#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 -#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 - -#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 - -#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 - -#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c - -#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 -#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 - -#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 - -#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 - -#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c - -#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 - -#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 -#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f -#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; -} -#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c -#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f -#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; -} -#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 -#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; -} - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 -#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff -#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; -} - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 -#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff -#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 -static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) -{ - return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; -} - -#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 - -#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 - -#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c - -#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 - -#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 - -#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 -#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 - -#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 - -#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 - -#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 - -#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 - -#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac - -#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 - -#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 - -#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 - -#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc - -#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 -#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc - -#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 - -#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 - -static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } - -static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } - -#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 - -#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 - -#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 - -#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c - -#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 - -#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 - -#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 - -#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c - -#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 - -#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 -#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 -#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 -#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c -#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 - -#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 -#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 -#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 -#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c -#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 -#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 -#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; -} - -#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c -#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -#define REG_DSI_20nm_PHY_CTRL_0 0x00000170 - -#define REG_DSI_20nm_PHY_CTRL_1 0x00000174 - -#define REG_DSI_20nm_PHY_CTRL_2 0x00000178 - -#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c - -#define REG_DSI_20nm_PHY_CTRL_4 0x00000180 - -#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 - -#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 - -#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 - -#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 - -#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc - -#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 - -#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 - -#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 - -#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 -#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 - -#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 - -#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 - -#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0 -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4 -static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK; -} -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0 -#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4 -static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK; -} - -#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014 -#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001 - -#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018 -#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004 - -#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c - -#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020 - -#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024 - -#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028 - -#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c - -#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c - -#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040 - -#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044 - -#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048 -#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001 - -#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c -#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f -#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } -#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0 -#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6 -static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } -#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001 - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007 -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK; -} -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 -#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007 -#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } -#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff -#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 -static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) -{ - return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK; -} - -static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } - -static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } - -#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000 - -#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004 - -#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010 - -#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c - -#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038 - -#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c - -#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040 - -#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044 - -#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048 - -#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c - -#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c - -#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058 - -#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c - -#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070 - -#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074 - -#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078 - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080 - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084 - -#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088 - -#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c - -#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090 - -#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094 - -#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098 - -#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c - -#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0 - -#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4 - -#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8 - -#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac - -#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4 - -#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8 - -#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc - -#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0 - -#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4 - -#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc - -#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8 - -#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0 - -#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4 - -#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8 - -#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc - -#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100 - -#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104 - -#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010 - -#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 - -#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018 - -#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c - -#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020 - -#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024 - -#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028 - -#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c - -#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030 - -#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034 - -#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4 - -#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4 - -#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8 - -#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec - -#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4 - -#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8 - -static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } - -static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } - -#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 - -#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 - -#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 - -#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c - -#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020 - -#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024 - -#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c - -#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030 - -#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054 - -#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064 - -#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c - -#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080 - -#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094 - -#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4 - -#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8 - -#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4 - -#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc - -#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0 - -#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 - -#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8 - -#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c - -#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110 - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114 - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118 - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c - -#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120 - -#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c - -#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140 - -#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144 - -#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c - -#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154 - -#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c - -#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164 - -#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180 - -#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184 - -#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c - -#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008 - -#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c - -#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010 - -#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014 - -#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018 - -#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c - -#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020 - -#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024 - -#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028 - -#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c - -#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030 - -#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034 - -#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038 - -#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c - -#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8 - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac - -#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4 - -#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8 - -#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec - -#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0 - -#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4 - -#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8 - -#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc - -#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100 - -#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104 - -#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108 - -#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c - -#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110 - -#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114 - -#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128 - -#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140 - -#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148 - -#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c - -static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } - -static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 - -#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008 - -#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018 - -#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c - -#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020 - -#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 - -#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028 - -#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c - -#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030 - -#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034 - -#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038 - -#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c - -#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040 - -#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088 - -#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c - -#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090 - -#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094 - -#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098 - -#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c - -#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0 - -#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4 - -#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8 - -#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac - -#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0 - -#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4 - -#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8 - -#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc - -#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0 - -#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4 - -#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8 - -#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8 - -#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc - -#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec - -#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8 - -#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc - -#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118 - -#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138 - -#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140 - -#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148 - -#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c - -#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150 - -#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c - -#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160 - -#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164 - -#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168 - -#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c - -#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170 - -#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174 - -#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178 - -#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c - -#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180 - -#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184 - -#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188 - -#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194 - -#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198 - -#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c - -#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0 - -#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4 - -#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8 - -#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac - -#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0 - -#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4 - -#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8 - -#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc - -#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0 - -#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4 - -#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8 - -#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc - -#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0 - -#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4 - -#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8 - -#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc - -#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0 - -#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4 - -#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8 - -#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec - -#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0 - -#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4 - -#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208 - -#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c - -#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210 - -#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214 - -#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218 - -#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c - -#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220 - -#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224 - -#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228 - -#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c - -#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230 - -#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234 - -#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238 - -#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c - -#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240 - -#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244 - -#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248 - -#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c - -#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250 - -#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258 - -#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c +#define REG_DSI_CPHY_MODE_CTRL 0x000002d4 -#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 #endif /* DSI_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8a10e4343281..ed504fe5074f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -102,6 +102,7 @@ struct msm_dsi_host { int id; void __iomem *ctrl_base; + phys_addr_t ctrl_size; struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; struct clk *bus_clks[DSI_BUS_CLK_MAX]; @@ -113,8 +114,6 @@ struct msm_dsi_host { struct clk *pixel_clk_src; struct clk *byte_intf_clk; - struct opp_table *opp_table; - u32 byte_clk_rate; u32 pixel_clk_rate; u32 esc_clk_rate; @@ -1092,7 +1091,7 @@ int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) uint64_t iova; u8 *data; - data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED, + data = msm_gem_kernel_new(dev, size, MSM_BO_WC, priv->kms->aspace, &msm_host->tx_gem_obj, &iova); @@ -1839,7 +1838,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } - msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); + msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size); if (IS_ERR(msm_host->ctrl_base)) { pr_err("%s: unable to map Dsi ctrl base\n", __func__); ret = PTR_ERR(msm_host->ctrl_base); @@ -1884,14 +1883,13 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } - msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte"); - if (IS_ERR(msm_host->opp_table)) - return PTR_ERR(msm_host->opp_table); + ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); + if (ret) + return ret; /* OPP table is optional */ - ret = dev_pm_opp_of_add_table(&pdev->dev); + ret = devm_pm_opp_of_add_table(&pdev->dev); if (ret && ret != -ENODEV) { dev_err(&pdev->dev, "invalid OPP table in device tree\n"); - dev_pm_opp_put_clkname(msm_host->opp_table); return ret; } @@ -1930,8 +1928,6 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) mutex_destroy(&msm_host->cmd_mutex); mutex_destroy(&msm_host->dev_mutex); - dev_pm_opp_of_remove_table(&msm_host->pdev->dev); - dev_pm_opp_put_clkname(msm_host->opp_table); pm_runtime_disable(&msm_host->pdev->dev); } @@ -2487,3 +2483,15 @@ struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) return of_drm_find_bridge(msm_host->device_node); } + +void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + pm_runtime_get_sync(&msm_host->pdev->dev); + + msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, + msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); + + pm_runtime_put_sync(&msm_host->pdev->dev); +} diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index cd016576e8c5..4ebfedc4a9ac 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -373,14 +373,14 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) if (!msm_dsi_device_connected(msm_dsi)) return; - ret = dsi_mgr_phy_enable(id, phy_shared_timings); - if (ret) - goto phy_en_fail; - /* Do nothing with the host if it is slave-DSI in case of dual DSI */ if (is_dual_dsi && !IS_MASTER_DSI_LINK(id)) return; + ret = dsi_mgr_phy_enable(id, phy_shared_timings); + if (ret) + goto phy_en_fail; + ret = msm_dsi_host_power_on(host, &phy_shared_timings[id], is_dual_dsi); if (ret) { pr_err("%s: power on host %d failed, %d\n", __func__, id, ret); @@ -817,8 +817,8 @@ int msm_dsi_manager_register(struct msm_dsi *msm_dsi) ret = dsi_mgr_setup_components(id); if (ret) { - pr_err("%s: failed to register mipi dsi host for DSI %d\n", - __func__, id); + pr_err("%s: failed to register mipi dsi host for DSI %d: %d\n", + __func__, id, ret); goto fail; } diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h new file mode 100644 index 000000000000..8872d77027dd --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h @@ -0,0 +1,228 @@ +#ifndef DSI_PHY_10NM_XML +#define DSI_PHY_10NM_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000 + +#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004 + +#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008 + +#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c + +#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010 + +#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014 + +#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018 + +#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c + +#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020 + +#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024 + +#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028 + +#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c + +#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030 + +#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034 + +#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 + +#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098 + +#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c + +#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0 + +#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4 + +#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4 + +#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8 + +#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec + +#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4 + +#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8 + +static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } + +static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } + +#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 + +#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 + +#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 + +#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c + +#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020 + +#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024 + +#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c + +#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030 + +#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054 + +#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064 + +#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c + +#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080 + +#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094 + +#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4 + +#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8 + +#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4 + +#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc + +#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0 + +#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4 + +#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8 + +#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c + +#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110 + +#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114 + +#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118 + +#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c + +#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120 + +#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c + +#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140 + +#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144 + +#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c + +#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154 + +#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c + +#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164 + +#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180 + +#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184 + +#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c + +#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0 + + +#endif /* DSI_PHY_10NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h new file mode 100644 index 000000000000..0d9a5ccfb808 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h @@ -0,0 +1,310 @@ +#ifndef DSI_PHY_14NM_XML +#define DSI_PHY_14NM_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000 + +#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004 + +#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008 + +#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c + +#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 +#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0 +#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4 +static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK; +} +#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0 +#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4 +static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK; +} + +#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014 +#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001 + +#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018 +#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004 + +#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c + +#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020 + +#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024 + +#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028 + +#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c + +#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030 + +#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034 + +#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038 + +#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c + +#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040 + +#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044 + +#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048 +#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001 + +#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c +#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f +#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } +#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0 +#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6 +static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } +#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001 + +static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff +#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff +#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff +#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff +#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff +#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007 +#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK; +} +#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 +#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007 +#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } +#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff +#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 +static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) +{ + return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK; +} + +static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } + +static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } + +#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000 + +#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004 + +#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010 + +#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c + +#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028 + +#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c + +#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030 + +#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034 + +#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038 + +#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c + +#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040 + +#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044 + +#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048 + +#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c + +#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c + +#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058 + +#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c + +#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070 + +#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074 + +#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078 + +#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c + +#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080 + +#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084 + +#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088 + +#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c + +#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090 + +#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094 + +#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098 + +#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c + +#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0 + +#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4 + +#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8 + +#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac + +#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4 + +#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8 + +#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc + +#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0 + +#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4 + +#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc + +#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8 + +#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0 + +#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4 + +#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8 + +#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc + +#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100 + +#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104 + +#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108 + + +#endif /* DSI_PHY_14NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h new file mode 100644 index 000000000000..15c7a5852c7a --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h @@ -0,0 +1,238 @@ +#ifndef DSI_PHY_20NM_XML +#define DSI_PHY_20NM_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } + +static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } + +#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100 + +#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104 + +#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108 + +#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c + +#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110 + +#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114 + +#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118 + +#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c + +#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120 + +#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140 +#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144 +#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148 +#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c +#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 + +#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150 +#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154 +#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158 +#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c +#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160 +#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164 +#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 +#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; +} +#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 +#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168 +#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 +#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK; +} + +#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c +#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff +#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 +static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) +{ + return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; +} + +#define REG_DSI_20nm_PHY_CTRL_0 0x00000170 + +#define REG_DSI_20nm_PHY_CTRL_1 0x00000174 + +#define REG_DSI_20nm_PHY_CTRL_2 0x00000178 + +#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c + +#define REG_DSI_20nm_PHY_CTRL_4 0x00000180 + +#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184 + +#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188 + +#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4 + +#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8 + +#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc + +#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0 + +#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4 + +#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8 + +#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4 +#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 + +#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc + +#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000 + +#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004 + +#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008 + +#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c + +#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010 + +#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014 + +#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 + + +#endif /* DSI_PHY_20NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h new file mode 100644 index 000000000000..5148f4d5b182 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h @@ -0,0 +1,385 @@ +#ifndef DSI_PHY_28NM_XML +#define DSI_PHY_28NM_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } + +#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 + +#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 + +#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 + +#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c + +#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 + +#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 + +#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 + +#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c + +#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 + +#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 +#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 +#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 +#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c +#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 + +#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 +#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 +#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 +#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c +#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 +#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; +} +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 +#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 +#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c +#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; +} + +#define REG_DSI_28nm_PHY_CTRL_0 0x00000170 + +#define REG_DSI_28nm_PHY_CTRL_1 0x00000174 + +#define REG_DSI_28nm_PHY_CTRL_2 0x00000178 + +#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c + +#define REG_DSI_28nm_PHY_CTRL_4 0x00000180 + +#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 + +#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 + +#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 + +#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 + +#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc + +#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 + +#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 + +#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 + +#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 +#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001 + +#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 + +#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 + +#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000 +#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004 + +#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008 + +#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c + +#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010 +#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002 + +#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 + +#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018 + +#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c + +#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004 +#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 + +#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028 + +#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c + +#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030 + +#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038 +#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f +#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK; +} +#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040 + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c +#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f +#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK; +} +#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040 +#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK; +} + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040 +#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff +#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK; +} + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044 +#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff +#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK; +} + +#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054 + +#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058 + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060 + +#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064 + +#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 +#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 + +#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098 + +#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0 + +#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4 + +#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8 + +#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac + +#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0 + +#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4 + +#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8 + +#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc + +#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0 +#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001 + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4 + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8 + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc + +#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0 + +#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4 + + +#endif /* DSI_PHY_28NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h new file mode 100644 index 000000000000..446fe9ffc9c4 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h @@ -0,0 +1,287 @@ +#ifndef DSI_PHY_28NM_8960_XML +#define DSI_PHY_28NM_8960_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } + +#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 + +#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 + +#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 + +#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c + +#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 + +#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 +#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 +#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 +#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 +#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 +#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 +#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c +#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 +#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; +} +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 +#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 +#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c +#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; +} + +#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 + +#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 + +#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 + +#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c + +#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 + +#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 + +#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c + +#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 + +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 + +#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 +#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 +#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c + +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 + +#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 +#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 + + +#endif /* DSI_PHY_28NM_8960_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h new file mode 100644 index 000000000000..404c890a29f1 --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_5nm.xml.h @@ -0,0 +1,480 @@ +#ifndef DSI_PHY_5NM_XML +#define DSI_PHY_5NM_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define REG_DSI_5nm_PHY_CMN_REVISION_ID0 0x00000000 + +#define REG_DSI_5nm_PHY_CMN_REVISION_ID1 0x00000004 + +#define REG_DSI_5nm_PHY_CMN_REVISION_ID2 0x00000008 + +#define REG_DSI_5nm_PHY_CMN_REVISION_ID3 0x0000000c + +#define REG_DSI_5nm_PHY_CMN_CLK_CFG0 0x00000010 + +#define REG_DSI_5nm_PHY_CMN_CLK_CFG1 0x00000014 + +#define REG_DSI_5nm_PHY_CMN_GLBL_CTRL 0x00000018 + +#define REG_DSI_5nm_PHY_CMN_RBUF_CTRL 0x0000001c + +#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_0 0x00000020 + +#define REG_DSI_5nm_PHY_CMN_CTRL_0 0x00000024 + +#define REG_DSI_5nm_PHY_CMN_CTRL_1 0x00000028 + +#define REG_DSI_5nm_PHY_CMN_CTRL_2 0x0000002c + +#define REG_DSI_5nm_PHY_CMN_CTRL_3 0x00000030 + +#define REG_DSI_5nm_PHY_CMN_LANE_CFG0 0x00000034 + +#define REG_DSI_5nm_PHY_CMN_LANE_CFG1 0x00000038 + +#define REG_DSI_5nm_PHY_CMN_PLL_CNTRL 0x0000003c + +#define REG_DSI_5nm_PHY_CMN_DPHY_SOT 0x00000040 + +#define REG_DSI_5nm_PHY_CMN_LANE_CTRL0 0x000000a0 + +#define REG_DSI_5nm_PHY_CMN_LANE_CTRL1 0x000000a4 + +#define REG_DSI_5nm_PHY_CMN_LANE_CTRL2 0x000000a8 + +#define REG_DSI_5nm_PHY_CMN_LANE_CTRL3 0x000000ac + +#define REG_DSI_5nm_PHY_CMN_LANE_CTRL4 0x000000b0 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_0 0x000000b4 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_1 0x000000b8 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_2 0x000000bc + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_4 0x000000c4 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_6 0x000000cc + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_7 0x000000d0 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_8 0x000000d4 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_9 0x000000d8 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_10 0x000000dc + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_11 0x000000e0 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_12 0x000000e4 + +#define REG_DSI_5nm_PHY_CMN_TIMING_CTRL_13 0x000000e8 + +#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec + +#define REG_DSI_5nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0 + +#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4 + +#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8 + +#define REG_DSI_5nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc + +#define REG_DSI_5nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100 + +#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104 + +#define REG_DSI_5nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108 + +#define REG_DSI_5nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c + +#define REG_DSI_5nm_PHY_CMN_VREG_CTRL_1 0x00000110 + +#define REG_DSI_5nm_PHY_CMN_CTRL_4 0x00000114 + +#define REG_DSI_5nm_PHY_CMN_PHY_STATUS 0x00000140 + +#define REG_DSI_5nm_PHY_CMN_LANE_STATUS0 0x00000148 + +#define REG_DSI_5nm_PHY_CMN_LANE_STATUS1 0x0000014c + +static inline uint32_t REG_DSI_5nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } + +static inline uint32_t REG_DSI_5nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 + +#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008 + +#define REG_DSI_5nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014 + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018 + +#define REG_DSI_5nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c + +#define REG_DSI_5nm_PHY_PLL_DSM_DIVIDER 0x00000020 + +#define REG_DSI_5nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 + +#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES 0x00000028 + +#define REG_DSI_5nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c + +#define REG_DSI_5nm_PHY_PLL_CMODE 0x00000030 + +#define REG_DSI_5nm_PHY_PLL_PSM_CTRL 0x00000034 + +#define REG_DSI_5nm_PHY_PLL_RSM_CTRL 0x00000038 + +#define REG_DSI_5nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c + +#define REG_DSI_5nm_PHY_PLL_PLL_CNTRL 0x00000040 + +#define REG_DSI_5nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MIN 0x00000054 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_MAX 0x00000058 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_IFILT 0x00000060 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074 + +#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078 + +#define REG_DSI_5nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c + +#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080 + +#define REG_DSI_5nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084 + +#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088 + +#define REG_DSI_5nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c + +#define REG_DSI_5nm_PHY_PLL_PFILT 0x00000090 + +#define REG_DSI_5nm_PHY_PLL_IFILT 0x00000094 + +#define REG_DSI_5nm_PHY_PLL_PLL_GAIN 0x00000098 + +#define REG_DSI_5nm_PHY_PLL_ICODE_LOW 0x0000009c + +#define REG_DSI_5nm_PHY_PLL_ICODE_HIGH 0x000000a0 + +#define REG_DSI_5nm_PHY_PLL_LOCKDET 0x000000a4 + +#define REG_DSI_5nm_PHY_PLL_OUTDIV 0x000000a8 + +#define REG_DSI_5nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac + +#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0 + +#define REG_DSI_5nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4 + +#define REG_DSI_5nm_PHY_PLL_CORE_OVERRIDE 0x000000b8 + +#define REG_DSI_5nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc + +#define REG_DSI_5nm_PHY_PLL_RATE_CHANGE 0x000000c0 + +#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4 + +#define REG_DSI_5nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8 + +#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8 + +#define REG_DSI_5nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc + +#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec + +#define REG_DSI_5nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8 + +#define REG_DSI_5nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc + +#define REG_DSI_5nm_PHY_PLL_MASH_CONTROL 0x00000100 + +#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104 + +#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108 + +#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c + +#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110 + +#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114 + +#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118 + +#define REG_DSI_5nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c + +#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120 + +#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124 + +#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128 + +#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c + +#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130 + +#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134 + +#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138 + +#define REG_DSI_5nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c + +#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140 + +#define REG_DSI_5nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144 + +#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148 + +#define REG_DSI_5nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c + +#define REG_DSI_5nm_PHY_PLL_SSC_CONTROL 0x00000150 + +#define REG_DSI_5nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154 + +#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158 + +#define REG_DSI_5nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c + +#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160 + +#define REG_DSI_5nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164 + +#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168 + +#define REG_DSI_5nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c + +#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170 + +#define REG_DSI_5nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174 + +#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178 + +#define REG_DSI_5nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c + +#define REG_DSI_5nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180 + +#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184 + +#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188 + +#define REG_DSI_5nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c + +#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190 + +#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194 + +#define REG_DSI_5nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198 + +#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c + +#define REG_DSI_5nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0 + +#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4 + +#define REG_DSI_5nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8 + +#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac + +#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0 + +#define REG_DSI_5nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4 + +#define REG_DSI_5nm_PHY_PLL_BAND_SEL_CAL 0x000001b8 + +#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc + +#define REG_DSI_5nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0 + +#define REG_DSI_5nm_PHY_PLL_FD_OUT_LOW 0x000001c4 + +#define REG_DSI_5nm_PHY_PLL_FD_OUT_HIGH 0x000001c8 + +#define REG_DSI_5nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc + +#define REG_DSI_5nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0 + +#define REG_DSI_5nm_PHY_PLL_FLL_CONFIG 0x000001d4 + +#define REG_DSI_5nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8 + +#define REG_DSI_5nm_PHY_PLL_FLL_CODE0 0x000001dc + +#define REG_DSI_5nm_PHY_PLL_FLL_CODE1 0x000001e0 + +#define REG_DSI_5nm_PHY_PLL_FLL_GAIN0 0x000001e4 + +#define REG_DSI_5nm_PHY_PLL_FLL_GAIN1 0x000001e8 + +#define REG_DSI_5nm_PHY_PLL_SW_RESET 0x000001ec + +#define REG_DSI_5nm_PHY_PLL_FAST_PWRUP 0x000001f0 + +#define REG_DSI_5nm_PHY_PLL_LOCKTIME0 0x000001f4 + +#define REG_DSI_5nm_PHY_PLL_LOCKTIME1 0x000001f8 + +#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc + +#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS0 0x00000200 + +#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS1 0x00000204 + +#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS2 0x00000208 + +#define REG_DSI_5nm_PHY_PLL_DEBUG_BUS3 0x0000020c + +#define REG_DSI_5nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210 + +#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG 0x00000214 + +#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218 + +#define REG_DSI_5nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c + +#define REG_DSI_5nm_PHY_PLL_RESET_SM_STATUS 0x00000220 + +#define REG_DSI_5nm_PHY_PLL_TDC_OFFSET 0x00000224 + +#define REG_DSI_5nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228 + +#define REG_DSI_5nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c + +#define REG_DSI_5nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230 + +#define REG_DSI_5nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234 + +#define REG_DSI_5nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238 + +#define REG_DSI_5nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c + +#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_1 0x00000240 + +#define REG_DSI_5nm_PHY_PLL_VCO_CONFIG_2 0x00000244 + +#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248 + +#define REG_DSI_5nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c + +#define REG_DSI_5nm_PHY_PLL_CMODE_1 0x00000250 + +#define REG_DSI_5nm_PHY_PLL_CMODE_2 0x00000254 + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258 + +#define REG_DSI_5nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c + +#define REG_DSI_5nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 + + +#endif /* DSI_PHY_5NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h new file mode 100644 index 000000000000..782f6b332baf --- /dev/null +++ b/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h @@ -0,0 +1,482 @@ +#ifndef DSI_PHY_7NM_XML +#define DSI_PHY_7NM_XML + +/* Autogenerated file, DO NOT EDIT manually! + +This file was generated by the rules-ng-ng headergen tool in this git repository: +http://github.com/freedreno/envytools/ +git clone https://github.com/freedreno/envytools.git + +The rules-ng-ng source files this header was generated from are: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: +- Rob Clark <robdclark@gmail.com> (robclark) +- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + + +#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000 + +#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004 + +#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008 + +#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c + +#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010 + +#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014 + +#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018 + +#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c + +#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020 + +#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024 + +#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028 + +#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c + +#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030 + +#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034 + +#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038 + +#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c + +#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040 + +#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0 + +#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4 + +#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8 + +#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac + +#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4 + +#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8 + +#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec + +#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0 + +#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4 + +#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8 + +#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc + +#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100 + +#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104 + +#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108 + +#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c + +#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110 + +#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114 + +#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128 + +#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140 + +#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148 + +#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c + +static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; } + +static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000 + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004 + +#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008 + +#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010 + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014 + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018 + +#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c + +#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020 + +#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024 + +#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028 + +#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c + +#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030 + +#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034 + +#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038 + +#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c + +#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040 + +#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074 + +#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078 + +#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c + +#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080 + +#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084 + +#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088 + +#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c + +#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090 + +#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094 + +#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098 + +#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c + +#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0 + +#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4 + +#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8 + +#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac + +#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0 + +#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4 + +#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8 + +#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc + +#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0 + +#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4 + +#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8 + +#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8 + +#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc + +#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec + +#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8 + +#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc + +#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100 + +#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104 + +#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108 + +#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c + +#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110 + +#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114 + +#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118 + +#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c + +#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120 + +#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124 + +#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128 + +#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c + +#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130 + +#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134 + +#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138 + +#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c + +#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140 + +#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144 + +#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148 + +#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c + +#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150 + +#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154 + +#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158 + +#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c + +#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160 + +#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164 + +#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168 + +#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c + +#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170 + +#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174 + +#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178 + +#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c + +#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180 + +#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184 + +#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188 + +#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c + +#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190 + +#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194 + +#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198 + +#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c + +#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0 + +#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4 + +#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8 + +#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac + +#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0 + +#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4 + +#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8 + +#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc + +#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0 + +#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4 + +#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8 + +#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc + +#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0 + +#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4 + +#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8 + +#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc + +#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0 + +#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4 + +#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8 + +#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec + +#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0 + +#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4 + +#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8 + +#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc + +#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200 + +#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204 + +#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208 + +#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c + +#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210 + +#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214 + +#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218 + +#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c + +#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220 + +#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224 + +#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228 + +#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c + +#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230 + +#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234 + +#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238 + +#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c + +#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240 + +#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244 + +#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248 + +#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c + +#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250 + +#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254 + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258 + +#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c + +#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260 + + +#endif /* DSI_PHY_7NM_XML */ diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h index 4e8660c3eb08..fbb6a7a6b940 100644 --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index ff7f2ec42030..6ca6bfd4809b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -658,14 +658,14 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) phy->regulator_ldo_mode = of_property_read_bool(dev->of_node, "qcom,dsi-phy-regulator-ldo-mode"); - phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY"); + phy->base = msm_ioremap_size(pdev, "dsi_phy", "DSI_PHY", &phy->base_size); if (IS_ERR(phy->base)) { DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__); ret = -ENOMEM; goto fail; } - phy->pll_base = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); + phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", "DSI_PLL", &phy->pll_size); if (IS_ERR(phy->pll_base)) { DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__); ret = -ENOMEM; @@ -673,7 +673,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) } if (phy->cfg->has_phy_lane) { - phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE"); + phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", "DSI_PHY_LANE", &phy->lane_size); if (IS_ERR(phy->lane_base)) { DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__); ret = -ENOMEM; @@ -682,7 +682,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) } if (phy->cfg->has_phy_regulator) { - phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG"); + phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", "DSI_PHY_REG", &phy->reg_size); if (IS_ERR(phy->reg_base)) { DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__); ret = -ENOMEM; @@ -868,3 +868,26 @@ int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy) return 0; } + +void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy) +{ + msm_disp_snapshot_add_block(disp_state, + phy->base_size, phy->base, + "dsi%d_phy", phy->id); + + /* Do not try accessing PLL registers if it is switched off */ + if (phy->pll_on) + msm_disp_snapshot_add_block(disp_state, + phy->pll_size, phy->pll_base, + "dsi%d_pll", phy->id); + + if (phy->lane_base) + msm_disp_snapshot_add_block(disp_state, + phy->lane_size, phy->lane_base, + "dsi%d_lane", phy->id); + + if (phy->reg_base) + msm_disp_snapshot_add_block(disp_state, + phy->reg_size, phy->reg_base, + "dsi%d_reg", phy->id); +} diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 94a77ac364d3..5b0feef87127 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -85,6 +85,10 @@ struct msm_dsi_phy { void __iomem *pll_base; void __iomem *reg_base; void __iomem *lane_base; + phys_addr_t base_size; + phys_addr_t pll_size; + phys_addr_t reg_size; + phys_addr_t lane_size; int id; struct clk *ahb_clk; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 657778889d35..e46b10fc793a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -9,6 +9,7 @@ #include "dsi_phy.h" #include "dsi.xml.h" +#include "dsi_phy_10nm.xml.h" /* * DSI PLL 10nm - clock diagram (eg: DSI0): diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 65d68eb9e3cb..a34cf151c517 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -9,6 +9,7 @@ #include "dsi_phy.h" #include "dsi.xml.h" +#include "dsi_phy_14nm.xml.h" #define PHY_14NM_CKLN_IDX 4 diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index e96d789aea18..ee7c418a1c29 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -5,6 +5,7 @@ #include "dsi_phy.h" #include "dsi.xml.h" +#include "dsi_phy_20nm.xml.h" static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy, struct msm_dsi_dphy_timing *timing) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 3304acda2165..2da673a2add6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -8,6 +8,7 @@ #include "dsi_phy.h" #include "dsi.xml.h" +#include "dsi_phy_28nm.xml.h" /* * DSI PLL 28nm - clock diagram (eg: DSI0): diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c index 86e40a0d41a3..aaa37456f4ee 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -8,6 +8,7 @@ #include "dsi_phy.h" #include "dsi.xml.h" +#include "dsi_phy_28nm_8960.xml.h" /* * DSI PLL 28nm (8960/A family) - clock diagram (eg: DSI1): diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 6f96fbac8282..7c23d4c47338 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -9,6 +9,7 @@ #include "dsi_phy.h" #include "dsi.xml.h" +#include "dsi_phy_7nm.xml.h" /* * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram @@ -973,7 +974,11 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = { .restore_pll_state = dsi_7nm_pll_restore_state, }, .min_pll_rate = 600000000UL, - .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX, +#ifdef CONFIG_64BIT + .max_pll_rate = 5000000000UL, +#else + .max_pll_rate = ULONG_MAX, +#endif .io_start = { 0xae94400, 0xae96400 }, .num_dsi_phy = 2, .quirks = DSI_PHY_7NM_QUIRK_V4_1, diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h index a3849220fc6a..1f5e9e9f9803 100644 --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h +++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h index 7aed6cf27790..7907e0f5988f 100644 --- a/drivers/gpu/drm/msm/edp/edp.xml.h +++ b/drivers/gpu/drm/msm/edp/edp.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h index 72c95b60b829..a1cede6cfd02 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h index 85be1b1f19a4..4bf34cea1c89 100644 --- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h +++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h @@ -8,19 +8,27 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) - -Copyright (C) 2013-2020 by the following authors: +- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44) + +Copyright (C) 2013-2021 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_debugfs.c index d611cc8e54a4..09d2d279c30a 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -108,6 +108,31 @@ static const struct file_operations msm_gpu_fops = { .release = msm_gpu_release, }; +static unsigned long last_shrink_freed; + +static int +shrink_get(void *data, u64 *val) +{ + *val = last_shrink_freed; + + return 0; +} + +static int +shrink_set(void *data, u64 val) +{ + struct drm_device *dev = data; + + last_shrink_freed = msm_gem_shrinker_shrink(dev, val); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(shrink_fops, + shrink_get, shrink_set, + "0x%08llx\n"); + + static int msm_gem_show(struct drm_device *dev, struct seq_file *m) { struct msm_drm_private *priv = dev->dev_private; @@ -226,6 +251,12 @@ void msm_debugfs_init(struct drm_minor *minor) debugfs_create_file("gpu", S_IRUSR, minor->debugfs_root, dev, &msm_gpu_fops); + debugfs_create_u32("hangcheck_period_ms", 0600, minor->debugfs_root, + &priv->hangcheck_period); + + debugfs_create_file("shrink", S_IRWXU, minor->debugfs_root, + dev, &shrink_fops); + if (priv->kms && priv->kms->funcs->debugfs_init) priv->kms->funcs->debugfs_init(priv->kms, minor); } diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index fe7d17cd35ec..9b8fa2ad0d84 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <robdclark@gmail.com> */ @@ -19,6 +19,7 @@ #include <drm/drm_of.h> #include <drm/drm_vblank.h> +#include "disp/msm_disp_snapshot.h" #include "msm_drv.h" #include "msm_debugfs.h" #include "msm_fence.h" @@ -40,9 +41,10 @@ * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl * - 1.6.0 - Syncobj support * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count + * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) */ #define MSM_VERSION_MAJOR 1 -#define MSM_VERSION_MINOR 7 +#define MSM_VERSION_MINOR 8 #define MSM_VERSION_PATCHLEVEL 0 static const struct drm_mode_config_funcs mode_config_funcs = { @@ -123,7 +125,7 @@ struct clk *msm_clk_get(struct platform_device *pdev, const char *name) } static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, - const char *dbgname, bool quiet) + const char *dbgname, bool quiet, phys_addr_t *psize) { struct resource *res; unsigned long size; @@ -152,19 +154,28 @@ static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name if (reglog) printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); + if (psize) + *psize = size; + return ptr; } void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, const char *dbgname) { - return _msm_ioremap(pdev, name, dbgname, false); + return _msm_ioremap(pdev, name, dbgname, false, NULL); } void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, const char *dbgname) { - return _msm_ioremap(pdev, name, dbgname, true); + return _msm_ioremap(pdev, name, dbgname, true, NULL); +} + +void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, + const char *dbgname, phys_addr_t *psize) +{ + return _msm_ioremap(pdev, name, dbgname, false, psize); } void msm_writel(u32 data, void __iomem *addr) @@ -278,6 +289,8 @@ static int msm_drm_uninit(struct device *dev) msm_fbdev_free(ddev); #endif + msm_disp_snapshot_destroy(ddev); + drm_mode_config_cleanup(ddev); pm_runtime_get_sync(dev); @@ -446,6 +459,7 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) mdss = priv->mdss; priv->wq = alloc_ordered_workqueue("msm", 0); + priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; INIT_LIST_HEAD(&priv->objects); mutex_init(&priv->obj_lock); @@ -523,6 +537,7 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) priv->event_thread[i].worker = kthread_create_worker(0, "crtc_event:%d", priv->event_thread[i].crtc_id); if (IS_ERR(priv->event_thread[i].worker)) { + ret = PTR_ERR(priv->event_thread[i].worker); DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); goto err_msm_uninit; } @@ -550,6 +565,10 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) if (ret) goto err_msm_uninit; + ret = msm_disp_snapshot_init(ddev); + if (ret) + DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); + drm_mode_config_reset(ddev); #ifdef CONFIG_DRM_FBDEV_EMULATION @@ -688,7 +707,7 @@ int msm_crtc_enable_vblank(struct drm_crtc *crtc) struct msm_kms *kms = priv->kms; if (!kms) return -ENXIO; - DBG("dev=%p, crtc=%u", dev, pipe); + drm_dbg_vbl(dev, "crtc=%u", pipe); return vblank_ctrl_queue_work(priv, pipe, true); } @@ -700,7 +719,7 @@ void msm_crtc_disable_vblank(struct drm_crtc *crtc) struct msm_kms *kms = priv->kms; if (!kms) return; - DBG("dev=%p, crtc=%u", dev, pipe); + drm_dbg_vbl(dev, "crtc=%u", pipe); vblank_ctrl_queue_work(priv, pipe, false); } diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 2668941df529..1a48a709ffb3 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -43,6 +43,7 @@ struct msm_gem_submit; struct msm_fence_context; struct msm_gem_address_space; struct msm_gem_vma; +struct msm_disp_state; #define MAX_CRTCS 8 #define MAX_PLANES 20 @@ -167,6 +168,7 @@ struct msm_drm_private { struct msm_file_private *lastctx; /* gpu is only set on open(), but we need this info earlier */ bool is_a2xx; + bool has_cached_coherent; struct drm_fb_helper *fbdev; @@ -242,6 +244,9 @@ struct msm_drm_private { struct shrinker shrinker; struct drm_atomic_state *pm_state; + + /* For hang detection, in ms */ + unsigned int hangcheck_period; }; struct msm_format { @@ -294,6 +299,10 @@ bool msm_use_mmu(struct drm_device *dev); int msm_ioctl_gem_submit(struct drm_device *dev, void *data, struct drm_file *file); +#ifdef CONFIG_DEBUG_FS +unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); +#endif + void msm_gem_shrinker_init(struct drm_device *dev); void msm_gem_shrinker_cleanup(struct drm_device *dev); @@ -340,6 +349,8 @@ void __init msm_dsi_register(void); void __exit msm_dsi_unregister(void); int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, struct drm_encoder *encoder); +void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); + #else static inline void __init msm_dsi_register(void) { @@ -353,6 +364,10 @@ static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, { return -EINVAL; } +static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) +{ +} + #endif #ifdef CONFIG_DRM_MSM_DP @@ -367,6 +382,7 @@ void msm_dp_display_mode_set(struct msm_dp *dp, struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode); void msm_dp_irq_postinstall(struct msm_dp *dp_display); +void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); @@ -410,6 +426,10 @@ static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) { } +static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) +{ +} + static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor) { @@ -448,6 +468,8 @@ struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, const char *name); void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, const char *dbgname); +void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, + const char *dbgname, phys_addr_t *size); void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, const char *dbgname); void msm_writel(u32 data, void __iomem *addr); @@ -502,7 +524,7 @@ static inline int align_pitch(int width, int bpp) /* for the generated headers: */ #define INVALID_IDX(idx) ({BUG(); 0;}) #define fui(x) ({BUG(); 0;}) -#define util_float_to_half(x) ({BUG(); 0;}) +#define _mesa_float_to_half(x) ({BUG(); 0;}) #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c index 91c0e493aed5..4d34df5354e0 100644 --- a/drivers/gpu/drm/msm/msm_fb.c +++ b/drivers/gpu/drm/msm/msm_fb.c @@ -61,7 +61,7 @@ int msm_framebuffer_prepare(struct drm_framebuffer *fb, for (i = 0; i < n; i++) { ret = msm_gem_get_and_pin_iova(fb->obj[i], aspace, &iova); - DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret); + drm_dbg_state(fb->dev, "FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret); if (ret) return ret; } @@ -140,8 +140,8 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, const struct msm_format *format; int ret, i, n; - DBG("create framebuffer: dev=%p, mode_cmd=%p (%dx%d@%4.4s)", - dev, mode_cmd, mode_cmd->width, mode_cmd->height, + drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%4.4s)", + mode_cmd, mode_cmd->width, mode_cmd->height, (char *)&mode_cmd->pixel_format); n = info->num_planes; @@ -194,7 +194,7 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, goto fail; } - DBG("create: FB ID: %d (%p)", fb->base.id, fb); + drm_dbg_state(dev, "create: FB ID: %d (%p)", fb->base.id, fb); return fb; diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index b61f5466e522..141178754231 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -211,6 +211,13 @@ void msm_gem_put_pages(struct drm_gem_object *obj) msm_gem_unlock(obj); } +static pgprot_t msm_gem_pgprot(struct msm_gem_object *msm_obj, pgprot_t prot) +{ + if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) + return pgprot_writecombine(prot); + return prot; +} + int msm_gem_mmap_obj(struct drm_gem_object *obj, struct vm_area_struct *vma) { @@ -218,22 +225,7 @@ int msm_gem_mmap_obj(struct drm_gem_object *obj, vma->vm_flags &= ~VM_PFNMAP; vma->vm_flags |= VM_MIXEDMAP; - - if (msm_obj->flags & MSM_BO_WC) { - vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); - } else if (msm_obj->flags & MSM_BO_UNCACHED) { - vma->vm_page_prot = pgprot_noncached(vm_get_page_prot(vma->vm_flags)); - } else { - /* - * Shunt off cached objs to shmem file so they have their own - * address_space (so unmap_mapping_range does what we want, - * in particular in the case of mmap'd dmabufs) - */ - vma->vm_pgoff = 0; - vma_set_file(vma, obj->filp); - - vma->vm_page_prot = vm_get_page_prot(vma->vm_flags); - } + vma->vm_page_prot = msm_gem_pgprot(msm_obj, vm_get_page_prot(vma->vm_flags)); return 0; } @@ -372,7 +364,7 @@ static void del_vma(struct msm_gem_vma *vma) kfree(vma); } -/** +/* * If close is true, this also closes the VMA (releasing the allocated * iova range) in addition to removing the iommu mapping. In the eviction * case (!close), we keep the iova allocated, but only remove the iommu @@ -451,6 +443,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, if (msm_obj->flags & MSM_BO_MAP_PRIV) prot |= IOMMU_PRIV; + if (msm_obj->flags & MSM_BO_CACHED_COHERENT) + prot |= IOMMU_CACHE; + GEM_WARN_ON(!msm_gem_is_locked(obj)); if (GEM_WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) @@ -653,7 +648,7 @@ static void *get_vaddr(struct drm_gem_object *obj, unsigned madv) goto fail; } msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT, - VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + VM_MAP, msm_gem_pgprot(msm_obj, PAGE_KERNEL)); if (msm_obj->vaddr == NULL) { ret = -ENOMEM; goto fail; @@ -773,7 +768,7 @@ void msm_gem_purge(struct drm_gem_object *obj) 0, (loff_t)-1); } -/** +/* * Unpin the backing pages and make them available to be swapped out. */ void msm_gem_evict(struct drm_gem_object *obj) @@ -1163,6 +1158,7 @@ static int msm_gem_new_impl(struct drm_device *dev, uint32_t size, uint32_t flags, struct drm_gem_object **obj) { + struct msm_drm_private *priv = dev->dev_private; struct msm_gem_object *msm_obj; switch (flags & MSM_BO_CACHE_MASK) { @@ -1170,6 +1166,10 @@ static int msm_gem_new_impl(struct drm_device *dev, case MSM_BO_CACHED: case MSM_BO_WC: break; + case MSM_BO_CACHED_COHERENT: + if (priv->has_cached_coherent) + break; + /* fallthrough */ default: DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n", (flags & MSM_BO_CACHE_MASK)); diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 03e2cc2a2ce1..405f8411e395 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -328,6 +328,7 @@ struct msm_gem_submit { struct dma_fence *fence; struct msm_gpu_submitqueue *queue; struct pid *pid; /* submitting process */ + bool fault_dumped; /* Limit devcoredump dumping to one per submit */ bool valid; /* true if no cmdstream patching needed */ bool in_rb; /* "sudo" mode, copy cmds into RB */ struct msm_ringbuffer *ring; diff --git a/drivers/gpu/drm/msm/msm_gem_shrinker.c b/drivers/gpu/drm/msm/msm_gem_shrinker.c index 1187ecf9d647..0f1b29ee04a9 100644 --- a/drivers/gpu/drm/msm/msm_gem_shrinker.c +++ b/drivers/gpu/drm/msm/msm_gem_shrinker.c @@ -145,6 +145,24 @@ msm_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) return (freed > 0) ? freed : SHRINK_STOP; } +#ifdef CONFIG_DEBUG_FS +unsigned long +msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan) +{ + struct msm_drm_private *priv = dev->dev_private; + struct shrink_control sc = { + .nr_to_scan = nr_to_scan, + }; + int ret; + + fs_reclaim_acquire(GFP_KERNEL); + ret = msm_gem_shrinker_scan(&priv->shrinker, &sc); + fs_reclaim_release(GFP_KERNEL); + + return ret; +} +#endif + /* since we don't know any better, lets bail after a few * and if necessary the shrinker will be invoked again. * Seems better than unmapping *everything* diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 5480852bdeda..44f84bfd0c0e 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -50,6 +50,7 @@ static struct msm_gem_submit *submit_create(struct drm_device *dev, submit->cmd = (void *)&submit->bos[nr_bos]; submit->queue = queue; submit->ring = gpu->rb[queue->prio]; + submit->fault_dumped = false; /* initially, until copy_from_user() and bo lookup succeeds: */ submit->nr_bos = 0; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 9dd1c58430ab..0ebf7bc6ad09 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -387,6 +387,7 @@ static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, /* Fill in the additional crash state information */ state->comm = kstrdup(comm, GFP_KERNEL); state->cmd = kstrdup(cmd, GFP_KERNEL); + state->fault_info = gpu->fault_info; if (submit) { int i, nr = 0; @@ -559,10 +560,57 @@ static void recover_worker(struct kthread_work *work) msm_gpu_retire(gpu); } +static void fault_worker(struct kthread_work *work) +{ + struct msm_gpu *gpu = container_of(work, struct msm_gpu, fault_work); + struct drm_device *dev = gpu->dev; + struct msm_gem_submit *submit; + struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); + char *comm = NULL, *cmd = NULL; + + mutex_lock(&dev->struct_mutex); + + submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); + if (submit && submit->fault_dumped) + goto resume_smmu; + + if (submit) { + struct task_struct *task; + + task = get_pid_task(submit->pid, PIDTYPE_PID); + if (task) { + comm = kstrdup(task->comm, GFP_KERNEL); + cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); + put_task_struct(task); + } + + /* + * When we get GPU iova faults, we can get 1000s of them, + * but we really only want to log the first one. + */ + submit->fault_dumped = true; + } + + /* Record the crash state */ + pm_runtime_get_sync(&gpu->pdev->dev); + msm_gpu_crashstate_capture(gpu, submit, comm, cmd); + pm_runtime_put_sync(&gpu->pdev->dev); + + kfree(cmd); + kfree(comm); + +resume_smmu: + memset(&gpu->fault_info, 0, sizeof(gpu->fault_info)); + gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); + + mutex_unlock(&dev->struct_mutex); +} + static void hangcheck_timer_reset(struct msm_gpu *gpu) { + struct msm_drm_private *priv = gpu->dev->dev_private; mod_timer(&gpu->hangcheck_timer, - round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES)); + round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period))); } static void hangcheck_handler(struct timer_list *t) @@ -922,6 +970,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, INIT_LIST_HEAD(&gpu->active_list); kthread_init_work(&gpu->retire_work, retire_worker); kthread_init_work(&gpu->recover_work, recover_worker); + kthread_init_work(&gpu->fault_work, fault_worker); timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 18baf935e143..ef41ec09f59c 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -71,6 +71,15 @@ struct msm_gpu_funcs { uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); }; +/* Additional state for iommu faults: */ +struct msm_gpu_fault_info { + u64 ttbr0; + unsigned long iova; + int flags; + const char *type; + const char *block; +}; + struct msm_gpu { const char *name; struct drm_device *dev; @@ -118,23 +127,19 @@ struct msm_gpu { struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; uint32_t fast_rate; - /* The gfx-mem interconnect path that's used by all GPU types. */ - struct icc_path *icc_path; - - /* - * Second interconnect path for some A3xx and all A4xx GPUs to the - * On Chip MEMory (OCMEM). - */ - struct icc_path *ocmem_icc_path; - /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ -#define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ -#define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) +#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */ struct timer_list hangcheck_timer; + /* Fault info for most recent iova fault: */ + struct msm_gpu_fault_info fault_info; + + /* work for handling GPU ioval faults: */ + struct kthread_work fault_work; + /* work for handling GPU recovery: */ struct kthread_work recover_work; @@ -242,6 +247,8 @@ struct msm_gpu_state { char *comm; char *cmd; + struct msm_gpu_fault_info fault_info; + int nr_bos; struct msm_gpu_state_bo *bos; }; diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/msm_gpummu.c index 379496186c7f..f7d1945e0c9f 100644 --- a/drivers/gpu/drm/msm/msm_gpummu.c +++ b/drivers/gpu/drm/msm/msm_gpummu.c @@ -68,6 +68,10 @@ static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) return 0; } +static void msm_gpummu_resume_translation(struct msm_mmu *mmu) +{ +} + static void msm_gpummu_destroy(struct msm_mmu *mmu) { struct msm_gpummu *gpummu = to_msm_gpummu(mmu); @@ -83,6 +87,7 @@ static const struct msm_mmu_funcs funcs = { .map = msm_gpummu_map, .unmap = msm_gpummu_unmap, .destroy = msm_gpummu_destroy, + .resume_translation = msm_gpummu_resume_translation, }; struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 50d881794758..eed2a762e9dd 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -184,6 +184,9 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) * the arm-smmu driver as a trigger to set up TTBR0 */ if (atomic_inc_return(&iommu->pagetables) == 1) { + /* Enable stall on iommu fault: */ + adreno_smmu->set_stall(adreno_smmu->cookie, true); + ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg); if (ret) { free_io_pgtable_ops(pagetable->pgtbl_ops); @@ -211,12 +214,28 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { struct msm_iommu *iommu = arg; + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev); + struct adreno_smmu_fault_info info, *ptr = NULL; + + if (adreno_smmu->get_fault_info) { + adreno_smmu->get_fault_info(adreno_smmu->cookie, &info); + ptr = &info; + } + if (iommu->base.handler) - return iommu->base.handler(iommu->base.arg, iova, flags); + return iommu->base.handler(iommu->base.arg, iova, flags, ptr); + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); return 0; } +static void msm_iommu_resume_translation(struct msm_mmu *mmu) +{ + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev); + + adreno_smmu->resume_translation(adreno_smmu->cookie, true); +} + static void msm_iommu_detach(struct msm_mmu *mmu) { struct msm_iommu *iommu = to_msm_iommu(mmu); @@ -264,6 +283,7 @@ static const struct msm_mmu_funcs funcs = { .map = msm_iommu_map, .unmap = msm_iommu_unmap, .destroy = msm_iommu_destroy, + .resume_translation = msm_iommu_resume_translation, }; struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index d8151a89e163..086a2d59b8c8 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -122,6 +122,10 @@ struct msm_kms_funcs { bool cmd_mode); /* cleanup: */ void (*destroy)(struct msm_kms *kms); + + /* snapshot: */ + void (*snapshot)(struct msm_disp_state *disp_state, struct msm_kms *kms); + #ifdef CONFIG_DEBUG_FS /* debugfs: */ int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor); @@ -152,6 +156,11 @@ struct msm_kms { /* mapper-id used to request GEM buffer mapped for scanout: */ struct msm_gem_address_space *aspace; + /* disp snapshot support */ + struct kthread_worker *dump_worker; + struct kthread_work dump_work; + struct mutex dump_mutex; + /* * For async commit, where ->flush_commit() and later happens * from the crtc's pending_timer close to end of the frame: diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 61ade89d9e48..de158e1bf765 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -15,6 +15,7 @@ struct msm_mmu_funcs { size_t len, int prot); int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len); void (*destroy)(struct msm_mmu *mmu); + void (*resume_translation)(struct msm_mmu *mmu); }; enum msm_mmu_type { @@ -26,7 +27,7 @@ enum msm_mmu_type { struct msm_mmu { const struct msm_mmu_funcs *funcs; struct device *dev; - int (*handler)(void *arg, unsigned long iova, int flags); + int (*handler)(void *arg, unsigned long iova, int flags, void *data); void *arg; enum msm_mmu_type type; }; @@ -43,7 +44,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu); static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, - int (*handler)(void *arg, unsigned long iova, int flags)) + int (*handler)(void *arg, unsigned long iova, int flags, void *data)) { mmu->arg = arg; mmu->handler = handler; diff --git a/drivers/gpu/drm/selftests/test-drm_framebuffer.c b/drivers/gpu/drm/selftests/test-drm_framebuffer.c index 789f22773dbc..61b44d3a6a61 100644 --- a/drivers/gpu/drm/selftests/test-drm_framebuffer.c +++ b/drivers/gpu/drm/selftests/test-drm_framebuffer.c @@ -8,6 +8,7 @@ #include <drm/drm_device.h> #include <drm/drm_mode.h> #include <drm/drm_fourcc.h> +#include <drm/drm_print.h> #include "../drm_crtc_internal.h" |