diff options
| author | Jonathan Marek <jonathan@marek.ca> | 2021-06-08 13:27:47 -0400 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-06-23 07:33:55 -0700 |
| commit | 564499f5ddbb2d8529a460e24ef6bd2e8593c775 (patch) | |
| tree | dd6eb14a1ff9295ed511ed25389601abc49b8a4d /drivers/gpu | |
| parent | 58e933e3f012d47d88ca35cd8688d4a31a0def4d (diff) | |
drm/msm/a6xx: add missing PC_DBG_ECO_CNTL bit for a640/a650
See downstream's "disable_tseskip" flag.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210608172808.11803-5-jonathan@marek.ca
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a69150cb75d8..16b3bd9ad44c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -844,13 +844,15 @@ static int a6xx_hw_init(struct msm_gpu *gpu) /* Setting the mem pool size */ gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); - /* Setting the primFifo thresholds default values */ + /* Setting the primFifo thresholds default values, + * and vccCacheSkipDis=1 bit (0x200) for A640 and newer + */ if (adreno_is_a650(adreno_gpu)) - gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); else if (adreno_is_a640(adreno_gpu)) - gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); else - gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); /* Set the AHB default slave response to "ERROR" */ gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); |