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author | Fabio Estevam <festevam@denx.de> | 2023-07-25 20:26:28 -0300 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2023-07-30 21:32:36 +0800 |
commit | f02b53375e8f14b4c27a14f6e4fb6e89914fdc29 (patch) | |
tree | 390b5ca109bb36304e850f20d393c1463a7dc09e /drivers/hid/hid-picolcd_fb.c | |
parent | 926c733508ddb9ec10e28a403f67feb0e38fad0d (diff) |
arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration
The CSI1 PHY reference clock is limited to 125 MHz according to:
i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
Table 5-1. Clock Root Table (continued) / page 307
Slice Index n = 123 .
Currently the IMX8MM_CLK_CSI1_PHY_REF clock is configured to be
fed directly from 1 GHz PLL2 , which overclocks them. Instead, drop
the configuration altogether, which defaults the clock to 24 MHz REF
clock input, which for the PHY reference clock is just fine.
Based on a patch from Marek Vasut for the imx8mn.
Fixes: e523b7c54c05 ("arm64: dts: imx8mm: Add CSI nodes")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/hid/hid-picolcd_fb.c')
0 files changed, 0 insertions, 0 deletions