diff options
| author | Austin Christ <austinwc@codeaurora.org> | 2018-05-10 10:13:56 -0600 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2018-05-29 19:53:03 +0200 |
| commit | 71fbafcc45fed7c647987495900b8f6ff29fc5aa (patch) | |
| tree | ff2e9e70e5065888adeb6a99ba595c53b19b7e64 /drivers/i2c | |
| parent | 109b8c42b7e28ddf843488f01f243a9c9eba032b (diff) | |
i2c: qup: Correct duty cycle for FM and FM+
The I2C spec UM10204 Rev. 6 specifies the following timings.
Standard Fast Mode Fast Mode Plus
SCL low 4.7us 1.3us 0.5us
SCL high 4.0us 0.6us 0.26us
This results in a 33%/66% duty cycle as opposed to the 50%/50% duty cycle
used for Standard-mode.
Add High Time Divider settings to correct duty cycle for FM(400kHz) and
FM+(1MHz).
Signed-off-by: Austin Christ <austinwc@codeaurora.org>
Reviewed-by: Sricharan R <sricharan@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/busses/i2c-qup.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c index ce5f215cd7e8..f87f29f5be65 100644 --- a/drivers/i2c/busses/i2c-qup.c +++ b/drivers/i2c/busses/i2c-qup.c @@ -1855,9 +1855,15 @@ nodma: size = QUP_INPUT_FIFO_SIZE(io_mode); qup->in_fifo_sz = qup->in_blk_sz * (2 << size); - fs_div = ((src_clk_freq / clk_freq) / 2) - 3; hs_div = 3; - qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); + if (clk_freq <= I2C_STANDARD_FREQ) { + fs_div = ((src_clk_freq / clk_freq) / 2) - 3; + qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); + } else { + /* 33%/66% duty cycle */ + fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; + qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); + } /* * Time it takes for a byte to be clocked out on the bus. |