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authorNeelesh Gupta <neelegup@linux.vnet.ibm.com>2015-03-13 15:25:33 +0100
committerWolfram Sang <wsa@the-dreams.de>2015-03-14 12:08:21 +0100
commitbf07038051ddd6c1e017cd50933e314040a69b11 (patch)
tree0f2c2b27f8b5f757bdd49f64f3e035126492f8c4 /drivers/i2c
parent338f1ab6c4ea60cbc8ee57b78707d4b8d0219519 (diff)
i2c: opal: Update quirk flags to do write-then-anything
Hardware can do write-then-anything. Activate that. Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com> [wsa: cosmetic updates] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-opal.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/i2c/busses/i2c-opal.c b/drivers/i2c/busses/i2c-opal.c
index b2788ecad5b3..75dd6d041241 100644
--- a/drivers/i2c/busses/i2c-opal.c
+++ b/drivers/i2c/busses/i2c-opal.c
@@ -104,7 +104,8 @@ static int i2c_opal_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
req.buffer_ra = cpu_to_be64(__pa(msgs[0].buf));
break;
case 2:
- req.type = OPAL_I2C_SM_READ;
+ req.type = (msgs[1].flags & I2C_M_RD) ?
+ OPAL_I2C_SM_READ : OPAL_I2C_SM_WRITE;
req.addr = cpu_to_be16(msgs[0].addr);
req.subaddr_sz = msgs[0].len;
for (i = 0; i < msgs[0].len; i++)
@@ -199,13 +200,12 @@ static const struct i2c_algorithm i2c_opal_algo = {
.functionality = i2c_opal_func,
};
-/* For two messages, we basically support only simple
- * smbus transactions of a write plus a read. We might
- * want to allow also two writes but we'd have to bounce
- * the data into a single buffer.
+/*
+ * For two messages, we basically support simple smbus transactions of a
+ * write-then-anything.
*/
static struct i2c_adapter_quirks i2c_opal_quirks = {
- .flags = I2C_AQ_COMB_WRITE_THEN_READ,
+ .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
.max_comb_1st_msg_len = 4,
};