diff options
| author | Lars-Peter Clausen <lars@metafoo.de> | 2020-09-22 15:46:24 +0200 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2021-01-09 14:25:24 +0000 |
| commit | c2b7720a7905bb8aa3a9decbf135fec98faba38d (patch) | |
| tree | 893e3774e1fcfd5d5c050ec7820ca81cdd4d4992 /drivers/iio/adc/xilinx-xadc-events.c | |
| parent | d0dc4c80b9ee667bfe9c3e5735707cfec085df3b (diff) | |
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor
The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx
7 series FPGAs. The system-monitor is the equivalent to the XADC in the
Xilinx UltraScale and UltraScale+ FPGAs.
The IP designers did a good job at maintaining backwards compatibility and
only minor changes are required to add basic support for the system-monitor
core.
The non backwards compatible changes are:
* Register map offset was moved from 0x200 to 0x400
* Only one ADC compared to two in the XADC
* 10 bit ADC instead of 12 bit ADC
* Two of the channels monitor different supplies
Add the necessary logic to accommodate these changes to support the
system-monitor in the XADC driver.
Note that this patch does not include support for some new features found
in the system-monitor like additional alarms, user supply monitoring and
secondary system-monitor access. This might be added at a later time.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Tested-by: Anand Ashok Dumbre <anandash@xilinx.com>
Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com>
Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc/xilinx-xadc-events.c')
| -rw-r--r-- | drivers/iio/adc/xilinx-xadc-events.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/iio/adc/xilinx-xadc-events.c b/drivers/iio/adc/xilinx-xadc-events.c index 2357f585720a..1bd375fb10e0 100644 --- a/drivers/iio/adc/xilinx-xadc-events.c +++ b/drivers/iio/adc/xilinx-xadc-events.c @@ -155,9 +155,6 @@ err_out: return ret; } -/* Register value is msb aligned, the lower 4 bits are ignored */ -#define XADC_THRESHOLD_VALUE_SHIFT 4 - int xadc_read_event_value(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, enum iio_event_type type, enum iio_event_direction dir, enum iio_event_info info, @@ -177,7 +174,8 @@ int xadc_read_event_value(struct iio_dev *indio_dev, return -EINVAL; } - *val >>= XADC_THRESHOLD_VALUE_SHIFT; + /* MSB aligned */ + *val >>= 16 - chan->scan_type.realbits; return IIO_VAL_INT; } @@ -191,7 +189,8 @@ int xadc_write_event_value(struct iio_dev *indio_dev, struct xadc *xadc = iio_priv(indio_dev); int ret = 0; - val <<= XADC_THRESHOLD_VALUE_SHIFT; + /* MSB aligned */ + val <<= 16 - chan->scan_type.realbits; if (val < 0 || val > 0xffff) return -EINVAL; |