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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 18:57:00 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 11:53:19 +0100
commitb5841c38cb2f7e54b0787b3e0326a6b21b89ea3e (patch)
tree64664b13b76e09d1669eeed907361ed60808995b /drivers/iio/potentiometer
parent54e03562bb960e78af050d2e550c28d77642ee44 (diff)
iio: potentiometer: ad5110: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: d03a74bfacce ("iio: potentiometer: Add driver support for AD5110") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Mugilraj Dhavachelvan <dmugil2000@gmail.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-81-jic23@kernel.org
Diffstat (limited to 'drivers/iio/potentiometer')
-rw-r--r--drivers/iio/potentiometer/ad5110.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/potentiometer/ad5110.c b/drivers/iio/potentiometer/ad5110.c
index d4eeedae56e5..8fbcce482989 100644
--- a/drivers/iio/potentiometer/ad5110.c
+++ b/drivers/iio/potentiometer/ad5110.c
@@ -63,10 +63,10 @@ struct ad5110_data {
struct mutex lock;
const struct ad5110_cfg *cfg;
/*
- * DMA (thus cache coherency maintenance) requires the
+ * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
- u8 buf[2] ____cacheline_aligned;
+ u8 buf[2] __aligned(IIO_DMA_MINALIGN);
};
static const struct iio_chan_spec ad5110_channels[] = {