diff options
| author | Wenpeng Liang <liangwenpeng@huawei.com> | 2021-06-18 18:10:18 +0800 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2021-06-22 15:17:07 -0300 |
| commit | c462a0242bd938967c9a69c41364f80e188c1a7a (patch) | |
| tree | b20db4ba16c5c7e1460093c70f6eaf25ef70b519 /drivers/infiniband/hw/hns/hns_roce_qp.c | |
| parent | a33958ca5204f8d2342fd8fe9f547e33fa6c07ed (diff) | |
RDMA/hns: Encapsulate flushing CQE as a function
The process of flushing CQE can be encapsultated into a function, which
can reduce duplicate code.
Link: https://lore.kernel.org/r/1624011020-16992-9-git-send-email-liweihang@huawei.com
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/infiniband/hw/hns/hns_roce_qp.c')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_qp.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index 090b1433ae82..b101b7e578f2 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -79,6 +79,21 @@ void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) queue_work(hr_dev->irq_workq, &flush_work->work); } +void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp) +{ + /* + * Hip08 hardware cannot flush the WQEs in SQ/RQ if the QP state + * gets into errored mode. Hence, as a workaround to this + * hardware limitation, driver needs to assist in flushing. But + * the flushing operation uses mailbox to convey the QP state to + * the hardware and which can sleep due to the mutex protection + * around the mailbox calls. Hence, use the deferred flush for + * now. + */ + if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) + init_flush_work(dev, qp); +} + void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) { struct device *dev = hr_dev->dev; @@ -102,8 +117,8 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) event_type == HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION || event_type == HNS_ROCE_EVENT_TYPE_INVALID_XRCETH)) { qp->state = IB_QPS_ERR; - if (!test_and_set_bit(HNS_ROCE_FLUSH_FLAG, &qp->flush_flag)) - init_flush_work(hr_dev, qp); + + flush_cqe(hr_dev, qp); } qp->event(qp, (enum hns_roce_event)event_type); |