diff options
| author | Jean-Philippe Brucker <jean-philippe@linaro.org> | 2020-02-24 17:58:43 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-03-18 21:32:25 +0000 |
| commit | 87e5fe5b779a20fa02382aaf169015e68710b9ff (patch) | |
| tree | f2da2a77c24715193ae8c44049567ba7e3b52eb8 /drivers/iommu | |
| parent | 058c59a047d61601abf503563bbea818ee645c09 (diff) | |
iommu/arm-smmu-v3: Write level-1 descriptors atomically
Use WRITE_ONCE() to make sure that the SMMU doesn't read incomplete
stream table descriptors. Refer to the comment about 64-bit accesses,
and add the comment to the equivalent context descriptor code.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/arm-smmu-v3.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 6b76df37025e..068a16d0eabe 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1531,6 +1531,7 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, u64 val = (l1_desc->l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) | CTXDESC_L1_DESC_V; + /* See comment in arm_smmu_write_ctx_desc() */ WRITE_ONCE(*dst, cpu_to_le64(val)); } @@ -1726,7 +1727,8 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) val |= FIELD_PREP(STRTAB_L1_DESC_SPAN, desc->span); val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK; - *dst = cpu_to_le64(val); + /* See comment in arm_smmu_write_ctx_desc() */ + WRITE_ONCE(*dst, cpu_to_le64(val)); } static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) |