diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2022-06-09 18:52:41 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-06-10 08:57:19 +0100 |
| commit | 6fac824f40987a54a08dfbcc36145869d02e45b1 (patch) | |
| tree | d7df6acbca838aa85962b0544a45cf13b0128362 /drivers/irqchip/irq-loongson-liointc.c | |
| parent | e3f056a7aafabe4ac3ad4b7465ba821b44a7e639 (diff) | |
irqchip/loongson-liointc: Use architecture register to get coreid
fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.
Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.
Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220609175242.977-1-jiaxun.yang@flygoat.com
Diffstat (limited to 'drivers/irqchip/irq-loongson-liointc.c')
| -rw-r--r-- | drivers/irqchip/irq-loongson-liointc.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c index aed88857d90f..8d05d8bcf56f 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -39,6 +39,12 @@ #define LIOINTC_ERRATA_IRQ 10 +#if defined(CONFIG_MIPS) +#define liointc_core_id get_ebase_cpunum() +#else +#define liointc_core_id get_csr_cpuid() +#endif + struct liointc_handler_data { struct liointc_priv *priv; u32 parent_int_map; @@ -57,7 +63,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc) struct liointc_handler_data *handler = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct irq_chip_generic *gc = handler->priv->gc; - int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES; + int core = liointc_core_id % LIOINTC_NUM_CORES; u32 pending; chained_irq_enter(chip, desc); |