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authorPaul Burton <paul.burton@imgtec.com>2017-08-12 21:36:44 -0700
committerRalf Baechle <ralf@linux-mips.org>2017-09-04 13:53:15 +0200
commitb2b2e584ceabeddbc5ea1965ca6ca435726f5de0 (patch)
treeaf01dc52cc6a699ff28ac1702bf2f3210db630bd /drivers/irqchip/irq-mips-gic.c
parent7778c4b27cbe0e24dc016477ec60d63b272f7ea2 (diff)
irqchip: mips-gic: Clean up mti, reserved-cpu-vectors handling
When parsing mti,reserved-cpu-vectors we generate a mask of all bits that have been declared reserved, the loop through starting from bit 2 to find one that isn't reserved (ie. is zero). This patch accomplishes the same task more simply by: - Inititialising the reserved mask to 0x3 (ie. the 2 software interrupts). This means we don't need to skip them later as the loop previously has. - Replacing the loop checking for zero bits with find_first_zero_bit, which fits our needs now that the 2 software interrupts are marked reserved. This requires that the type of reserved is changed to unsigned long so that it's suitable for use with bitmap functions. - Replacing the magic number 8 with the hamming weight of the ST0_IM field - ie. the number of bits that a MIPS CPU has for interrupt inputs. This is still a compile-time constant 8, but makes it clearer why it's 8. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17054/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers/irqchip/irq-mips-gic.c')
-rw-r--r--drivers/irqchip/irq-mips-gic.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index e2ab0cee9ff2..183c225b84de 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -636,21 +636,21 @@ static const struct irq_domain_ops gic_ipi_domain_ops = {
static int __init gic_of_init(struct device_node *node,
struct device_node *parent)
{
- unsigned int cpu_vec, i, j, reserved, gicconfig, cpu, v[2];
+ unsigned int cpu_vec, i, j, gicconfig, cpu, v[2];
+ unsigned long reserved;
phys_addr_t gic_base;
struct resource res;
size_t gic_len;
/* Find the first available CPU vector. */
- i = reserved = 0;
+ i = 0;
+ reserved = (C_SW0 | C_SW1) >> __fls(C_SW0);
while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
i++, &cpu_vec))
reserved |= BIT(cpu_vec);
- for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
- if (!(reserved & BIT(cpu_vec)))
- break;
- }
- if (cpu_vec == 8) {
+
+ cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
+ if (cpu_vec == hweight_long(ST0_IM)) {
pr_err("No CPU vectors available for GIC\n");
return -ENODEV;
}