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authorMarc Zyngier <maz@kernel.org>2023-02-06 17:26:11 +0000
committerMarc Zyngier <maz@kernel.org>2023-02-06 17:26:11 +0000
commitdf2d85d0b0b5b1533d6db9079f0a0a7b73ef6a9e (patch)
treea11141d24ef36ddd12257a3189611e848cde4444 /drivers/irqchip
parent5f61c6931b18369798e561aa378d5ea6236bcdef (diff)
parent9c1a7bfc2993112cfb3056b18301fcafe5c2fde5 (diff)
Merge branch irq/misc-6.3 into irq/irqchip-next
* irq/misc-6.3: : . : - Cleanup Kconfig dependencies for LS_SCFG_MSI : : - Improve save/restore for the loongson-liointc irqchip : : - Correctly initialise status and enable registers for one : of the ASpeed controllers : . irqchip/ls-scfg-msi: Simplify Kconfig dependencies irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4 irqchip/aspeed-scu-ic: Correctly initialise status and enable registers Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/Kconfig2
-rw-r--r--drivers/irqchip/irq-aspeed-scu-ic.c5
-rw-r--r--drivers/irqchip/irq-loongson-liointc.c13
3 files changed, 18 insertions, 2 deletions
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index cbf504794e7c..7abdb98f805d 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -389,7 +389,7 @@ config LS_EXTIRQ
config LS_SCFG_MSI
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
- depends on PCI && PCI_MSI
+ depends on PCI_MSI
config PARTITION_PERCPU
bool
diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c
index 279e92cf0b16..94a7223e95df 100644
--- a/drivers/irqchip/irq-aspeed-scu-ic.c
+++ b/drivers/irqchip/irq-aspeed-scu-ic.c
@@ -17,8 +17,9 @@
#define ASPEED_SCU_IC_REG 0x018
#define ASPEED_SCU_IC_SHIFT 0
-#define ASPEED_SCU_IC_ENABLE GENMASK(6, ASPEED_SCU_IC_SHIFT)
+#define ASPEED_SCU_IC_ENABLE GENMASK(15, ASPEED_SCU_IC_SHIFT)
#define ASPEED_SCU_IC_NUM_IRQS 7
+#define ASPEED_SCU_IC_STATUS GENMASK(28, 16)
#define ASPEED_SCU_IC_STATUS_SHIFT 16
#define ASPEED_AST2600_SCU_IC0_REG 0x560
@@ -155,6 +156,8 @@ static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic,
rc = PTR_ERR(scu_ic->scu);
goto err;
}
+ regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_STATUS, ASPEED_SCU_IC_STATUS);
+ regmap_write_bits(scu_ic->scu, scu_ic->reg, ASPEED_SCU_IC_ENABLE, 0);
irq = irq_of_parse_and_map(node, 0);
if (!irq) {
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 85b754f7f4e6..8d00a9ad5b00 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -55,6 +55,8 @@ struct liointc_priv {
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
void __iomem *core_isr[LIOINTC_NUM_CORES];
u8 map_cache[LIOINTC_CHIP_IRQ];
+ u32 int_pol;
+ u32 int_edge;
bool has_lpc_irq_errata;
};
@@ -138,6 +140,14 @@ static int liointc_set_type(struct irq_data *data, unsigned int type)
return 0;
}
+static void liointc_suspend(struct irq_chip_generic *gc)
+{
+ struct liointc_priv *priv = gc->private;
+
+ priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);
+ priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);
+}
+
static void liointc_resume(struct irq_chip_generic *gc)
{
struct liointc_priv *priv = gc->private;
@@ -150,6 +160,8 @@ static void liointc_resume(struct irq_chip_generic *gc)
/* Restore map cache */
for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
writeb(priv->map_cache[i], gc->reg_base + i);
+ writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);
+ writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);
/* Restore mask cache */
writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
irq_gc_unlock_irqrestore(gc, flags);
@@ -269,6 +281,7 @@ static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
gc->private = priv;
gc->reg_base = base;
gc->domain = domain;
+ gc->suspend = liointc_suspend;
gc->resume = liointc_resume;
ct = gc->chip_types;