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authorVladimir Murzin <vladimir.murzin@arm.com>2021-12-01 11:02:58 +0000
committerMarc Zyngier <maz@kernel.org>2021-12-02 09:27:06 +0000
commitc5e0cbe2858d278a27d5b3fe31890aea5be064c4 (patch)
tree10771c98bce693f81bef0f234050abfac1e9c6ea /drivers/irqchip
parent357a9c4b79f4c8bbceb77c64ea09d8da3a6a870d (diff)
irqchip: nvic: Fix offset for Interrupt Priority Offsets
According to ARM(v7M) ARM Interrupt Priority Offsets located at 0xE000E400-0xE000E5EC, while 0xE000E300-0xE000E33C covers read-only Interrupt Active Bit Registers Fixes: 292ec080491d ("irqchip: Add support for ARMv7-M NVIC") Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211201110259.84857-1-vladimir.murzin@arm.com
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/irq-nvic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
index 63bac3f78863..ba4759b3e269 100644
--- a/drivers/irqchip/irq-nvic.c
+++ b/drivers/irqchip/irq-nvic.c
@@ -26,7 +26,7 @@
#define NVIC_ISER 0x000
#define NVIC_ICER 0x080
-#define NVIC_IPR 0x300
+#define NVIC_IPR 0x400
#define NVIC_MAX_BANKS 16
/*