diff options
| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-04-25 10:26:21 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-04-25 10:26:21 -0300 |
| commit | cfc3d6c44470c5509f1e8efb1577b49dbaeeb2da (patch) | |
| tree | e63c49de395435ce6a8ae906b13e134636810d3d /drivers/media/dvb-frontends/rtl2832_priv.h | |
| parent | 542b329f8e0d92ca93d033d13a9db16b89830acd (diff) | |
| parent | 396f3659aa9decdb0acf82a36e59c20d656e19ed (diff) | |
Merge branch 'topic/r820t' into patchwork
* topic/r820t: (31 commits)
[media] r820t: Don't divide the IF by two
[media] r820t: disable auto gain/VGA setting
[media] rtl2832: Fix IF calculus
[media] r820t: put it into automatic gain mode
[media] r820t: Fix hp_cor filter mask
[media] r820t: fix PLL calculus
[media] r820t: Don't put it in standby if not initialized yet
[media] r820t: avoid rewrite all regs when not needed
[media] r820t: Allow disabling IMR callibration
[media] r820t: add a commented code for GPIO
[media] r820t: add IMR calibrate code
[media] r820t: proper initialize the PLL register
[media] r820t: use usleep_range()
[media] r820t: fix prefix of the r820t_read() function
[media] r820t: split the function that read cached regs
[media] r820t: better report signal strength
[media] r820t: add support for diplexer
[media] r820t: Show the read data in the bit-reversed order
[media] r820t: use the second table for 7MHz
[media] r820t: Invert bits for read ops
...
Diffstat (limited to 'drivers/media/dvb-frontends/rtl2832_priv.h')
| -rw-r--r-- | drivers/media/dvb-frontends/rtl2832_priv.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/media/dvb-frontends/rtl2832_priv.h b/drivers/media/dvb-frontends/rtl2832_priv.h index 7d97ce9d2193..b5f2b80092ee 100644 --- a/drivers/media/dvb-frontends/rtl2832_priv.h +++ b/drivers/media/dvb-frontends/rtl2832_priv.h @@ -267,6 +267,7 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = { {DVBT_OPT_ADC_IQ, 0x1}, {DVBT_AD_AVI, 0x0}, {DVBT_AD_AVQ, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { @@ -300,6 +301,7 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = { {DVBT_GI_PGA_STATE, 0x0}, {DVBT_EN_AGC_PGA, 0x1}, {DVBT_IF_AGC_MAN, 0x0}, + {DVBT_SPEC_INV, 0x0}, }; static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { @@ -337,6 +339,32 @@ static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = { {DVBT_REG_MONSEL, 0x1}, {DVBT_REG_MON, 0x1}, {DVBT_REG_4MSEL, 0x0}, + {DVBT_SPEC_INV, 0x0}, +}; + +static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = { + {DVBT_DAGC_TRG_VAL, 0x39}, + {DVBT_AGC_TARG_VAL_0, 0x0}, + {DVBT_AGC_TARG_VAL_8_1, 0x40}, + {DVBT_AAGC_LOOP_GAIN, 0x16}, + {DVBT_LOOP_GAIN2_3_0, 0x8}, + {DVBT_LOOP_GAIN2_4, 0x1}, + {DVBT_LOOP_GAIN3, 0x18}, + {DVBT_VTOP1, 0x35}, + {DVBT_VTOP2, 0x21}, + {DVBT_VTOP3, 0x21}, + {DVBT_KRF1, 0x0}, + {DVBT_KRF2, 0x40}, + {DVBT_KRF3, 0x10}, + {DVBT_KRF4, 0x10}, + {DVBT_IF_AGC_MIN, 0x80}, + {DVBT_IF_AGC_MAX, 0x7f}, + {DVBT_RF_AGC_MIN, 0x80}, + {DVBT_RF_AGC_MAX, 0x7f}, + {DVBT_POLAR_RF_AGC, 0x0}, + {DVBT_POLAR_IF_AGC, 0x0}, + {DVBT_AD7_SETTING, 0xe9f4}, + {DVBT_SPEC_INV, 0x1}, }; #endif /* RTL2832_PRIV_H */ |