diff options
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-06-22 12:16:24 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:52:09 +0100 |
| commit | cac8f5d28e56c405befd1613fc38c962aaf69f30 (patch) | |
| tree | db75fe3b01234730fee1d89847e102a49c5ebc3a /drivers/media/i2c/ccs-pll.h | |
| parent | e583e654565fd12e45d8cef64dcdd80e2902ac13 (diff) | |
media: ccs-pll: Add support for lane speed model
CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.
Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index 3ad4e6524ab6..fe8eb3d4bcff 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -22,6 +22,8 @@ /* op pix clock is for all lanes in total normally */ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) +/* CCS PLL flags */ +#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front) @@ -63,6 +65,8 @@ struct ccs_pll_branch_bk { * All information required to calculate CCS PLL configuration. * * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input) + * @op_lanes: Number of operational lanes (input) + * @vt_lanes: Number of video timing lanes (input) * @csi2: CSI-2 related parameters * @csi2.lanes: The number of the CSI-2 data lanes (input) * @binning_vertical: Vertical binning factor (input) @@ -84,6 +88,8 @@ struct ccs_pll_branch_bk { struct ccs_pll { /* input values */ uint8_t bus_type; + uint8_t op_lanes; + uint8_t vt_lanes; struct { uint8_t lanes; } csi2; |