diff options
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-06-23 13:40:32 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:56:17 +0100 |
| commit | 4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c (patch) | |
| tree | b5738c25e951292d6dd82a158af6d0ef54f73a88 /drivers/media/i2c/ccs | |
| parent | ae502e08f45e47460406ab5c5fd2167a1011499a (diff) | |
media: ccs-pll: Add support for extended input PLL clock divider
CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculator and the CCS
driver.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs')
| -rw-r--r-- | drivers/media/i2c/ccs/ccs-core.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 855e51675864..6c2b8a4259fd 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3219,6 +3219,9 @@ static int ccs_probe(struct i2c_client *client) sensor->pll.op_lanes = sensor->pll.csi2.lanes; } } + if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & + CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER) + sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER; sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); |