diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-10-12 16:29:19 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-15 10:12:32 +0100 |
| commit | 2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8 (patch) | |
| tree | 2f0e111f2fb5f4797a8bce773f122053278c5ca2 /drivers/memory/tegra/tegra114.c | |
| parent | 02b0cc52c0c3c89641276cb1e7abddd35e036923 (diff) | |
memory: tegra: Create SMMU display groups
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210.
This allows the display controllers on these devices to share the same
IOMMU domain using the standard IOMMU group mechanism.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra/tegra114.c')
| -rw-r--r-- | drivers/memory/tegra/tegra114.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index ba8fff3d66a6..b20e6e3e208e 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -912,11 +912,26 @@ static const struct tegra_smmu_swgroup tegra114_swgroups[] = { { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, }; +static const unsigned int tegra114_group_display[] = { + TEGRA_SWGROUP_DC, + TEGRA_SWGROUP_DCB, +}; + +static const struct tegra_smmu_group_soc tegra114_groups[] = { + { + .name = "display", + .swgroups = tegra114_group_display, + .num_swgroups = ARRAY_SIZE(tegra114_group_display), + }, +}; + static const struct tegra_smmu_soc tegra114_smmu_soc = { .clients = tegra114_mc_clients, .num_clients = ARRAY_SIZE(tegra114_mc_clients), .swgroups = tegra114_swgroups, .num_swgroups = ARRAY_SIZE(tegra114_swgroups), + .groups = tegra114_groups, + .num_groups = ARRAY_SIZE(tegra114_groups), .supports_round_robin_arbitration = false, .supports_request_limit = false, .num_tlb_lines = 32, |