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authorDmitry Osipenko <digetx@gmail.com>2021-12-22 07:32:15 +0300
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2022-01-27 10:40:35 +0100
commit9ff684342ee7d3ea2755c6e9b60bc43085baa3ad (patch)
tree16d4d1e32d7135d2e54b7b5954ec12c884f6ac26 /drivers/memory
parente3aabb3c7dbe66201b45d7b2c20132196f491ad4 (diff)
memory: tegra20-emc: Correct memory device mask
Memory chip select is swapped when we read mode register, correct it. We didn't have devices that use a single LPDDR chip and both chips are always identical, hence this change is just a minor improvement. Fixes: 131dd9a436d8 ("memory: tegra20-emc: Support matching timings by LPDDR2 configuration") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20211222043215.28237-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/tegra20-emc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 497b6edbf3ca..25ba3c5e4ad6 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -540,7 +540,7 @@ static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
unsigned int register_addr,
unsigned int *register_data)
{
- u32 memory_dev = emem_dev + 1;
+ u32 memory_dev = emem_dev ? 1 : 2;
u32 val, mr_mask = 0xff;
int err;