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authorThierry Reding <treding@nvidia.com>2019-02-15 16:28:19 +0100
committerThierry Reding <treding@nvidia.com>2019-11-11 14:55:24 +0100
commitc4c21f22150ff5bffffb9454ce556ffa047e780d (patch)
tree93e27a379562c904a1ae1e28fe2031cba66dc49b /drivers/memory
parent3feb4a3cf0f8542ed00f4b257c842ffad8008b4e (diff)
memory: tegra: Set DMA mask based on supported address bits
The memory controller on Tegra124 and later supports 34 or more address bits. Advertise that by setting the DMA mask based on the number of the address bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/mc.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 3d8d322511c5..322aa7e8b088 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -626,6 +627,7 @@ static int tegra_mc_probe(struct platform_device *pdev)
struct resource *res;
struct tegra_mc *mc;
void *isr;
+ u64 mask;
int err;
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
@@ -637,6 +639,14 @@ static int tegra_mc_probe(struct platform_device *pdev)
mc->soc = of_device_get_match_data(&pdev->dev);
mc->dev = &pdev->dev;
+ mask = DMA_BIT_MASK(mc->soc->num_address_bits);
+
+ err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
+ if (err < 0) {
+ dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
+ return err;
+ }
+
/* length of MC tick in nanoseconds */
mc->tick = 30;