diff options
| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2021-10-15 10:14:31 +0200 |
|---|---|---|
| committer | Lee Jones <lee.jones@linaro.org> | 2021-10-20 17:24:53 +0100 |
| commit | c4359f750a1e9e2665690171211645e7fe0095f8 (patch) | |
| tree | 056ebd0664f91914efb615ce63edf4473e8dbfd0 /drivers/mfd | |
| parent | 36e48f07ba2ba2aad98040df5e63a992a1eccba1 (diff) | |
mfd: ti_am335x_tscadc: Reword the comment explaining the dividers
The comment misses the main information which is that we assume that a
sample takes 15 ADC clock cycles to be generated. Let's take the
occasion to rework a little bit this comment.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211015081506.933180-14-miquel.raynal@bootlin.com
Diffstat (limited to 'drivers/mfd')
| -rw-r--r-- | drivers/mfd/ti_am335x_tscadc.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c index a211b35ad106..7aeabac37990 100644 --- a/drivers/mfd/ti_am335x_tscadc.c +++ b/drivers/mfd/ti_am335x_tscadc.c @@ -199,12 +199,12 @@ static int ti_tscadc_probe(struct platform_device *pdev) pm_runtime_get_sync(&pdev->dev); /* - * The TSC_ADC_Subsystem has 2 clock domains - * OCP_CLK and ADC_CLK. - * The ADC clock is expected to run at target of 3MHz, - * and expected to capture 12-bit data at a rate of 200 KSPS. - * The TSC_ADC_SS controller design assumes the OCP clock is - * at least 6x faster than the ADC clock. + * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK. + * ADCs produce a 12-bit sample every 15 ADC_CLK cycles. + * am33xx ADCs expect to capture 200ksps. + * We need the ADC clocks to run at 3MHz. + * This frequency is valid since TSC_ADC_SS controller design + * assumes the OCP clock is at least 6x faster than the ADC clock. */ clk = devm_clk_get(&pdev->dev, "adc_tsc_fck"); if (IS_ERR(clk)) { |