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authorOfir Bitton <obitton@habana.ai>2021-01-28 16:30:25 +0200
committerOded Gabbay <ogabbay@kernel.org>2021-02-08 18:20:08 +0200
commit5dbd7b4de6ef84321cc1378eccdd92d4730c2e56 (patch)
treef356ec10cf6ca9f7a9ae591b44b243491a8c7a70 /drivers/misc/habanalabs/common/habanalabs.h
parent6c1e3f92f9f1dfc7f14b43fd432c8ec95b1a188f (diff)
habanalabs: improve communication protocol with cpucp
Current messaging communictaion protocol with cpucp can get out of sync due to coherency issues. In order to improve the protocol reliability, we modify the protocol to expect a different acknowledgment for every packet sent to cpucp. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/common/habanalabs.h')
-rw-r--r--drivers/misc/habanalabs/common/habanalabs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/common/habanalabs.h b/drivers/misc/habanalabs/common/habanalabs.h
index 30f32f2edb8a..3c54010f7ab9 100644
--- a/drivers/misc/habanalabs/common/habanalabs.h
+++ b/drivers/misc/habanalabs/common/habanalabs.h
@@ -419,6 +419,8 @@ struct hl_mmu_properties {
* from BOOT_DEV_STS0
* @dram_supports_virtual_memory: is there an MMU towards the DRAM
* @hard_reset_done_by_fw: true if firmware is handling hard reset flow
+ * @fw_cpucp_ack_with_pi: true if cpucp is acking messages with the PQ PI
+ * instead of a magic number
* @num_functional_hbms: number of functional HBMs in each DCORE.
*/
struct asic_fixed_properties {
@@ -479,6 +481,7 @@ struct asic_fixed_properties {
u8 fw_security_status_valid;
u8 dram_supports_virtual_memory;
u8 hard_reset_done_by_fw;
+ u8 fw_cpucp_ack_with_pi;
u8 num_functional_hbms;
};