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authorOfir Bitton <obitton@habana.ai>2020-10-04 17:34:37 +0300
committerOded Gabbay <ogabbay@kernel.org>2020-11-30 10:47:31 +0200
commitc692dec70379526b0bb09f94467bbd456859dcad (patch)
treeb1baa6a777e5699a686c93ea3112bf3edf282538 /drivers/misc/habanalabs/gaudi/gaudi_security.c
parent323b726706be3b1e547d2662dd77611b8bd82a3a (diff)
habanalabs/gaudi: add support for FW security
Skip relevant HW configurations once FW security is enabled because these configurations are being performed by FW. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/gaudi/gaudi_security.c')
-rw-r--r--drivers/misc/habanalabs/gaudi/gaudi_security.c83
1 files changed, 46 insertions, 37 deletions
diff --git a/drivers/misc/habanalabs/gaudi/gaudi_security.c b/drivers/misc/habanalabs/gaudi/gaudi_security.c
index 8a921ab56557..e10181692d0b 100644
--- a/drivers/misc/habanalabs/gaudi/gaudi_security.c
+++ b/drivers/misc/habanalabs/gaudi/gaudi_security.c
@@ -1448,21 +1448,23 @@ static void gaudi_init_dma_protection_bits(struct hl_device *hdev)
u32 pb_addr, mask;
u8 word_offset;
- gaudi_pb_set_block(hdev, mmDMA_IF_E_S_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH0_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH1_BASE);
- gaudi_pb_set_block(hdev, mmDMA_E_PLL_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_BASE);
-
- gaudi_pb_set_block(hdev, mmDMA_IF_W_N_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH0_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH1_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_BASE);
-
- gaudi_pb_set_block(hdev, mmDMA_IF_E_N_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH0_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH1_BASE);
- gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_BASE);
+ if (hdev->asic_prop.fw_security_disabled) {
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_S_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH0_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_CH1_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_E_PLL_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_S_DOWN_BASE);
+
+ gaudi_pb_set_block(hdev, mmDMA_IF_W_N_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH0_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_CH1_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_W_N_DOWN_BASE);
+
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_N_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH0_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_CH1_BASE);
+ gaudi_pb_set_block(hdev, mmDMA_IF_E_N_DOWN_BASE);
+ }
WREG32(mmDMA0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
WREG32(mmDMA1_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
@@ -9133,14 +9135,16 @@ static void gaudi_init_tpc_protection_bits(struct hl_device *hdev)
u32 pb_addr, mask;
u8 word_offset;
- gaudi_pb_set_block(hdev, mmTPC0_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC1_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC2_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC3_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC4_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC5_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC6_E2E_CRED_BASE);
- gaudi_pb_set_block(hdev, mmTPC7_E2E_CRED_BASE);
+ if (hdev->asic_prop.fw_security_disabled) {
+ gaudi_pb_set_block(hdev, mmTPC0_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC1_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC2_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC3_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC4_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC5_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC6_E2E_CRED_BASE);
+ gaudi_pb_set_block(hdev, mmTPC7_E2E_CRED_BASE);
+ }
WREG32(mmTPC0_QM_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
WREG32(mmTPC0_CFG_BASE - CFG_BASE + PROT_BITS_OFFS + 0x7C, 0);
@@ -12822,11 +12826,13 @@ static void gaudi_init_protection_bits(struct hl_device *hdev)
* secured
*/
- gaudi_pb_set_block(hdev, mmIF_E_PLL_BASE);
- gaudi_pb_set_block(hdev, mmMESH_W_PLL_BASE);
- gaudi_pb_set_block(hdev, mmSRAM_W_PLL_BASE);
- gaudi_pb_set_block(hdev, mmMESH_E_PLL_BASE);
- gaudi_pb_set_block(hdev, mmSRAM_E_PLL_BASE);
+ if (hdev->asic_prop.fw_security_disabled) {
+ gaudi_pb_set_block(hdev, mmIF_E_PLL_BASE);
+ gaudi_pb_set_block(hdev, mmMESH_W_PLL_BASE);
+ gaudi_pb_set_block(hdev, mmSRAM_W_PLL_BASE);
+ gaudi_pb_set_block(hdev, mmMESH_E_PLL_BASE);
+ gaudi_pb_set_block(hdev, mmSRAM_E_PLL_BASE);
+ }
gaudi_init_dma_protection_bits(hdev);
@@ -13025,17 +13031,20 @@ void gaudi_init_security(struct hl_device *hdev)
* property configuration of MME SBAB and ACC to be non-privileged and
* non-secured
*/
- WREG32(mmMME0_SBAB_PROT, 0x2);
- WREG32(mmMME0_ACC_PROT, 0x2);
- WREG32(mmMME1_SBAB_PROT, 0x2);
- WREG32(mmMME1_ACC_PROT, 0x2);
- WREG32(mmMME2_SBAB_PROT, 0x2);
- WREG32(mmMME2_ACC_PROT, 0x2);
- WREG32(mmMME3_SBAB_PROT, 0x2);
- WREG32(mmMME3_ACC_PROT, 0x2);
+ if (hdev->asic_prop.fw_security_disabled) {
+ WREG32(mmMME0_SBAB_PROT, 0x2);
+ WREG32(mmMME0_ACC_PROT, 0x2);
+ WREG32(mmMME1_SBAB_PROT, 0x2);
+ WREG32(mmMME1_ACC_PROT, 0x2);
+ WREG32(mmMME2_SBAB_PROT, 0x2);
+ WREG32(mmMME2_ACC_PROT, 0x2);
+ WREG32(mmMME3_SBAB_PROT, 0x2);
+ WREG32(mmMME3_ACC_PROT, 0x2);
+ }
/* On RAZWI, 0 will be returned from RR and 0xBABA0BAD from PB */
- WREG32(0xC01B28, 0x1);
+ if (hdev->asic_prop.fw_security_disabled)
+ WREG32(0xC01B28, 0x1);
gaudi_init_range_registers_lbw(hdev);