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authorGeorgi Djakov <georgi.djakov@linaro.org>2018-05-30 17:43:35 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2018-05-31 11:45:00 +0200
commit4ba9bf98b8996b70d73381e700384ac75b82f745 (patch)
tree6f9effa50a027a28d278c69d41cf995148b21270 /drivers/mmc
parentaf6b8ff4bce4ea43e89236339f84fc0a26044c42 (diff)
mmc: sdhci-msm: Remove NO_CARD_NO_RESET quirk
Now we have a proper implementation for the power irq handling and this quirk is not needed anymore. In fact, it is causing card detection delays on apq8096 platforms and the following error is displayed: sdhci_msm 74a4900.sdhci: mmc0: pwr_irq for req: (4) timed out The quirk is forcing the controller to retain 1.8V signalling on the slot even when a new card is inserted, which is not correct. The proper behavior would be to reset the controller in order to start with 3.3V signaling. Fixes: c0309b3803fe ("mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr irq") Suggested-by: Vijay Viswanath <vviswana@codeaurora.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-msm.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index bb11916c58a1..646bf377ba77 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1412,7 +1412,6 @@ static const struct sdhci_ops sdhci_msm_ops = {
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
- SDHCI_QUIRK_NO_CARD_NO_RESET |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,