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authorAndrew Jeffery <andrew@aj.id.au>2021-01-14 13:44:31 +1030
committerUlf Hansson <ulf.hansson@linaro.org>2021-02-01 11:54:47 +0100
commit0bbcd22556ef203b29e39a6ce1bd7e9523b6032e (patch)
treec64e100e740fa7462eeb46d9f05d2ed0cb5f02df /drivers/mmc
parent0c53dc321a507c78fdd15a682f42175a131b1763 (diff)
mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations
Converting degrees of phase to logic delays is irritating to test on hardware, so lets exercise the function using KUnit. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210114031433.2388532-5-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/Kconfig14
-rw-r--r--drivers/mmc/host/sdhci-of-aspeed-test.c98
-rw-r--r--drivers/mmc/host/sdhci-of-aspeed.c4
3 files changed, 116 insertions, 0 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 596f32637315..d6f00d1d6251 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -168,6 +168,20 @@ config MMC_SDHCI_OF_ASPEED
If unsure, say N.
+config MMC_SDHCI_OF_ASPEED_TEST
+ bool "Tests for the ASPEED SDHCI driver"
+ depends on MMC_SDHCI_OF_ASPEED && KUNIT=y
+ help
+ Enable KUnit tests for the ASPEED SDHCI driver. Select this
+ option only if you will boot the kernel for the purpose of running
+ unit tests (e.g. under UML or qemu).
+
+ The KUnit tests generally exercise parts of the driver that do not
+ directly touch the hardware, for example, the phase correction
+ calculations.
+
+ If unsure, say N.
+
config MMC_SDHCI_OF_AT91
tristate "SDHCI OF support for the Atmel SDMMC controller"
depends on MMC_SDHCI_PLTFM
diff --git a/drivers/mmc/host/sdhci-of-aspeed-test.c b/drivers/mmc/host/sdhci-of-aspeed-test.c
new file mode 100644
index 000000000000..34070605b28b
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-aspeed-test.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/* Copyright (C) 2020 IBM Corp. */
+
+#include <kunit/test.h>
+
+static void aspeed_sdhci_phase_ddr52(struct kunit *test)
+{
+ int rate = 52000000;
+
+ KUNIT_EXPECT_EQ(test, 0,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 0));
+ KUNIT_EXPECT_EQ(test, 0,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 1));
+ KUNIT_EXPECT_EQ(test, 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 2));
+ KUNIT_EXPECT_EQ(test, 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 3));
+ KUNIT_EXPECT_EQ(test, 2,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 4));
+ KUNIT_EXPECT_EQ(test, 3,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 5));
+ KUNIT_EXPECT_EQ(test, 14,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 23));
+ KUNIT_EXPECT_EQ(test, 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 24));
+ KUNIT_EXPECT_EQ(test, 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 25));
+
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 0,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 180));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 0,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 181));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 182));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 183));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 2,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 184));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 3,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 185));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 14,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 203));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 204));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 205));
+}
+
+static void aspeed_sdhci_phase_hs200(struct kunit *test)
+{
+ int rate = 200000000;
+
+ KUNIT_EXPECT_EQ(test, 0,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 0));
+ KUNIT_EXPECT_EQ(test, 0,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 5));
+ KUNIT_EXPECT_EQ(test, 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 6));
+ KUNIT_EXPECT_EQ(test, 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 7));
+ KUNIT_EXPECT_EQ(test, 14,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 89));
+ KUNIT_EXPECT_EQ(test, 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 90));
+ KUNIT_EXPECT_EQ(test, 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 91));
+ KUNIT_EXPECT_EQ(test, 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 96));
+
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 180));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 185));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 186));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 1,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 187));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 14,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 269));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 270));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 271));
+ KUNIT_EXPECT_EQ(test, (int)ASPEED_SDHCI_TAP_PARAM_INVERT_CLK | 15,
+ aspeed_sdhci_phase_to_tap(NULL, rate, 276));
+}
+
+static struct kunit_case aspeed_sdhci_test_cases[] = {
+ KUNIT_CASE(aspeed_sdhci_phase_ddr52),
+ KUNIT_CASE(aspeed_sdhci_phase_hs200),
+ {}
+};
+
+static struct kunit_suite aspeed_sdhci_test_suite = {
+ .name = "sdhci-of-aspeed",
+ .test_cases = aspeed_sdhci_test_cases,
+};
+kunit_test_suite(aspeed_sdhci_test_suite);
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index 4b30f6a1178e..3b0d381e1215 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -579,6 +579,10 @@ static void __exit aspeed_sdc_exit(void)
}
module_exit(aspeed_sdc_exit);
+#if defined(CONFIG_MMC_SDHCI_OF_ASPEED_TEST)
+#include "sdhci-of-aspeed-test.c"
+#endif
+
MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers");
MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");
MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");