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authorBen Chuang <benchuanggli@gmail.com>2021-05-11 14:18:35 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2021-06-14 13:57:38 +0200
commit34dd3ccccab0b93ebdf7ecde138814d121f72e98 (patch)
tree04444de4f809229458b900e386f60d59d6938035 /drivers/mmc
parent110a8688c6cd11e81a1805d5dc24a7a6b5d86a18 (diff)
mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay
Fine tune the value to 21us in order to improve read/write performance. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Link: https://lore.kernel.org/r/20210511061835.5559-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-pci-gli.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 061618aa247f..4fd99c1e82ba 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -94,7 +94,7 @@
#define PCIE_GLI_9763E_CFG2 0x8A4
#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
-#define GLI_9763E_CFG2_L1DLY_MID 0x50
+#define GLI_9763E_CFG2_L1DLY_MID 0x54
#define PCIE_GLI_9763E_MMC_CTRL 0x960
#define GLI_9763E_HS400_SLOW BIT(3)
@@ -847,7 +847,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
value &= ~GLI_9763E_CFG2_L1DLY;
- /* set ASPM L1 entry delay to 20us */
+ /* set ASPM L1 entry delay to 21us */
value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);