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authorAisheng Dong <b29396@freescale.com>2014-05-09 14:53:15 +0800
committerChris Ball <chris@printf.net>2014-05-22 08:40:45 -0400
commit69f5bf38f93c78faeb93d51dc41adf51e13fe78d (patch)
tree71302b48f24ca133ef6f8c8bd977410f5f556164 /drivers/mmc
parent706adf6bc31c8e4b2b977e1666a01237e4d10e0d (diff)
mmc: sdhci-esdhc-imx: fix mmc ddr mode regression issue
It's caused by the platform driver was still using MMC_TIMING_UHS_DDR50 for MMC DDR mode which needs update too. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Reported-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 4866d802f9e2..ccec0e32590f 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -852,6 +852,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
case MMC_TIMING_MMC_HS200:
break;
case MMC_TIMING_UHS_DDR50:
+ case MMC_TIMING_MMC_DDR52:
writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
ESDHC_MIX_CTRL_DDREN,
host->ioaddr + ESDHC_MIX_CTRL);