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authorChaotian Jing <chaotian.jing@mediatek.com>2017-10-16 09:46:34 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2017-11-02 15:20:24 +0100
commitacde28c434623bde0812cb3051eeea63428871e8 (patch)
treeb3820e2117a9f7d2270731b7bac75b074a32aa7d /drivers/mmc
parent2fea581926703a7cbcf92fa7e3d74d83b5e40d3c (diff)
mmc: mediatek: add busy_check support
bit7 of PATCH_BIT1 has different meaning in new design, to compatible with previous platform, clear this bit in new platform. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Tested-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/mtk-sd.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index c17168ad2be0..650b94498f7c 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -316,6 +316,7 @@ struct mtk_mmc_compatible {
u32 pad_tune_reg;
bool async_fifo;
bool data_tune;
+ bool busy_check;
};
struct msdc_tune_para {
@@ -380,6 +381,7 @@ static const struct mtk_mmc_compatible mt8135_compat = {
.pad_tune_reg = MSDC_PAD_TUNE,
.async_fifo = false,
.data_tune = false,
+ .busy_check = false,
};
static const struct mtk_mmc_compatible mt8173_compat = {
@@ -388,6 +390,7 @@ static const struct mtk_mmc_compatible mt8173_compat = {
.pad_tune_reg = MSDC_PAD_TUNE,
.async_fifo = false,
.data_tune = false,
+ .busy_check = false,
};
static const struct mtk_mmc_compatible mt2701_compat = {
@@ -396,6 +399,7 @@ static const struct mtk_mmc_compatible mt2701_compat = {
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
.data_tune = true,
+ .busy_check = false,
};
static const struct mtk_mmc_compatible mt2712_compat = {
@@ -404,6 +408,7 @@ static const struct mtk_mmc_compatible mt2712_compat = {
.pad_tune_reg = MSDC_PAD_TUNE0,
.async_fifo = true,
.data_tune = true,
+ .busy_check = true,
};
static const struct of_device_id msdc_of_ids[] = {
@@ -1275,6 +1280,8 @@ static void msdc_init_hw(struct msdc_host *host)
sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
+ if (host->dev_comp->busy_check)
+ sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
if (host->dev_comp->async_fifo) {
sdr_set_field(host->base + MSDC_PATCH_BIT2,
MSDC_PB2_RESPWAIT, 3);