diff options
| author | Heiner Kallweit <hkallweit1@gmail.com> | 2017-04-04 21:03:22 +0200 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-04-24 21:42:20 +0200 |
| commit | c08bcb6c90068d8eacffdb8b5f77916de5481a72 (patch) | |
| tree | 2016023e1b0d3edfe545172f327683675deb48c6 /drivers/mmc | |
| parent | 06c9ccb78e68e2e9b69e736fc0a39fb13be49b74 (diff) | |
mmc: meson-gx: introduce struct meson_tuning_params
Introduce struct meson_tuning_params for storing the clock phase
configurations. There's no functional change because tx and rx
clock phase were implicitely set to CLK_PHASE_0 before.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/meson-gx-mmc.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 0036680bad9e..3a6e51c8c5d2 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -49,6 +49,8 @@ #define CLK_SRC_PLL 1 /* FCLK_DIV2 */ #define CLK_SRC_PLL_RATE 1000000000 #define CLK_CORE_PHASE_MASK GENMASK(9, 8) +#define CLK_TX_PHASE_MASK GENMASK(11, 10) +#define CLK_RX_PHASE_MASK GENMASK(13, 12) #define CLK_PHASE_0 0 #define CLK_PHASE_90 1 #define CLK_PHASE_180 2 @@ -111,6 +113,12 @@ #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */ #define MUX_CLK_NUM_PARENTS 2 +struct meson_tuning_params { + u8 core_phase; + u8 tx_phase; + u8 rx_phase; +}; + struct meson_host { struct device *dev; struct mmc_host *mmc; @@ -130,6 +138,7 @@ struct meson_host { void *bounce_buf; dma_addr_t bounce_dma_addr; + struct meson_tuning_params tp; bool vqmmc_enabled; }; @@ -312,7 +321,9 @@ static int meson_mmc_clk_init(struct meson_host *host) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180); + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); clk_reg &= ~CLK_ALWAYS_ON; @@ -757,6 +768,10 @@ static int meson_mmc_probe(struct platform_device *pdev) if (ret) goto free_host; + host->tp.core_phase = CLK_PHASE_180; + host->tp.tx_phase = CLK_PHASE_0; + host->tp.rx_phase = CLK_PHASE_0; + ret = meson_mmc_clk_init(host); if (ret) goto err_core_clk; |