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authorBoris Brezillon <boris.brezillon@bootlin.com>2018-09-04 16:23:28 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2018-10-03 11:12:25 +0200
commit309600c14e36d0e78c22fe3df58317965b90f4d1 (patch)
tree02bac1ad9718de502ed1049aedb07f62479dcc03 /drivers/mtd/nand/raw/fsmc_nand.c
parente2bfa4ca23d9b5a7bdfcf21319fad9b59e38a05c (diff)
mtd: rawnand: Allow selection of ECC byte ordering at runtime
Currently, the selection of ECC byte ordering for software hamming is done at compilation time, which doesn't make sense when ECC byte calculation is done in hardware and byte ordering is forced by the hardware engine. In this case, only the correction is done in software and we want to force the byte-ordering no matter the value of CONFIG_MTD_NAND_ECC_SMC. This is typically the case for the FSMC (Smart Media ordering), TMIO and TXX9NDFMC (regular byte ordering) blocks. For all other use cases (pure software implementation, SM FTL and nandecctest), we keep selecting the byte ordering based on the CONFIG_MTD_NAND_ECC_SMC value. It might not be ideal for SM FTL (I'd expect Smart Media ordering to be employed by the Smart Media FTL), but this option doesn't seem to be enabled in the existing _defconfig, so I can't tell setting sm_order to true is the right choice. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'drivers/mtd/nand/raw/fsmc_nand.c')
-rw-r--r--drivers/mtd/nand/raw/fsmc_nand.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index f9874fc72f30..70ac8d875218 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -949,6 +949,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
nand->ecc.correct = nand_correct_data;
nand->ecc.bytes = 3;
nand->ecc.strength = 1;
+ nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
break;
case NAND_ECC_SOFT: