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authorMiquel Raynal <miquel.raynal@bootlin.com>2020-09-30 01:01:23 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2020-12-10 22:37:30 +0100
commit35fe1b98a0082ad3f576bcc420c74dab435da307 (patch)
tree22c6e65e7dd7d2e830dfdabc93f55b2825d49223 /drivers/mtd/nand/raw/nand_base.c
parent5180a62c12497aa491a7c79c062a9e3a884c9762 (diff)
mtd: nand: ecc-hamming: Create the software Hamming engine
Let's continue introducing the generic ECC engine abstraction in the NAND subsystem by instantiating a second ECC engine: software Hamming. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200929230124.31491-20-miquel.raynal@bootlin.com
Diffstat (limited to 'drivers/mtd/nand/raw/nand_base.c')
-rw-r--r--drivers/mtd/nand/raw/nand_base.c26
1 files changed, 9 insertions, 17 deletions
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index c36d2d4a72d5..c33fa1b1847f 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5141,34 +5141,24 @@ static void nand_scan_ident_cleanup(struct nand_chip *chip)
int rawnand_sw_hamming_init(struct nand_chip *chip)
{
- struct mtd_info *mtd = nand_to_mtd(chip);
struct nand_ecc_sw_hamming_conf *engine_conf;
struct nand_device *base = &chip->base;
+ int ret;
base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING;
base->ecc.user_conf.strength = chip->ecc.strength;
base->ecc.user_conf.step_size = chip->ecc.size;
- if (base->ecc.user_conf.strength != 1 ||
- (base->ecc.user_conf.step_size != 256 &&
- base->ecc.user_conf.step_size != 512)) {
- pr_err("%s: unsupported strength or step size\n", __func__);
- return -EINVAL;
- }
-
- engine_conf = kzalloc(sizeof(*engine_conf), GFP_KERNEL);
- if (!engine_conf)
- return -ENOMEM;
+ ret = nand_ecc_sw_hamming_init_ctx(base);
+ if (ret)
+ return ret;
- engine_conf->code_size = 3;
- engine_conf->nsteps = mtd->writesize / base->ecc.user_conf.step_size;
+ engine_conf = base->ecc.ctx.priv;
if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER)
engine_conf->sm_order = true;
- base->ecc.ctx.priv = engine_conf;
-
chip->ecc.size = base->ecc.ctx.conf.step_size;
chip->ecc.strength = base->ecc.ctx.conf.strength;
chip->ecc.total = base->ecc.ctx.total;
@@ -5204,7 +5194,7 @@ void rawnand_sw_hamming_cleanup(struct nand_chip *chip)
{
struct nand_device *base = &chip->base;
- kfree(base->ecc.ctx.priv);
+ nand_ecc_sw_hamming_cleanup_ctx(base);
}
EXPORT_SYMBOL(rawnand_sw_hamming_cleanup);
@@ -5733,7 +5723,9 @@ static int nand_scan_tail(struct nand_chip *chip)
*/
if (!mtd->ooblayout &&
!(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
- ecc->algo == NAND_ECC_ALGO_BCH)) {
+ ecc->algo == NAND_ECC_ALGO_BCH) &&
+ !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
+ ecc->algo == NAND_ECC_ALGO_HAMMING)) {
switch (mtd->oobsize) {
case 8:
case 16: