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authorCédric Le Goater <clg@kaod.org>2016-12-21 17:57:18 +0100
committerCyrille Pitchen <cyrille.pitchen@atmel.com>2017-02-10 13:54:54 +0100
commite56beebbc7341fd72251bd31580ca4e4e5164d0f (patch)
tree180a65e009e6628bedf44cd4bc15f86b3697f6f2 /drivers/mtd/spi-nor/aspeed-smc.c
parentceb720c71b6309e7f0e91346779f538625eff3aa (diff)
mtd: aspeed: add memory controllers for the Aspeed AST2400 SoC
This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Diffstat (limited to 'drivers/mtd/spi-nor/aspeed-smc.c')
-rw-r--r--drivers/mtd/spi-nor/aspeed-smc.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index f1e18bea9888..6bb4c7d1788c 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -44,8 +44,27 @@ struct aspeed_smc_info {
void (*set_4b)(struct aspeed_smc_chip *chip);
};
+static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip);
static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip);
+static const struct aspeed_smc_info fmc_2400_info = {
+ .maxsize = 64 * 1024 * 1024,
+ .nce = 5,
+ .hastype = true,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .set_4b = aspeed_smc_chip_set_4b,
+};
+
+static const struct aspeed_smc_info spi_2400_info = {
+ .maxsize = 64 * 1024 * 1024,
+ .nce = 1,
+ .hastype = false,
+ .we0 = 0,
+ .ctl0 = 0x04,
+ .set_4b = aspeed_smc_chip_set_4b_spi_2400,
+};
+
static const struct aspeed_smc_info fmc_2500_info = {
.maxsize = 256 * 1024 * 1024,
.nce = 3,
@@ -135,6 +154,7 @@ struct aspeed_smc_controller {
#define CONTROL_IO_DUMMY_HI BIT(14)
#define CONTROL_IO_DUMMY_HI_SHIFT 14
#define CONTROL_CLK_DIV4 BIT(13) /* others */
+#define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */
#define CONTROL_RW_MERGE BIT(12)
#define CONTROL_IO_DUMMY_LO_SHIFT 6
#define CONTROL_IO_DUMMY_LO GENMASK(7, \
@@ -397,6 +417,8 @@ static int aspeed_smc_remove(struct platform_device *dev)
}
static const struct of_device_id aspeed_smc_matches[] = {
+ { .compatible = "aspeed,ast2400-fmc", .data = &fmc_2400_info },
+ { .compatible = "aspeed,ast2400-spi", .data = &spi_2400_info },
{ .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info },
{ .compatible = "aspeed,ast2500-spi", .data = &spi_2500_info },
{ }
@@ -470,6 +492,17 @@ static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip)
}
}
+/*
+ * The AST2400 SPI flash controller does not have a CE Control
+ * register. It uses the CE0 control register to set 4Byte mode at the
+ * controller level.
+ */
+static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip)
+{
+ chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B;
+ chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B;
+}
+
static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
struct resource *res)
{