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authorVivien Didelot <vivien.didelot@savoirfairelinux.com>2017-06-08 18:34:13 -0400
committerDavid S. Miller <davem@davemloft.net>2017-06-09 12:10:59 -0400
commitcd782656da9037150502a16bbbc46272e00f9b1b (patch)
tree1a4430b7f7a2d2e619f7a747654a4e681ea43fc0 /drivers/net/dsa/mv88e6xxx/port.c
parent0898432cc296cc27cee6647f6748f2add37e09b6 (diff)
net: dsa: mv88e6xxx: rework jumbo size operation
Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functionalities, no driver logic. Change port_jumbo_config to port_set_jumbo_size setting the mode from a given maximum size value. There is no functional changes since we still use 10240 bytes. At the same time, correctly clear all Jumbo Mode bits before writing. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx/port.c')
-rw-r--r--drivers/net/dsa/mv88e6xxx/port.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index ee94d16789a2..efeb8d6b02e6 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -816,7 +816,8 @@ int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
}
-int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
+int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
+ size_t size)
{
u16 reg;
int err;
@@ -825,7 +826,16 @@ int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
if (err)
return err;
- reg |= PORT_CONTROL_2_JUMBO_10240;
+ reg &= ~PORT_CONTROL_2_JUMBO_MASK;
+
+ if (size <= 1522)
+ reg |= PORT_CONTROL_2_JUMBO_1522;
+ else if (size <= 2048)
+ reg |= PORT_CONTROL_2_JUMBO_2048;
+ else if (size <= 10240)
+ reg |= PORT_CONTROL_2_JUMBO_10240;
+ else
+ return -ERANGE;
return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
}