diff options
| author | Michael Chan <michael.chan@broadcom.com> | 2023-11-13 16:16:13 -0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-11-15 10:07:39 +0000 |
| commit | 9c0b06de6fb6f3b5871011aae19305b40084e037 (patch) | |
| tree | 7905435adb124f1add9b3ec9cd1a9657a5561b66 /drivers/net/ethernet/broadcom/bnxt/bnxt.h | |
| parent | 7845b8dfc7136752cdffe2acde43fa892ab4f0e0 (diff) | |
bnxt_en: Remove BNXT_RX_HDL and BNXT_TX_HDL
These 2 constants were used for the one RX and one TX completion
ring pointer in the cpr->cp_ring_arr fixed array. Now that we've
changed to allocating the array for the exact number of entries to
support more TX rings, we no longer use these constants.
The array index as well as the type of completion ring (RX/TX) are
now encoded in the handle for the completion ring. This will allow
us to locate the completion ring during NAPI for any number of
completion rings sharing the same MSIX. In the following patches,
we'll be adding support for more TX rings associated with the same
MSIX vector.
Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnxt/bnxt.h')
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnxt/bnxt.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.h b/drivers/net/ethernet/broadcom/bnxt/bnxt.h index c04089e7ac39..efb0db54575b 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.h @@ -543,6 +543,19 @@ struct nqe_cn { __le32 cq_handle_high; }; +#define BNXT_NQ_HDL_IDX_MASK 0x00ffffff +#define BNXT_NQ_HDL_TYPE_MASK 0xff000000 +#define BNXT_NQ_HDL_TYPE_SHIFT 24 +#define BNXT_NQ_HDL_TYPE_RX 0x00 +#define BNXT_NQ_HDL_TYPE_TX 0x01 + +#define BNXT_NQ_HDL_IDX(hdl) ((hdl) & BNXT_NQ_HDL_IDX_MASK) +#define BNXT_NQ_HDL_TYPE(hdl) (((hdl) & BNXT_NQ_HDL_TYPE_MASK) >> \ + BNXT_NQ_HDL_TYPE_SHIFT) + +#define BNXT_SET_NQ_HDL(cpr) \ + (((cpr)->cp_ring_type << BNXT_NQ_HDL_TYPE_SHIFT) | (cpr)->cp_idx) + #define DB_IDX_MASK 0xffffff #define DB_IDX_VALID (0x1 << 26) #define DB_IRQ_DIS (0x1 << 27) @@ -997,6 +1010,8 @@ struct bnxt_cp_ring_info { u8 had_work_done:1; u8 has_more_work:1; + u8 cp_ring_type; + u8 cp_idx; u32 last_cp_raw_cons; @@ -1023,8 +1038,6 @@ struct bnxt_cp_ring_info { int cp_ring_count; struct bnxt_cp_ring_info *cp_ring_arr; -#define BNXT_RX_HDL 0 -#define BNXT_TX_HDL 1 }; struct bnxt_napi { |