diff options
author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2023-01-19 18:04:30 +0200 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2023-01-23 13:13:09 +0000 |
commit | 12717decb570ea457b2baa5ad36758c0c967c306 (patch) | |
tree | 8751a482634e02ea0e2c0f4dc45192bdae29e23c /drivers/net/ethernet/freescale/enetc/enetc_pf.c | |
parent | 219355f1b093526fc980a202e4d48e8469c9a29c (diff) |
net: enetc: implement software lockstep for port MAC registers
Currently the enetc driver duplicates its writes to the PM0 registers
also to PM1, but it doesn't do this consistently - for example we write
to ENETC_PM0_MAXFRM but not to ENETC_PM1_MAXFRM.
Create enetc_port_mac_wr() which writes both the PM0 and PM1 register
with the same value (if frame preemption is supported on this port).
Also create enetc_port_mac_rd() which reads from PM0 - the assumption
being that PM1 contains just the same value.
This will be necessary when we enable the MAC Merge layer properly, and
the pMAC becomes operational.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/freescale/enetc/enetc_pf.c')
-rw-r--r-- | drivers/net/ethernet/freescale/enetc/enetc_pf.c | 71 |
1 files changed, 33 insertions, 38 deletions
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c index 1662e3f96285..70d6b13b3299 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c @@ -319,24 +319,23 @@ static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid) static void enetc_set_loopback(struct net_device *ndev, bool en) { struct enetc_ndev_priv *priv = netdev_priv(ndev); - struct enetc_hw *hw = &priv->si->hw; + struct enetc_si *si = priv->si; u32 reg; - reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE); + reg = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); if (reg & ENETC_PM0_IFM_RG) { /* RGMII mode */ reg = (reg & ~ENETC_PM0_IFM_RLP) | (en ? ENETC_PM0_IFM_RLP : 0); - enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg); + enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, reg); } else { /* assume SGMII mode */ - reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); + reg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); reg = (reg & ~ENETC_PM0_CMD_XGLP) | (en ? ENETC_PM0_CMD_XGLP : 0); reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) | (en ? ENETC_PM0_CMD_PHY_TX_EN : 0); - enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg); - enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg); + enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, reg); } } @@ -538,52 +537,50 @@ void enetc_reset_ptcmsdur(struct enetc_hw *hw) enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE); } -static void enetc_configure_port_mac(struct enetc_hw *hw) +static void enetc_configure_port_mac(struct enetc_si *si) { - enetc_port_wr(hw, ENETC_PM0_MAXFRM, - ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); + struct enetc_hw *hw = &si->hw; - enetc_reset_ptcmsdur(hw); + enetc_port_mac_wr(si, ENETC_PM0_MAXFRM, + ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE)); - enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | - ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); + enetc_reset_ptcmsdur(hw); - enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | - ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); + enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN | + ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC); /* On LS1028A, the MAC RX FIFO defaults to 2, which is too high * and may lead to RX lock-up under traffic. Set it to 1 instead, * as recommended by the hardware team. */ - enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); + enetc_port_mac_wr(si, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); } -static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode) +static void enetc_mac_config(struct enetc_si *si, phy_interface_t phy_mode) { u32 val; if (phy_interface_mode_is_rgmii(phy_mode)) { - val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); + val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK); val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG; - enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); + enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); } if (phy_mode == PHY_INTERFACE_MODE_USXGMII) { val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII; - enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); + enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); } } -static void enetc_mac_enable(struct enetc_hw *hw, bool en) +static void enetc_mac_enable(struct enetc_si *si, bool en) { - u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); + u32 val = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0; - enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val); - enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val); + enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, val); } static void enetc_configure_port_pmac(struct enetc_hw *hw) @@ -604,7 +601,7 @@ static void enetc_configure_port(struct enetc_pf *pf) enetc_configure_port_pmac(hw); - enetc_configure_port_mac(hw); + enetc_configure_port_mac(pf->si); enetc_port_si_configure(pf->si); @@ -996,14 +993,14 @@ static void enetc_pl_mac_config(struct phylink_config *config, { struct enetc_pf *pf = phylink_to_enetc_pf(config); - enetc_mac_config(&pf->si->hw, state->interface); + enetc_mac_config(pf->si, state->interface); } -static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex) +static void enetc_force_rgmii_mac(struct enetc_si *si, int speed, int duplex) { u32 old_val, val; - old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE); + old_val = val = enetc_port_mac_rd(si, ENETC_PM0_IF_MODE); if (speed == SPEED_1000) { val &= ~ENETC_PM0_IFM_SSP_MASK; @@ -1024,7 +1021,7 @@ static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex) if (val == old_val) return; - enetc_port_wr(hw, ENETC_PM0_IF_MODE, val); + enetc_port_mac_wr(si, ENETC_PM0_IF_MODE, val); } static void enetc_pl_mac_link_up(struct phylink_config *config, @@ -1036,6 +1033,7 @@ static void enetc_pl_mac_link_up(struct phylink_config *config, u32 pause_off_thresh = 0, pause_on_thresh = 0; u32 init_quanta = 0, refresh_quanta = 0; struct enetc_hw *hw = &pf->si->hw; + struct enetc_si *si = pf->si; struct enetc_ndev_priv *priv; u32 rbmr, cmd_cfg; int idx; @@ -1047,7 +1045,7 @@ static void enetc_pl_mac_link_up(struct phylink_config *config, if (!phylink_autoneg_inband(mode) && phy_interface_mode_is_rgmii(interface)) - enetc_force_rgmii_mac(hw, speed, duplex); + enetc_force_rgmii_mac(si, speed, duplex); /* Flow control */ for (idx = 0; idx < priv->num_rx_rings; idx++) { @@ -1083,24 +1081,21 @@ static void enetc_pl_mac_link_up(struct phylink_config *config, pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE; } - enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta); - enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta); - enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta); - enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta); + enetc_port_mac_wr(si, ENETC_PM0_PAUSE_QUANTA, init_quanta); + enetc_port_mac_wr(si, ENETC_PM0_PAUSE_THRESH, refresh_quanta); enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh); enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh); - cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG); + cmd_cfg = enetc_port_mac_rd(si, ENETC_PM0_CMD_CFG); if (rx_pause) cmd_cfg &= ~ENETC_PM0_PAUSE_IGN; else cmd_cfg |= ENETC_PM0_PAUSE_IGN; - enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg); - enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg); + enetc_port_mac_wr(si, ENETC_PM0_CMD_CFG, cmd_cfg); - enetc_mac_enable(hw, true); + enetc_mac_enable(si, true); } static void enetc_pl_mac_link_down(struct phylink_config *config, @@ -1109,7 +1104,7 @@ static void enetc_pl_mac_link_down(struct phylink_config *config, { struct enetc_pf *pf = phylink_to_enetc_pf(config); - enetc_mac_enable(&pf->si->hw, false); + enetc_mac_enable(pf->si, false); } static const struct phylink_mac_ops enetc_mac_phylink_ops = { |