diff options
| author | Lisheng <lisheng011@huawei.com> | 2016-03-31 21:00:09 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-04-02 20:17:14 -0400 |
| commit | 5ada37b53ea2b310df143b2c7d6c48fbf14d5cb8 (patch) | |
| tree | 9cca070b2da71b1a548a3bc612e9e52f42b5eaa1 /drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h | |
| parent | 7822ce73e659ab0c5dd8289f077efbcc4cd03164 (diff) | |
net: hns: add support of pause frame ctrl for HNS V2
The patch adds support of pause ctrl for HNS V2, and this feature is lost
by HNS V1:
1) service ports can disable rx pause frame,
2) debug ports can open tx/rx pause frame.
And this patch updates the REGs about the pause ctrl when updated
status function called by upper layer routine.
Signed-off-by: Lisheng <lisheng011@huawei.com>
Signed-off-by: Yisen Zhuang <Yisen.Zhuang@huawei.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h index 7d7204f45e78..7ff195e60b02 100644 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h @@ -137,6 +137,7 @@ #define DSAF_PPE_INT_STS_0_REG 0x1E0 #define DSAF_ROCEE_INT_STS_0_REG 0x200 #define DSAFV2_SERDES_LBK_0_REG 0x220 +#define DSAF_PAUSE_CFG_REG 0x240 #define DSAF_PPE_QID_CFG_0_REG 0x300 #define DSAF_SW_PORT_TYPE_0_REG 0x320 #define DSAF_STP_PORT_TYPE_0_REG 0x340 @@ -155,6 +156,7 @@ #define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG 0x1030 #define DSAF_INODE_SBM_PID_NUM_0_REG 0x1038 #define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x103C +#define DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x1024 #define DSAF_INODE_SBM_RELS_NUM_0_REG 0x104C #define DSAF_INODE_SBM_DROP_NUM_0_REG 0x1050 #define DSAF_INODE_CRC_FALSE_NUM_0_REG 0x1054 @@ -711,6 +713,10 @@ #define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1) #define DSAF_PFC_UNINT_CNT_S 0 +#define DSAF_MAC_PAUSE_RX_EN_B 2 +#define DSAF_PFC_PAUSE_RX_EN_B 1 +#define DSAF_PFC_PAUSE_TX_EN_B 0 + #define DSAF_PPE_QID_CFG_M 0xFF #define DSAF_PPE_QID_CFG_S 0 |